JPH0897419A - Mos type transistor and its manufacture - Google Patents

Abstract

PURPOSE: To acquire a MOSFET such that the reverse short channel effect is weakened and which can be further microminiaturized by making the level of the lower end of the source region different from that of the drain region. CONSTITUTION: The title MOS type transistor has a semiconductor substrate 1 with a groove, a gate electrode 5 which is buried in a surface of the semiconductor substrate 1 with an insulation film 4 therebetween and a source region 2 and a drain region 3 which are formed on both side-sides of a channel region of the semiconductor substrate 1 below the gate electrode 5 and have different depths.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS type transistor, and more particularly to a MOS type transistor which suppresses a change in threshold voltage due to miniaturization.

[0002]

2. Description of the Related Art Conventionally, MOS type transistors (hereinafter referred to as M
A trench MOSFET has been used in order to suppress the fluctuation of the threshold voltage due to the miniaturization of an OSFET).
FIG. 6 is a sectional view showing the structure of the trench MOSFET.

The trench MOSFET is a P-type silicon substrate 1
An N-type source region 2 and an N-type drain region 3 formed on the surface of the P-type silicon substrate 1, and a P-type silicon substrate 1.
The gate insulating film 4 is formed after the surface of the gate insulating film is hollowed out, and the gate electrode 5 is formed on the gate insulating film 4.

Next, the basic operation of this trench MOSFET will be described. In the conventional trench MOSFET, the P-type silicon substrate 1 and the N-type source region 2 are grounded, and the gate electrode 5 is applied with a constant positive voltage applied to the N-type drain region 3.
The voltage applied to is changed. Then, the gate insulating film 4
The density of the electrons generated at the interface between the and P-type silicon substrate 1 changes, and the current flowing through the N-type drain region 3 changes. In particular, the voltage applied to the gate electrode 5 when the current starts flowing in the drain region 3 is called a threshold voltage.

However, the conventional trench MOSFET has a problem that the threshold voltage fluctuates because the region (volume) of the depletion layer per unit gate increases with the miniaturization and the reverse short channel effect occurs.

[0006]

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a MOSFET that facilitates miniaturization by suppressing the reverse short channel effect.

[0007]

In order to achieve the above object, a first aspect of the present invention is to provide a semiconductor substrate having a groove, a gate electrode buried in the surface of the groove with an insulating film, and a gate electrode (3) A MOS transistor having a source region and a drain region which are formed so as to sandwich the channel region of the semiconductor substrate and have different depths.

A second aspect of the present invention is to provide a semiconductor substrate having a step on its surface, a gate electrode embedded in the step of the semiconductor substrate via an insulating film, and a channel region of the semiconductor substrate below the gate electrode. Provided is a MOS-type transistor having a source region and a drain region sandwiched between.

It is desirable that the source region and the drain region have substantially the same thickness. Third of the present invention
Includes a semiconductor substrate, a gate electrode embedded in the surface of the semiconductor substrate via an insulating film, and a source region and a drain region formed with a channel region of the semiconductor substrate below the gate electrode sandwiched therebetween. In a MOS transistor, in the operating state in which a threshold voltage is applied to the gate electrode and predetermined voltages are applied to the source region and the drain region, respectively, a lower end of a depletion layer formed in the source region, and Provided is a MOS transistor in which a lower end of a depletion layer formed in a channel region and a lower end of a depletion layer formed in the drain region are formed at substantially the same depth.

In a fourth aspect of the present invention, a step of forming a groove on the surface of the semiconductor substrate, a step of forming an insulating film on the inner surface of the groove of the semiconductor substrate, and a step of depositing polycrystalline silicon in the groove via the insulating film. Then, a step of forming a gate electrode, a step of forming a source / drain region by ion implantation on the entire surface of the semiconductor substrate with the groove interposed therebetween, and a step of forming a resist in the drain region by patterning, and then again forming an ion in the source region. Provided is a method for manufacturing a MOS transistor having a step of implanting.

A fifth aspect of the present invention is to form a groove on the surface of the semiconductor substrate, to form an insulating film on the surface of the semiconductor substrate, and to deposit polycrystalline silicon on the insulating film to form a gate electrode. And a step of etching the opening after patterning a resist having the source planned region as an opening, and a step of performing ion implantation on the entire surface after removing the resist. A method for manufacturing the same is provided.

[0012]

The reverse short channel effect of MOSFET can be understood from the idea of charge distribution. FIG. 7 is a schematic diagram showing the state of charge distribution in the conventional trench MOSFET shown in FIG.
The N-type source region 2 and the P-type silicon region 1 are grounded, and a positive drain voltage is applied to the N-type drain region 3,
A state in which a threshold voltage is applied to the gate electrode 5 is shown. The depletion layer formed on the P-type silicon substrate 1 is divided into the following three regions. That is, the depletion layer 6 formed by the N-type source region 2, the depletion layers 7, 9, 10 formed by the gate electrode 5, and the depletion layer 8 formed by the N-type drain region 3.

In order to suppress the reverse short channel effect, when the length of the gate electrode 5 is shortened, the amount of charges contained in the depletion layers 7, 9, 10 formed by the gate electrode 5 becomes smaller than that of the gate electrode 5. It is necessary to decrease in proportion to the length. That is, it is desirable to increase the region of the depletion layer 7 formed by the gate electrode 5 and remove the depletion layers 9 and 10 generated on the side surface of the gate electrode 5. This is because the regions of the depletion layers 9 and 10 hardly change even if the length of the gate electrode 5 is shortened.

The MOSFET of the present invention has an N-type source region 2
The regions of the depletion layers 9 and 10 can be simultaneously reduced by changing the heights of the lower end of the N type drain region and the lower end of the N-type drain region.

In the MOSFET of the present invention, the heights of the upper ends of the N-type source region 2 and the N-type drain region 3 are changed to change the heights of the N-type source region 2 and the N-type drain region 3.
Can be formed by the same manufacturing process.

[0016]

Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a sectional view showing the structure of an N-type MOSFET which is an embodiment of the MOSFET of the present invention.

This N-type MOSFET includes a P-type silicon substrate 1, an N-type source region 2 formed on the surface of a P-type silicon substrate, an N-type drain region 3 formed on the surface of a P-type silicon substrate, The gate insulating film 4 is formed on the surface of the P-type silicon substrate that is locally ground, and the gate electrode 5 is formed on the surface of the gate insulating film 4. Here, the lower end of the N-type source region 2 formed on the surface of the P-type silicon substrate is the N formed on the surface of the P-type silicon substrate.
It is deeper than the lower end of the mold drain region 3.

FIG. 2 is a sectional view showing a manufacturing process of this N-type MOSFET. A resist 11 having a channel region as an opening is patterned on the surface of the P-type silicon substrate 1. Next, the channel region of the P-type silicon substrate 1 is etched by the anisotropic etching method (FIG. 2A).
Next, after removing the resist 11, the P-type silicon substrate 1
The surface is thermally oxidized to form the gate insulating film 4 (see FIG. 2).
(B)). After that, polycrystalline silicon is deposited on the gate insulating film 4, phosphorus is diffused, and then a gate electrode 5 is formed by a planarization technique (FIG. 2C).

Next, phosphorus is applied to the entire surface of the substrate at an accelerating voltage of 15 kV,
Ion implantation is performed at a dose of 5 × 10 ¹⁵ cm ^-2 (Fig. 2
(D)). Further, after patterning the resist 12 having the N-type source region 2 as an opening, phosphorus is ion-implanted again with an acceleration voltage of 20 kV and a dose of 1 × 10 ¹⁵ cm ⁻² (FIG. 2E).

After that, the resist 12 is removed and 900
Phosphorus is activated by annealing at 1 ° C. for 1 hour to form the N-type source region 2 and the N-type drain region 3 (FIG. 2F).

According to the method of the present invention, it is easy to provide a difference in the depth of the lower ends of the source region and the drain region.
Therefore, the lower end of the depletion layer formed in the source and drain regions and the lower end of the depletion layer formed in the channel region can be formed at the same depth.

FIG. 3 shows the N-type MOSFET of this embodiment,
It is a figure which shows the effective gate length dependence of the threshold voltage of the groove | channel MOSFET by the prior art, and the surface type MOSFET by the prior art. A drain voltage of + 3V was applied to the drain electrode.

FIG. 6 shows a structural sectional view of a groove type MOSFET according to the prior art, and FIG. 8 shows a structural sectional view of a surface type MOSFET. In FIG. 6, the effective gate length is N, which is measured along the interface between the gate insulating film and the N-type silicon substrate.
The distance between the type source region and the N-type drain region. It can be seen from FIG. 3 that the reverse short channel effect is suppressed in the N-type MOSFET which is the MOSFET of this embodiment. That is, it is suitable for miniaturization of MOSFET.

FIG. 4 is a sectional view showing the structure of an N-type MOSFET which is another embodiment of the MOSFET of the present invention. This N-type MOSFET includes a P-type silicon substrate 1, an N-type source region 2 formed on the surface of the P-type silicon substrate, and a P-type silicon substrate.
-Type drain region 3 formed on the surface of a silicon substrate
And a gate insulating film 4 formed on the surface of the P-type silicon substrate which is locally ground, and a gate electrode 5 formed on the surface of the gate insulating film 4. Here, the upper end of the N-type source region 2 formed on the surface of the P-type silicon substrate is P
-Type drain region 3 formed on the surface of a silicon substrate
Lower than the top of.

FIG. 5 is a diagram showing a manufacturing process of the N-type MOSFET. A resist 11 having a channel region as an opening is patterned on the surface of the P-type silicon substrate 1. Next, the channel region of the P-type silicon substrate 1 is etched by the anisotropic etching method (FIG. 5A). next,
After removing the resist 11, the surface of the P-type silicon substrate 1 in the channel region is oxidized by a known method to form the gate insulating film 4 (FIG. 5B). After that, the gate insulating film 4
After depositing polycrystalline silicon on top of it and further diffusing phosphorus,
The gate electrode 5 is formed by the flattening technique (FIG. 5).
(C)).

Next, the resist 12 is patterned again, and the N-type source region is anisotropically etched to a depth of 0.1 μm (FIG. 5D). After that, the resist 12 is removed, phosphorus is ion-implanted at ¹⁵ kV and a dose amount of 5 × 10 ¹⁵ cm ^-2 , and annealing is performed at 900 ° C. for 1 hour to activate phosphorus, and the N-type source region 2 and The N-type drain region 3 is formed (FIG. 5E).

By pre-etching the source region according to the method of the present invention, the ion implantation in one step,
The lower end of the depletion layer formed in the source / drain regions and the lower end of the depletion layer formed in the channel region can have the same depth.

Also in this embodiment, the dependence of the threshold voltage on the effective gate length is as shown in FIG. Therefore, it is understood that the reverse short channel effect is suppressed in the N-type MOSFET which is the MOSFET of the present invention. That is, MOSFET
Suitable for miniaturization of. In addition, the present invention can be variously modified without departing from the scope of the invention.

[0029]

As described above, according to the present invention, it is possible to provide an easily miniaturized MOSFET in which the reverse short channel effect is suppressed by changing the heights of the lower end of the source region and the lower end of the drain region. it can.

[Brief description of drawings]

FIG. 1 is an MO according to one embodiment of a MOSFET of the present invention.
Sectional drawing of SFET.

FIG. 2 is an MO according to one embodiment of the MOSFET of the present invention.
Process sectional drawing of SFET.

FIG. 3 is a characteristic diagram showing the effective gate length dependence of the threshold voltage of the MOSFET of the present invention and the conventional groove-type and surface-type MOSFETs.

FIG. 4 shows an M according to another embodiment of the MOSFET of the present invention.
Sectional drawing of OSFET.

FIG. 5 shows an M according to another embodiment of the MOSFET of the present invention.
3 is a process sectional view of OSFET. FIG.

FIG. 6 is a cross-sectional view of a trench MOSFET according to a conventional technique.

FIG. 7 is a schematic diagram showing a charge distribution of a trench MOSFET according to a conventional technique.

FIG. 8 is a cross-sectional view of a surface type MOSFET according to a conventional technique.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... P-type silicon substrate 2 ... N-type source region 3 ... N-type drain region 4 ... Gate insulating film 5 ... Gate electrode 6 ... N-type source region 2 depletion layer Region 7 ... Depletion layer region that the gate electrode 5 covers 8 ... Depletion layer region that the N-type drain region 3 covers 9 ... Depletion layer region 1 on the side surface of the gate electrode 5 10 ... Gate electrode 5 Region of the depletion layer formed on the side surface of the wafer 2 11 ... Resist 12 ... Resist

Claims (6)

[Claims] 1. A semiconductor substrate having a groove portion, a gate electrode buried in the surface of the groove portion with an insulating film interposed therebetween, and a channel region of the semiconductor substrate below the gate electrode sandwiched between the semiconductor substrate and the respective depths. A MOS transistor having different source regions and drain regions. 2. A semiconductor substrate having a stepped surface, a gate electrode embedded in the stepped portion of the semiconductor substrate with an insulating film interposed therebetween, and a channel region of the semiconductor substrate below the gate electrode. A MOS transistor having a source region and a drain region. 3. The M of claim 2, wherein the source region and the drain region have substantially the same thickness.
OS type transistor. 4. A semiconductor substrate, a gate electrode embedded in the surface of the semiconductor substrate via an insulating film, and a source region and a drain region formed with a channel region of the semiconductor substrate below the gate electrode sandwiched therebetween. A lower end of a depletion layer formed in the source region in an operating state in which a threshold voltage is applied to the gate electrode and predetermined voltages are applied to the source region and the drain region, respectively. And a lower end of the depletion layer formed in the channel region and a lower end of the depletion layer formed in the drain region are formed at substantially the same depth. 5. A step of forming a groove on the surface of a semiconductor substrate,
A step of forming an insulating film on the inner surface of the semiconductor substrate groove, a step of depositing polycrystalline silicon via the insulating film in the groove to form a gate electrode, and a step of forming the groove by ion implantation on the entire surface of the semiconductor substrate. A method of manufacturing a MOS transistor, comprising: a step of forming a source / drain region sandwiched therebetween; and a step of patterning a resist in the drain region and then performing ion implantation in the source region again. 6. A step of forming a groove on the surface of a semiconductor substrate,
Forming an insulating film on the surface of the semiconductor substrate; depositing polycrystalline silicon on the insulating film to form a gate electrode; and patterning a resist having the source planned region as an opening, and then opening the opening. A method of manufacturing a MOS transistor, comprising: a step of etching a portion; and a step of performing ion implantation on the entire surface after removing the resist.