JPH0481339B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device.
This invention relates to a method for manufacturing a CMOS type semiconductor device.

[Technical background of the invention and its problems]

CMOS semiconductor devices have features such as low power consumption and large noise margins.
It is attracting attention as an important technology for the formation of future VLSIs. However, this device has an n-type substrate and a p-type substrate on one chip, and the circuit is constructed by interconnecting the p-channel and n-channel transistors formed on each substrate. There are still many problems with integration that need to be resolved. Particular problems arise in the well formation method and their separation. Not only is it difficult to miniaturize the well, but if it is formed near the well boundary, switching in the PnPn parasitic structure (so-called latch-up phenomenon) will occur. There were inconveniences such as the circuit being destroyed.

This problem will be explained below using a CMOS inverter as an example. FIGS. 1a to 1c are cross-sectional views showing a conventional CMOS inverter manufacturing process. First, the first
As ^shown in _FIG . Ion implantation is performed at a dose of ¹² [cm ^- ₂ ]. Here, 3 in the figure is an ion implantation region. Next, heat treatment was performed at 1200 [℃] for about 8 hours.
As shown in FIG. 1b, boron is diffused so that the bonding depth becomes 5 to 6 μm. This is the P-type diffusion layer p-well 4 formed in this manner. Next, the mask layer 2 is removed, and as shown in FIG.
b, P ⁺ diffusion layers 8a, 9a and N ⁺ which form gate electrodes 7a, 7b and become sources and drains;
Diffusion layers 8b, 9b, etc. are formed, and a p-channel transistor 10a and an n-channel transistor 1 are formed.
Form 0b. Thereafter, a CMOS inverter is formed by forming Al wiring and the like through an insulating film and making necessary electrical connections.

According to such a conventional method, when the p-well 4 having a junction depth of 5 to 6 [μm] is formed by thermally diffusing the ion-implanted boron, the boron also spreads in the lateral direction about 4 to 5 [μm]. μm] Due to the diffusion, the p-well region also expands laterally. Therefore, it has been difficult to form small wells with high precision. Also,
As shown in FIG. 1c, the drain 9a of the p-channel transistor 10a, the n-type substrate 1, the p-well 4, and the source 8 of the n-channel transistor 10b.
A pnpn parasitic structure is formed between b, and if this turns on during circuit operation, the circuit will be destroyed.
A so-called latch-up phenomenon occurs. In order to prevent this, it is necessary to provide a sufficient distance between the n ⁺ layer 9a (drain) and the n ⁺ layer 8b (source).
This was a major factor hindering the miniaturization of CMOS ICs. Note that the above-mentioned problem is not limited to CMOS inverters but also applies to various CMOS type semiconductor devices.

[Purpose of the invention]

An object of the present invention is to provide a semiconductor device that can form small wells with high precision, prevents latch-up, etc., and contributes to miniaturization and improved reliability of CMOS semiconductor devices. The purpose of this invention is to provide a method for manufacturing the same.

[Summary of the invention]

The gist of the present invention is to provide a groove between a well and a substrate or between wells, and to fill this groove with an insulating film.

That is, the present invention provides a method for manufacturing a semiconductor device by forming a well of a conductivity type opposite to that of the substrate in a part of the semiconductor substrate, and forming active elements on the well and the substrate, respectively. After forming one or more first layers outside the area,
A second coating is formed on the entire surface using a CVD method, and then the second coating on the side wall of the first coating is selectively removed by isotropic etching, and then the remaining second coating is removed. A trench is formed by selectively etching the substrate using the film as a mask, and then an insulating film is buried in the trench using the CVD method, and then, using the film and the insulating film as a mask, the substrate is doped with impurities of a conductivity type opposite to that of the substrate. This method involves doping.

The present invention also provides a method for forming a first well of a first conductivity type and a second well of a second conductivity type on a semiconductor substrate,
When manufacturing a semiconductor device by forming active elements on each of these wells, one or more first layers are formed on the second well formation region of the substrate, and then a first film is coated on the entire surface using a CVD method. 2 is formed, and then the stepped portion of the second coating on the side wall of the first coating is selectively removed by isotropic etching, and then the remaining second coating is used as a mask to remove the step portion of the second coating on the substrate. A groove is formed by selectively etching the groove, and then an insulating film is buried in the groove using a CVD method. Next, an impurity of a first conductivity type is injected onto the first well formation region using the first film and the insulating film as a mask. doping, then forming a third coating on the first well formation region, and then forming a third coating on the first well formation region;
In this method, the second conductive type impurity is doped onto the second well forming region using the third coating as a mask.

〔Effect of the invention〕

According to the present invention, since the lateral extent of the well is defined by the insulating film embedded in the groove, a small well can be formed with high precision. Further, since the second film is a CVD film, by using isotropic etching such as wet etching, the second film on the side wall portion of the first film can be selectively removed with good controllability. As a result, a mask pattern with high dimensional accuracy can be obtained, grooves with small hole diameters can be formed, and a wide element formation area can be obtained. Furthermore, since each element is reliably isolated by the insulating film embedded in the groove, latch-up phenomena and the like are not caused. Furthermore, since the insulating film is formed by the CVD method, there is no fear that the substrate will be damaged by heat, unlike the thermal oxidation method. Therefore,
It is extremely effective in miniaturizing CMOS semiconductor devices and improving their reliability.

[Embodiments of the invention]

Figures 2a to 2h relate to the first embodiment of the present invention.
FIG. 3 is a cross-sectional view showing a CMOS inverter manufacturing process.
First, as shown in FIG. 2a, a thermal oxide film (SiO ₂ film) 12 is placed on an n-type silicon substrate (semiconductor substrate) 11.
A first film consisting of the Si ₃ N ₄ film 13 and the Si _{3 N 4 film 13 is formed to a thickness of, for example, 1000 [Å], and then, for example, a phytoresist 14 is selectively formed, and using this resist 14 as a mask, the Si 3} N 4 film 13 and the Si 3 N ₄ film 13 and _siO2 membrane 12
Remove by etching. Next, as shown in FIG. 2b, for example, a plasma SiO ₂ film (second film) is applied to the entire surface.
15 with a thickness of about 10 [μm]. This sample is then etched with, for example, NH ₄ F for about 20 to 30 seconds, as shown in Figure 2c.
As shown in Fig. 2, plasma SiO ₂ 1 is generated only at the step part.
5 is removed by etching.

Next, the photoresist film 14 is removed and the plasma SiO ₂ film 15 on the resist 14 is removed by lift-off. Next, as shown in FIG. 2d, the Si ₃ H ₄ film 13 and the remaining plasma SiO ₂ film 1 are removed.
5 as a mask, the silicon substrate 11 is selectively etched by an anisotropic etching method to form a groove 16 at a depth of 5 to 10 μm around the pattern of the first film. Next, plasma SiO ₂ film 15
After removing it by etching, for example, a CVD SiO ₂ film (insulating film) 17 is deposited on the entire surface as shown in Fig. 2e.
It is deposited to a thickness of 2000 Å, filling the groove 16 and simultaneously covering the entire surface. Next, the entire surface is etched using a directional etching method, and the SiO ₂ film 17 is approximately etched.
When 2000 [Å] is removed, the groove 16 is filled with the SiO ₂ film 17, as shown in FIG. 2f. Next, using the Si ₃ N ₄ film 13 and the SiO ₂ film as a mask,
A p-well 18 is formed by diffusing boron (B ⁺ ).
Here, the boron diffusion described above may be vapor phase diffusion using boron nitride, or may be a combination of boron ion implantation and drive-in diffusion.

Next, as shown in FIG. 2g, the Si ₃ N ₄ film 13 and
The SiO ₂ film 12 is removed. Then, as shown in FIG. 2h, a field oxide film 19 and a gate oxide film 20 are formed.
a, 20b, gate electrodes 21a, 21b, p ⁺ diffusion layers 22a, 23a, and N ⁺ diffusion layers 22b, 23b, which will become sources and drains, are formed. Thereafter, a CMOS inverter is manufactured by forming an interlayer insulating film, Al wiring, etc. in the same manner as in the conventional method.

Thus, according to the method of this embodiment, the p-well 18
During the diffusion process to form SiO ₂ on both sides
Since boron is surrounded by the film 17, it does not diffuse laterally. Therefore, a fine p-well region can be easily formed. Furthermore, even if the source or drain 23a of the p-channel transistor and the source or drain 22b of the n-channel transistor are placed close to each other as shown in _FIG . Because they are separated from each other, the latch-up phenomenon can be made as difficult to occur as, or even more difficult than, the conventional method in which the structures are sufficiently spaced apart. Therefore, miniaturization of CMOS inverters could be realized extremely easily. Various methods have been tried to achieve well isolation by forming the grooves 16 described above, but the mask forming process for forming the grooves and the process for performing p-well diffusion are difficult. Since each mask forming process was performed separately, the process became complicated, and it was also disadvantageous in forming a finer p-well. On the other hand, in this embodiment, the mask forming process for forming the groove can be performed by self-alignment, and the mask for p-well diffusion is also used as a mask for forming the groove, so the process It also has the advantage that it becomes extremely easy to use.

FIGS. 3a and 3b are process sectional views relating to the second embodiment. This embodiment differs from the first embodiment described above in that a π-type substrate 31 is used as the semiconductor substrate. That is, the π-type substrate 3
1, the steps up _{to FIG .}
A film) 32 is formed. Next, Si ₃ N ₄ film 13 and
After removing the SiO ₂ film 12, as shown in FIG. 3b, the substrate 31 is removed using the SiO ₂ film (third film) 32 formed by selective oxidation of n-type impurities such as arsenic (As) as a mask. to form an n-well 33. As a result, an n-well 3 is formed on the π-type substrate 31.
A structure is realized in which the P-well 3 and the P-well 18 can be formed at the same time, and these are separated by the SiO ₂ film 32.

Therefore, it goes without saying that this embodiment also provides the same effects as the first embodiment. Note that the formation order of the p-well and n-well may be reversed. In addition, using the n-type substrate 11 as the substrate as in the previous embodiment, the oxide film 32 is
For example, the ion implantation is performed using a mask as the n-type substrate 1.
1 may be performed for the purpose of preventing field inversion and controlling the threshold value of the channel section. In this case, for example, As ion implantation is used to
Ion implantation may be performed at 100 KV with a dose in the range of 5×10 ¹¹ to 10 ¹³ .

FIG. 4 is a cross-sectional view of the process according to the third embodiment. This embodiment is an improvement of the first embodiment, in which n-type impurity ions are implanted into the bottom of the groove 16 in the step shown in FIG. A case where it is formed inside the substrate 11 is shown. With this structure, the shape of the air layer on the n-substrate 11 side of the air layer at the interface of the p-well 18 is as shown by the broken line in FIG. That is, since the expansion of the air layer is prevented by the high concentration layer 41, the withstand voltage for latch-up and punch-through can be further increased.

Note that the present invention is not limited to the embodiments described above. In the first embodiment, plasma
Although selective etching of the silicon substrate 11 was performed after removing the SiO ₂ film 15 by lift-off, this need not necessarily be performed. That is, the silicon substrate 11 may be etched in the state shown in FIG. 2c. Furthermore, although the CVD SiO ₂ film 15 was deposited to fill the trench with an insulating film, thermal oxidation may be performed instead. Further, although the remaining plasma SiO ₂ film 17 is removed and then the trench 16 is filled with an insulator, it may also be filled before the SiO ₂ film 15 is removed, that is, at the stage shown in FIG. 2d. Furthermore, although the explanation has been made using resist/Si ₃ N ₄ /SiO ₂ as the first film,
Any other combination may be used. For example, Al may be used instead of the resist, or a SiO ₂ film or a si ₃ N ₄ film alone may be used. In addition, although we have only described the case of a plasma SiO ₂ film as a film in which the etching rate at the step part is faster than the etching rate at the flat part, other films such as plasma Si ₃ N ₄ , plasma PSG film, or deposited by sputtering may be used. It may also be a film of SiO ₂ , Si ₃ N ₄ , PSG film, or the like.
Furthermore, the same effect can be obtained by using the remaining Al pattern by removing the thinned film at the stepped portion by isotropic etching using Al vapor deposition. Further, it does not depart from the spirit of the present invention even if the mask material is left as shown in FIG. 2d by using a mask alignment process without using any film having such properties. In addition, in FIG. 2h, the illustrated n-channel transistor and the p-
Although the well isolation oxide film 17 is used as is for isolation from the channel transistor, a field oxide film may also be used for isolation. Furthermore, the field oxide film may be formed using any method, such as the so-called conventional LOCOS method,
Needless to say, any method such as a method using a buried oxide film may be used. In short, the present invention can be implemented with various modifications without departing from the gist thereof.

[Brief explanation of the drawing]

FIGS. 1a to 1c are cross-sectional views showing a conventional CMOS inverter manufacturing process. 2A to 2H are cross-sectional views showing the CMOS inverter manufacturing process according to the first embodiment of the present invention, FIGS. 3A to 3B are cross-sectional views of the process according to the second embodiment, and FIG. It is a process sectional view concerning an example. DESCRIPTION OF SYMBOLS 11... N-type silicon substrate, 12... Thermal oxide film (SiO ₂ film), 13... Si ₃ N ₄ film, 14... Resist, 15... Plasma SiO ₂ film, 16... Groove,
17...CVD SiO ₂ film (insulating film), 18... Well, 20a, 20b... Gate oxide film, 21a,
21b...gate electrode, 22a, 22b, 23
a, 23b... Source/drain, 31... π type substrate, 32... Oxide film (SiO ₂ film), 33... N well, 41... High concentration impurity layer.

Claims (1)

[Scope of Claims] 1. A method for manufacturing a semiconductor device in which a well of a conductivity type opposite to that of the substrate is formed in a part of a semiconductor substrate, and active elements are formed on this well and the substrate, respectively. a step of forming a first film outside the well formation region; a step of forming a second film on the entire surface using CVD; and a step of forming the second film on the side wall of the first film by isotropic etching. a step of selectively removing a film; a step of selectively etching the substrate using the remaining second film as a mask to form a groove; a step of embedding an insulating film in the groove using a CVD method; 1. A method of manufacturing a semiconductor device, comprising the step of doping the substrate with an impurity of a conductivity type opposite to that of the substrate using a film and an insulating film as a mask. 2. The step of forming grooves by selectively etching the substrate includes forming a second coating on the entire surface of the substrate on which the coating is formed, the etching rate of which is higher in the stepped portions than the etching rate of the flat portions, and then etching the entire surface. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the step portion of the second coating is removed, and then the remaining second coating is used as a part of a mask to selectively etch the substrate. . 3. In a method for manufacturing a semiconductor device, in which a first well of a first conductivity type and a second well of a second conductivity type are formed on a semiconductor substrate, and active elements are formed on each of these wells, the second well of the substrate a step of forming a first film on the formation region, a step of forming a second film on the entire surface using a CVD method, and a step of forming the second film on the side wall portion of the first film by isotropic etching. a step of selectively etching the substrate using the remaining second film as a mask to form a groove portion; a step of filling the groove portion with an insulating film using a CVD method; a step of doping impurities of a first conductivity type onto a first well formation region using the first film and an insulating film as a mask; a step of forming a third film on the first well formation region; A method for manufacturing a semiconductor device, comprising the steps of: removing the third coating; and doping an impurity of a second conductivity type onto the second well formation region using the third coating as a mask. 4. The step of selectively etching the substrate to form grooves is performed after forming a second coating on the entire surface of the substrate on which the first coating is formed, the etching rate of which is higher in the stepped portions than in the flat portions. 3. The semiconductor device according to claim 3, wherein etching is performed on the entire surface to remove the stepped portion of the second film, and then the remaining second film is used as a part of a mask to selectively etch the substrate. manufacturing method. 5. The semiconductor device according to claim 3 or 4, wherein the third coating is formed by selective oxidation of the substrate, and the first coating includes an oxidation-resistant film. manufacturing method.