JPS55154748A - Complementary mos semiconductor device - Google Patents

Complementary mos semiconductor device

Info

Publication number
JPS55154748A
JPS55154748A JP6345279A JP6345279A JPS55154748A JP S55154748 A JPS55154748 A JP S55154748A JP 6345279 A JP6345279 A JP 6345279A JP 6345279 A JP6345279 A JP 6345279A JP S55154748 A JPS55154748 A JP S55154748A
Authority
JP
Japan
Prior art keywords
groove
layer
substrate
type
implanted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6345279A
Other languages
Japanese (ja)
Inventor
Yoshihide Nagakubo
Susumu Kayama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP6345279A priority Critical patent/JPS55154748A/en
Publication of JPS55154748A publication Critical patent/JPS55154748A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To obtain a C-MOS device having extremely high integration degree by forming a groove having deeper depth than a p-well layer and less than 4mum of width in the boundary between an n-type substrate and the p-well layer and filling a thermal oxide film in the groove. CONSTITUTION:A resist mask 12 having an opening including a width of 1.5mum is coated on an n-type Si substrate 11, Ar ion is implanted through the opening to form a groove 13 having a depth of approx. 10mum (deeper than a p-well layer), P ion is implanted to the bottom of the groove 13 to form a field inversion preventive layer 14 thereon. The mask 12 is then removed, and the substrate is wet oxidized to form an SiO2 film 15 and to fill the SiO2 16 in the groove 13. Thereafter, the film 15 is removed with NH4F to form an isolation layer 17 at the groove. Subsequently, B ion is implanted to form a p-well 18 having a depth of approx. 9mum shallower than the layer 17. Then, a p<+>-type layer is formed in the substrate 11, and a n<+>-type layer is formed in the p-well layer to form a C-MOSFET. According to this configuration, both of FETs are extremely approached without deteriorating the operating properties of the FETs with flat surface without disconnection.
JP6345279A 1979-05-23 1979-05-23 Complementary mos semiconductor device Pending JPS55154748A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6345279A JPS55154748A (en) 1979-05-23 1979-05-23 Complementary mos semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6345279A JPS55154748A (en) 1979-05-23 1979-05-23 Complementary mos semiconductor device

Publications (1)

Publication Number Publication Date
JPS55154748A true JPS55154748A (en) 1980-12-02

Family

ID=13229636

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6345279A Pending JPS55154748A (en) 1979-05-23 1979-05-23 Complementary mos semiconductor device

Country Status (1)

Country Link
JP (1) JPS55154748A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS592346A (en) * 1982-06-28 1984-01-07 Semiconductor Res Found Semiconductor integrated circuit
JPS5932163A (en) * 1982-08-18 1984-02-21 Nec Corp C-mos integrated circuit
JPS5940563A (en) * 1982-08-31 1984-03-06 Toshiba Corp Manufacture of semiconductor device
JPS59121865A (en) * 1982-12-28 1984-07-14 Toshiba Corp Manufacture of complementary semiconductor device
JPS6450540A (en) * 1987-08-21 1989-02-27 Nec Corp Isolation of microelement
US4868136A (en) * 1985-08-28 1989-09-19 Sgs-Thomson Microelectronics S.R.L. Process of forming an isolation structure
US6649951B2 (en) 1999-02-25 2003-11-18 Canon Kabushiki Kaisha Light-receiving element and photoelectric conversion device
KR20030096703A (en) * 2002-06-17 2003-12-31 주식회사 하이닉스반도체 method for fabricating semicinductor device

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0427706B2 (en) * 1982-06-28 1992-05-12 Handotai Kenkyu Shinkokai
JPS592346A (en) * 1982-06-28 1984-01-07 Semiconductor Res Found Semiconductor integrated circuit
JPS5932163A (en) * 1982-08-18 1984-02-21 Nec Corp C-mos integrated circuit
JPS6255309B2 (en) * 1982-08-18 1987-11-19 Nippon Electric Co
JPS5940563A (en) * 1982-08-31 1984-03-06 Toshiba Corp Manufacture of semiconductor device
JPH0481339B2 (en) * 1982-08-31 1992-12-22 Tokyo Shibaura Electric Co
JPH0481340B2 (en) * 1982-12-28 1992-12-22 Tokyo Shibaura Electric Co
JPS59121865A (en) * 1982-12-28 1984-07-14 Toshiba Corp Manufacture of complementary semiconductor device
US4868136A (en) * 1985-08-28 1989-09-19 Sgs-Thomson Microelectronics S.R.L. Process of forming an isolation structure
JPS6450540A (en) * 1987-08-21 1989-02-27 Nec Corp Isolation of microelement
US6649951B2 (en) 1999-02-25 2003-11-18 Canon Kabushiki Kaisha Light-receiving element and photoelectric conversion device
US7235831B2 (en) 1999-02-25 2007-06-26 Canon Kabushiki Kaisha Light-receiving element and photoelectric conversion device
KR20030096703A (en) * 2002-06-17 2003-12-31 주식회사 하이닉스반도체 method for fabricating semicinductor device

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