JPS56111241A - Preparation of semiconductor device - Google Patents
Preparation of semiconductor deviceInfo
- Publication number
- JPS56111241A JPS56111241A JP1126780A JP1126780A JPS56111241A JP S56111241 A JPS56111241 A JP S56111241A JP 1126780 A JP1126780 A JP 1126780A JP 1126780 A JP1126780 A JP 1126780A JP S56111241 A JPS56111241 A JP S56111241A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- mask
- reactive ion
- ion etching
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
PURPOSE:To obtain a device of higher integration and improved properties, by forming a field oxidized film on a substrate surface without employing the selective oxidation method, forming selectively an inversion preventing layer to the said portion and preventing oozing to the device region. CONSTITUTION:An SiO2 12, a polycrystalline Si 13 are stacked on a P type Si substrate 11, and a resist mask 14 is coated to form P<+> layer 15 by B ion implantation. After removal of the mask 14 and the evaporation of Al 16, the layer 13 is removed by a reactive ion etching. Then with the Al 16 as a mask, the SiO2 12 is etched by a reactive ion etching for an opening and the Al 16 is exfoliated. Because of the reactive ion etching, side etching on the oxidized film 12 is virtually zero. Moreover, as no oozing by ion implantation takes place on the P<+> layer, a minute device forming region as designed can be obtained. Therefore, by employing the conventional method to form a MOSFET, a device of higher integration and improved properties can be obtained.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1126780A JPS56111241A (en) | 1980-02-01 | 1980-02-01 | Preparation of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1126780A JPS56111241A (en) | 1980-02-01 | 1980-02-01 | Preparation of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56111241A true JPS56111241A (en) | 1981-09-02 |
Family
ID=11773182
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1126780A Pending JPS56111241A (en) | 1980-02-01 | 1980-02-01 | Preparation of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56111241A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61500046A (en) * | 1983-09-30 | 1986-01-09 | ヒュ−ズ・エアクラフト・カンパニ− | Method of manufacturing MOSFET devices |
JPH05243373A (en) * | 1984-05-15 | 1993-09-21 | Digital Equip Corp <Dec> | Method for manufacturing integrated circuit chip |
CN103746045A (en) * | 2014-02-10 | 2014-04-23 | 中国电子科技集团公司第四十四研究所 | Method for inhibiting surface high-temperature inversion of P-type super-high-resistance monocrystalline silicon material |
-
1980
- 1980-02-01 JP JP1126780A patent/JPS56111241A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61500046A (en) * | 1983-09-30 | 1986-01-09 | ヒュ−ズ・エアクラフト・カンパニ− | Method of manufacturing MOSFET devices |
JPH05243373A (en) * | 1984-05-15 | 1993-09-21 | Digital Equip Corp <Dec> | Method for manufacturing integrated circuit chip |
CN103746045A (en) * | 2014-02-10 | 2014-04-23 | 中国电子科技集团公司第四十四研究所 | Method for inhibiting surface high-temperature inversion of P-type super-high-resistance monocrystalline silicon material |
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