JPS56158446A - Manufacture of semiconductor integrated circuit - Google Patents

Manufacture of semiconductor integrated circuit

Info

Publication number
JPS56158446A
JPS56158446A JP6324780A JP6324780A JPS56158446A JP S56158446 A JPS56158446 A JP S56158446A JP 6324780 A JP6324780 A JP 6324780A JP 6324780 A JP6324780 A JP 6324780A JP S56158446 A JPS56158446 A JP S56158446A
Authority
JP
Japan
Prior art keywords
layers
films
si3n4
polycrystalline
sio2
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6324780A
Other languages
Japanese (ja)
Inventor
Tadanaka Yoneda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP6324780A priority Critical patent/JPS56158446A/en
Publication of JPS56158446A publication Critical patent/JPS56158446A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To obtain a minute isolation layer of the semiconductor integrated circuit by a method wherein BSG films are provided selectively, an epitaxial layer is accumulated thereon, the half thickness of the polycrystalline Si layers are removed to form grooves, the side walls of the grooves are converted into SiO2 films by heating, and N<+> type layers are formed simultaneously under the BSG films. CONSTITUTION:The BSG films 22 are provided selectively on a P type Si substrate 20 having N<+> type buried layers 21, and when an N type epitaxial layer 23 is accumulated thereon, the polycrystalline Si layers 24 are formed on the BSG films. An SiO2 film 25 ane an Si3N4 film 26 are accumulated thereon, openings are formed in the Si3N4 film 26 and the SiO2 film 25 by CF4 plasma applying a resist mask 27 to etch the half thickness of the polycrystalline Si layer 24 to form the grooves 28. The surface is covered with an Si3N4 film 29 and sputter etching is performed in the vertical direction using CF4 gas to remain the Si3N4 films on the side walls. Ar ions are implanted to accelerate the speed of oxidation of the polycrystalline Si layers 24', and wet oxidation is performed to convert thereof into the SiO2 layers 30. At this time, P<+> layers 31 are formed directly under the BSG films 22. The Si3N4 films 26 are removed, and various kind of IC's are formed in the epitaxial layer 23. By this constitution, the area of the isolation layer can be made as small, and density of integration can be enhanced because of the flatness of the surface.
JP6324780A 1980-05-12 1980-05-12 Manufacture of semiconductor integrated circuit Pending JPS56158446A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6324780A JPS56158446A (en) 1980-05-12 1980-05-12 Manufacture of semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6324780A JPS56158446A (en) 1980-05-12 1980-05-12 Manufacture of semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS56158446A true JPS56158446A (en) 1981-12-07

Family

ID=13223714

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6324780A Pending JPS56158446A (en) 1980-05-12 1980-05-12 Manufacture of semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS56158446A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6165447A (en) * 1984-09-07 1986-04-04 Mitsubishi Electric Corp Manufacture of semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6165447A (en) * 1984-09-07 1986-04-04 Mitsubishi Electric Corp Manufacture of semiconductor device
JPH0522387B2 (en) * 1984-09-07 1993-03-29 Mitsubishi Electric Corp

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