JPS55107244A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS55107244A
JPS55107244A JP1387379A JP1387379A JPS55107244A JP S55107244 A JPS55107244 A JP S55107244A JP 1387379 A JP1387379 A JP 1387379A JP 1387379 A JP1387379 A JP 1387379A JP S55107244 A JPS55107244 A JP S55107244A
Authority
JP
Japan
Prior art keywords
layer
poly
selectively
thin
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1387379A
Other languages
Japanese (ja)
Inventor
Yoshihide Nagakubo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP1387379A priority Critical patent/JPS55107244A/en
Publication of JPS55107244A publication Critical patent/JPS55107244A/en
Pending legal-status Critical Current

Links

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: To increase integration degree by a method wherein a poly-Si layer uniformly formed is selectively etched to form a thin layer portion and a highly resistance element in that portion.
CONSTITUTION: An element isolating region 23 is made by selectively oxidizing a Si substrate 21, and a poly-Si layer 24 is accumulated on the substrate after the formation of an oxide gate film. Next by providing a resist mask 25, ion injection is added to the surface layer while selecting the quantity of addition and energy. If the mask is removed and plasma etching is added, a thin layer portion can be made selectively in the ion-injected portion by means of difference in etching speed. The surface is then etched while providing a resist mask 26 so as to make a window selectively in the poly-Si layer 24. By this method, it is possible to control the quantity of injection ions and form a thin poly-Si layer with the resistance value desired readily and accurately in the region specified.
COPYRIGHT: (C)1980,JPO&Japio
JP1387379A 1979-02-09 1979-02-09 Manufacture of semiconductor device Pending JPS55107244A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1387379A JPS55107244A (en) 1979-02-09 1979-02-09 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1387379A JPS55107244A (en) 1979-02-09 1979-02-09 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS55107244A true JPS55107244A (en) 1980-08-16

Family

ID=11845342

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1387379A Pending JPS55107244A (en) 1979-02-09 1979-02-09 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS55107244A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62299050A (en) * 1986-06-18 1987-12-26 Sanyo Electric Co Ltd Manufacture of semiconductor device
US5436177A (en) * 1992-08-19 1995-07-25 Sgs-Thomson Microelectronics S.R.L. Process for forming implanted regions with lowered channeling risk on semiconductors

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62299050A (en) * 1986-06-18 1987-12-26 Sanyo Electric Co Ltd Manufacture of semiconductor device
US5436177A (en) * 1992-08-19 1995-07-25 Sgs-Thomson Microelectronics S.R.L. Process for forming implanted regions with lowered channeling risk on semiconductors

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