JPS5764973A - Manufacture os semiconductor device - Google Patents
Manufacture os semiconductor deviceInfo
- Publication number
- JPS5764973A JPS5764973A JP14133780A JP14133780A JPS5764973A JP S5764973 A JPS5764973 A JP S5764973A JP 14133780 A JP14133780 A JP 14133780A JP 14133780 A JP14133780 A JP 14133780A JP S5764973 A JPS5764973 A JP S5764973A
- Authority
- JP
- Japan
- Prior art keywords
- mask
- film
- gate
- diffusion layer
- oxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title abstract 2
- 238000004519 manufacturing process Methods 0.000 title 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 4
- 238000009792 diffusion process Methods 0.000 abstract 3
- 229910052681 coesite Inorganic materials 0.000 abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract 2
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract 2
- 229910052682 stishovite Inorganic materials 0.000 abstract 2
- 229910052905 tridymite Inorganic materials 0.000 abstract 2
- 238000000034 method Methods 0.000 abstract 1
- 238000001020 plasma etching Methods 0.000 abstract 1
- 239000000758 substrate Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
Abstract
PURPOSE:To obtain the Si gate MOS device having a short effective channel length for the subject semiconductor device by a method wherein a shallow diffusion layer having the desired low density is formed in the vicinity of a gate electrode without using an SiO2 mask on a polycrystalline Si. CONSTITUTION:A field oxide film 22 and a gate oxide film 23 are provided on a P type si substrate 21 and a polycrystalline Si 24 is superposed. A resist mask 26 is provided, films 23 and 24 are etched and an isotropic plasma etching is performed on the side face of the film 24. When the mask 26 is removed and an ion is implanted 28, an N layer 27a and an N<-> layer 27b are formed simultaneously. Lastly, the above is covered by n SiO2 film 29. According to this constitution, as a gate oxide film is used as a mask, the control of film thickness is performed easily, a diffusion layer can be formed accurately and an ion can be implanted at low accelerating voltage. By the drop of accelerating voltage., a diffusion layer with the density distribution having a sharp peak in shallow depth can be formed and a small typed Si gate FET having short effective channel length can be obtained.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14133780A JPS5764973A (en) | 1980-10-09 | 1980-10-09 | Manufacture os semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14133780A JPS5764973A (en) | 1980-10-09 | 1980-10-09 | Manufacture os semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5764973A true JPS5764973A (en) | 1982-04-20 |
Family
ID=15289601
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14133780A Pending JPS5764973A (en) | 1980-10-09 | 1980-10-09 | Manufacture os semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5764973A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6230374A (en) * | 1985-07-31 | 1987-02-09 | Toshiba Corp | Semiconductor device |
| US4818715A (en) * | 1987-07-09 | 1989-04-04 | Industrial Technology Research Institute | Method of fabricating a LDDFET with self-aligned silicide |
| US4906589A (en) * | 1989-02-06 | 1990-03-06 | Industrial Technology Research Institute | Inverse-T LDDFET with self-aligned silicide |
| US5015598A (en) * | 1989-11-03 | 1991-05-14 | U.S. Philips Corporation | Method of manufacturing a device comprising MIS transistors having a gate electrode in the form of an inverted "T" |
| JPH07226518A (en) * | 1994-02-10 | 1995-08-22 | Semiconductor Energy Lab Co Ltd | Manufacture of semiconductor device |
-
1980
- 1980-10-09 JP JP14133780A patent/JPS5764973A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6230374A (en) * | 1985-07-31 | 1987-02-09 | Toshiba Corp | Semiconductor device |
| US4818715A (en) * | 1987-07-09 | 1989-04-04 | Industrial Technology Research Institute | Method of fabricating a LDDFET with self-aligned silicide |
| US4906589A (en) * | 1989-02-06 | 1990-03-06 | Industrial Technology Research Institute | Inverse-T LDDFET with self-aligned silicide |
| US5015598A (en) * | 1989-11-03 | 1991-05-14 | U.S. Philips Corporation | Method of manufacturing a device comprising MIS transistors having a gate electrode in the form of an inverted "T" |
| JPH07226518A (en) * | 1994-02-10 | 1995-08-22 | Semiconductor Energy Lab Co Ltd | Manufacture of semiconductor device |
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