JPS5696865A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5696865A
JPS5696865A JP17320579A JP17320579A JPS5696865A JP S5696865 A JPS5696865 A JP S5696865A JP 17320579 A JP17320579 A JP 17320579A JP 17320579 A JP17320579 A JP 17320579A JP S5696865 A JPS5696865 A JP S5696865A
Authority
JP
Japan
Prior art keywords
type
ions
injected
oxide film
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17320579A
Other languages
Japanese (ja)
Inventor
Kazunori Imaoka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP17320579A priority Critical patent/JPS5696865A/en
Publication of JPS5696865A publication Critical patent/JPS5696865A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To obtain the semiconductor device having the same advantages as an MIS device having a V-shaped groove by forming a recess without using forming means with chemicals such as anisotropic etching or the like. CONSTITUTION:A p type epitaxial layer 21 is superposed on an n<+> type Si substrate 20, an Si3N4 mask 23 is formed on an SiO2 thin film 22 using a resist 24, ions are injected thereto, and a p type layer 25 is formed thereon. The resist is removed, a field oxide film 26 is formed thereon, ions are injected thereonto, and an n<+> type layer 27 is formed thereon. An Si3N4 mask 28 is formed again thereon, and the film 26 is etched and removed. A thick oxide film 29 is formed again thereon, and the lower end is arrived at the n<+> type substrate 20. Then, the layer 25 is partly divided into channels 25C. The films 29, 23, 28 are etched, a gate oxide film 30 is formed in the recess, B ions are injected thereto, the threshold value is adjusted, a gate electrode 31 is formed thereafter thereon, a PSG32 is covered thereon, and electrodes 33D, 33G are attached thereon. According to this configuration no contamination with chemicals occurs, the selection of planar azimuth is unnecessary, and the device having the same advantages as the MIS with V-shaped groove can be obtained.
JP17320579A 1979-12-30 1979-12-30 Manufacture of semiconductor device Pending JPS5696865A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17320579A JPS5696865A (en) 1979-12-30 1979-12-30 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17320579A JPS5696865A (en) 1979-12-30 1979-12-30 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5696865A true JPS5696865A (en) 1981-08-05

Family

ID=15956053

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17320579A Pending JPS5696865A (en) 1979-12-30 1979-12-30 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5696865A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60124970A (en) * 1983-12-10 1985-07-04 Matsushita Electronics Corp Manufacture of fet
WO1993003502A1 (en) * 1991-07-26 1993-02-18 Nippondenso Co., Ltd. Method of producing vertical mosfet
US5470770A (en) * 1994-03-31 1995-11-28 Nippondenso Co., Ltd. Manufacturing method of semiconductor device
US5672524A (en) * 1995-08-01 1997-09-30 Advanced Micro Devices, Inc. Three-dimensional complementary field effect transistor process
US5877527A (en) * 1996-04-26 1999-03-02 Denso Corporation Semiconductor device and method of producing the same
US5920784A (en) * 1994-06-08 1999-07-06 Samsung Electronics Co., Ltd. Method for manufacturing a buried transistor
US6015737A (en) * 1991-07-26 2000-01-18 Denso Corporation Production method of a vertical type MOSFET
EP1009022A1 (en) * 1998-12-09 2000-06-14 STMicroelectronics S.r.l. Manufacturing process of a high integration density power MOS device
US6603173B1 (en) 1991-07-26 2003-08-05 Denso Corporation Vertical type MOSFET

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0576787B2 (en) * 1983-12-10 1993-10-25 Matsushita Electronics Corp
JPS60124970A (en) * 1983-12-10 1985-07-04 Matsushita Electronics Corp Manufacture of fet
US6015737A (en) * 1991-07-26 2000-01-18 Denso Corporation Production method of a vertical type MOSFET
US5460985A (en) * 1991-07-26 1995-10-24 Ipics Corporation Production method of a verticle type MOSFET
WO1993003502A1 (en) * 1991-07-26 1993-02-18 Nippondenso Co., Ltd. Method of producing vertical mosfet
US6603173B1 (en) 1991-07-26 2003-08-05 Denso Corporation Vertical type MOSFET
US5470770A (en) * 1994-03-31 1995-11-28 Nippondenso Co., Ltd. Manufacturing method of semiconductor device
US5920784A (en) * 1994-06-08 1999-07-06 Samsung Electronics Co., Ltd. Method for manufacturing a buried transistor
US5672524A (en) * 1995-08-01 1997-09-30 Advanced Micro Devices, Inc. Three-dimensional complementary field effect transistor process
US5925909A (en) * 1995-08-01 1999-07-20 Advanced Micro Devices, Inc. Three-dimensional complementary field effect transistor process and structures
US5877527A (en) * 1996-04-26 1999-03-02 Denso Corporation Semiconductor device and method of producing the same
US6114207A (en) * 1996-04-26 2000-09-05 Denso Corporation Method of producing a semiconductor device
US6278155B1 (en) 1996-04-26 2001-08-21 Denso Corporation P-channel MOSFET semiconductor device having a low on resistance
EP1009022A1 (en) * 1998-12-09 2000-06-14 STMicroelectronics S.r.l. Manufacturing process of a high integration density power MOS device
US6541318B2 (en) 1998-12-09 2003-04-01 Stmicroelectronics, S.R.L. Manufacturing process of a high integration density power MOS device

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