JPS57202756A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS57202756A
JPS57202756A JP6054682A JP6054682A JPS57202756A JP S57202756 A JPS57202756 A JP S57202756A JP 6054682 A JP6054682 A JP 6054682A JP 6054682 A JP6054682 A JP 6054682A JP S57202756 A JPS57202756 A JP S57202756A
Authority
JP
Japan
Prior art keywords
substrate
films
grooves
layers
isolation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6054682A
Other languages
Japanese (ja)
Inventor
Hiroshi Iwai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP6054682A priority Critical patent/JPS57202756A/en
Publication of JPS57202756A publication Critical patent/JPS57202756A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To flatten completely the element regions and the isolation regions of an LSI by a method wherein films being possible to be oxidized faster than a substrate are made to be survived selectively in grooves provided in the Si substrate, oxidation is performed, and the gap parts in the grooves are eliminated completely with an insulating matter of low melting point. CONSTITUTION:The grooves 13 are formed in the P type Si substrate 11 applying a resist mask 12, and B ions are implanted to form inversion preventive layers 14. The surface is covered with porous Si films 15, the resist mask 12 and polycrystalline Si layers formed thereon are removed, and when thermal oxidation is performed, the films 15 are converted into the SiO2 films 15', and thin SiO2 films 23 are generated on the substrate. Becuase the oxidizing speed of the substrate 11 is slow, enchroaching upon the isolation layer side is not generated. The thin films 23 are etched to expose the substrate making the SiO2 films 15' to be survived only in the grooves 13, and BPSG 16 is accumulated and is molten to be buried up sufficiently in the gaps a. When the surface of the layer 16 is etched to expose the upper face of the substrate 11, the Si substrate 11, the Si substrate having the insulating isolation layers and the element regions being in the same plane therewith and having the flat upper face can be obtained. When the LSI is formed by this constitution, miniaturization of field can be attained, and the isolation layers having the favorable characteristic can be obtained with favorable yield.
JP6054682A 1982-04-12 1982-04-12 Manufacture of semiconductor device Pending JPS57202756A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6054682A JPS57202756A (en) 1982-04-12 1982-04-12 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6054682A JPS57202756A (en) 1982-04-12 1982-04-12 Manufacture of semiconductor device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP16858580A Division JPS5791538A (en) 1980-11-29 1980-11-29 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS57202756A true JPS57202756A (en) 1982-12-11

Family

ID=13145389

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6054682A Pending JPS57202756A (en) 1982-04-12 1982-04-12 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS57202756A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100364125B1 (en) * 1995-12-22 2003-02-05 주식회사 하이닉스반도체 Method for manufacturing isolation layer in semiconductor device
US7067387B2 (en) * 2003-08-28 2006-06-27 Taiwan Semiconductor Manufacturing Company Method of manufacturing dielectric isolated silicon structure

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5363871A (en) * 1976-11-18 1978-06-07 Matsushita Electric Ind Co Ltd Production of semiconductor device
JPS54589A (en) * 1977-06-03 1979-01-05 Hitachi Ltd Burying method of insulator

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5363871A (en) * 1976-11-18 1978-06-07 Matsushita Electric Ind Co Ltd Production of semiconductor device
JPS54589A (en) * 1977-06-03 1979-01-05 Hitachi Ltd Burying method of insulator

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100364125B1 (en) * 1995-12-22 2003-02-05 주식회사 하이닉스반도체 Method for manufacturing isolation layer in semiconductor device
US7067387B2 (en) * 2003-08-28 2006-06-27 Taiwan Semiconductor Manufacturing Company Method of manufacturing dielectric isolated silicon structure

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