JPS57202755A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS57202755A
JPS57202755A JP6054182A JP6054182A JPS57202755A JP S57202755 A JPS57202755 A JP S57202755A JP 6054182 A JP6054182 A JP 6054182A JP 6054182 A JP6054182 A JP 6054182A JP S57202755 A JPS57202755 A JP S57202755A
Authority
JP
Japan
Prior art keywords
substrate
grooves
mask
insulating
bpsg
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6054182A
Other languages
Japanese (ja)
Inventor
Hiroshi Iwai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP6054182A priority Critical patent/JPS57202755A/en
Publication of JPS57202755A publication Critical patent/JPS57202755A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior

Abstract

PURPOSE:To flatten the element regions and the isolation regions of a semiconductor device by a method wherein the first insulating film is made to survive selectively in grooves provided in an Si substrate, and are covered with the second insulating film of low multing point to bury gaps between the grooves and the insulating films completely. CONSTITUTION:The grooves 13 are formed in the P type Si substrate 11 applying a resist mask 12, B ions are implanted to form inversion preventive layers 14, and are covered with thin SiO2 films 15. The SiO2 films 15 on the mask 12 are removed together with the mask, and BPSG 16 of the low melting point is accumulated thereon to be molten and to bury the gaps a completely. When BPSG 16 is etched to expose the upper face of the substrate 11 next, the insulators 15, 16 are buried only in the grooves 13 to obtain the substrate 11 having the insulating isolation regions and the element regions being in the same plane therewith forming the flat upper face. When the LSI is formed after then according to the prescribed method, because miniaturization is enabled and field oxidation is not generated, exuding out of the inversion preventive layers is not generated.
JP6054182A 1982-04-12 1982-04-12 Manufacture of semiconductor device Pending JPS57202755A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6054182A JPS57202755A (en) 1982-04-12 1982-04-12 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6054182A JPS57202755A (en) 1982-04-12 1982-04-12 Manufacture of semiconductor device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP16858480A Division JPS5791537A (en) 1980-11-29 1980-11-29 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS57202755A true JPS57202755A (en) 1982-12-11

Family

ID=13145250

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6054182A Pending JPS57202755A (en) 1982-04-12 1982-04-12 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS57202755A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54591A (en) * 1977-06-03 1979-01-05 Hitachi Ltd Element isolating method
JPS54589A (en) * 1977-06-03 1979-01-05 Hitachi Ltd Burying method of insulator

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54591A (en) * 1977-06-03 1979-01-05 Hitachi Ltd Element isolating method
JPS54589A (en) * 1977-06-03 1979-01-05 Hitachi Ltd Burying method of insulator

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