JPS5745947A - Mos type semiconductor integrated circuit - Google Patents

Mos type semiconductor integrated circuit

Info

Publication number
JPS5745947A
JPS5745947A JP12189480A JP12189480A JPS5745947A JP S5745947 A JPS5745947 A JP S5745947A JP 12189480 A JP12189480 A JP 12189480A JP 12189480 A JP12189480 A JP 12189480A JP S5745947 A JPS5745947 A JP S5745947A
Authority
JP
Japan
Prior art keywords
layer
insulating layer
film
substrate
field
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12189480A
Other languages
Japanese (ja)
Inventor
Shigeru Morita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP12189480A priority Critical patent/JPS5745947A/en
Publication of JPS5745947A publication Critical patent/JPS5745947A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/7627—Vertical isolation by full isolation by porous oxide silicon, i.e. FIPOS techniques

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To obtain an MOS device which has no erroneous operation and the stepwise disconnection of a wire by forming a field insulating layer consecutively integrally with a buried type insulation isolating layer. CONSTITUTION:A resist mask 9 is covered on an SiO2 film 2 on a P type Si substrate 1. When a CF4 plasma is emitted to the film, the film is then etched with NH4F to form a hole 10 having a flaw. The mask 9 is removed, an O2 ion injecting layer 11 is formed, the layer is treated at higher thabn 1,100 deg.C, and a wavy thin insulaing layer 2 made of a field insulating layer 2b consecutive to a buried insulating layer 2a is formed. Thereafter, a memory cell MC, a wiring diffused layer C, and MOS transistor Q are formed on the region surrounded by an insulating layer 1a. Since the minority carrier due to the operation of the Q does not flow to the MC, the erroneous operation can be prevented with no leakage due to the inversion of the field and the layer 2b can be reduced in thickness with this configuration, the surface of the substrate can be smoothened, and no stepwise disconnection of the wire occurs.
JP12189480A 1980-09-03 1980-09-03 Mos type semiconductor integrated circuit Pending JPS5745947A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12189480A JPS5745947A (en) 1980-09-03 1980-09-03 Mos type semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12189480A JPS5745947A (en) 1980-09-03 1980-09-03 Mos type semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS5745947A true JPS5745947A (en) 1982-03-16

Family

ID=14822530

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12189480A Pending JPS5745947A (en) 1980-09-03 1980-09-03 Mos type semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS5745947A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6242556A (en) * 1985-08-20 1987-02-24 Matsushita Electronics Corp Manufacture of semiconductor device
US4713678A (en) * 1984-12-07 1987-12-15 Texas Instruments Incorporated dRAM cell and method
JPH0291973A (en) * 1988-09-29 1990-03-30 Toshiba Corp Manufacture of semiconductor device
US5034335A (en) * 1987-05-26 1991-07-23 U.S. Philips Corp. Method of manufacturing a silicon on insulator (SOI) semiconductor device
JPH07109872B1 (en) * 1987-10-08 1995-11-22 Matsushita Electric Ind Co Ltd
JPH1012850A (en) * 1995-12-30 1998-01-16 Hyundai Electron Ind Co Ltd Soi substrate and its manufacture
US6197656B1 (en) 1998-03-24 2001-03-06 International Business Machines Corporation Method of forming planar isolation and substrate contacts in SIMOX-SOI.

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5116268A (en) * 1974-07-31 1976-02-09 Sumitomo Metal Ind DAISUSHUGOTAIBUNKAIKUMITATESOCHI
JPS5153488A (en) * 1974-11-06 1976-05-11 Hitachi Ltd HANDOTAISHUSEKIKAIROYOKIBANNO SEIHO

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5116268A (en) * 1974-07-31 1976-02-09 Sumitomo Metal Ind DAISUSHUGOTAIBUNKAIKUMITATESOCHI
JPS5153488A (en) * 1974-11-06 1976-05-11 Hitachi Ltd HANDOTAISHUSEKIKAIROYOKIBANNO SEIHO

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4713678A (en) * 1984-12-07 1987-12-15 Texas Instruments Incorporated dRAM cell and method
JPS6242556A (en) * 1985-08-20 1987-02-24 Matsushita Electronics Corp Manufacture of semiconductor device
US5034335A (en) * 1987-05-26 1991-07-23 U.S. Philips Corp. Method of manufacturing a silicon on insulator (SOI) semiconductor device
JPH07109872B1 (en) * 1987-10-08 1995-11-22 Matsushita Electric Ind Co Ltd
JPH0291973A (en) * 1988-09-29 1990-03-30 Toshiba Corp Manufacture of semiconductor device
JPH1012850A (en) * 1995-12-30 1998-01-16 Hyundai Electron Ind Co Ltd Soi substrate and its manufacture
US6197656B1 (en) 1998-03-24 2001-03-06 International Business Machines Corporation Method of forming planar isolation and substrate contacts in SIMOX-SOI.

Similar Documents

Publication Publication Date Title
US4271422A (en) CMOS SOS With narrow ring shaped P silicon gate common to both devices
US3432920A (en) Semiconductor devices and methods of making them
GB1418969A (en) Method of making integrated circuits
US3456168A (en) Structure and method for production of narrow doped region semiconductor devices
JPS5745947A (en) Mos type semiconductor integrated circuit
JPS5736842A (en) Semiconductor integrated circuit device
JPS5643749A (en) Semiconductor device and its manufacture
JPS54161282A (en) Manufacture of mos semiconductor device
JPS56125875A (en) Semiconductor integrated circuit device
JPS5632757A (en) Insulated gate type transistor and integrated circuit
JPS55165681A (en) Preparation of semiconductor device
JPS5585041A (en) Semiconductor device and its preparation
JPS57134956A (en) Manufacture of semiconductor integrated circuit
JPS5773974A (en) Manufacture of most type semiconductor device
JPS54130883A (en) Production of semiconductor device
JP2817226B2 (en) Method for manufacturing semiconductor device
JPS54121683A (en) Semiconductor device and its manufacture
JPS56112742A (en) Manufacture of semiconductor device
JPS5791537A (en) Manufacture of semiconductor device
JPS5593268A (en) Manufacture of semiconductor device
KR100256263B1 (en) Semiconductor element trench type isolation layer manufacturing method
JPS5694759A (en) Wiring forming method
JPS56135970A (en) Semiconductor device
JPS54143076A (en) Semiconductor device and its manufacture
JPS5721865A (en) Manufacture of semiconductor device