JPH0291973A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0291973A JPH0291973A JP24231888A JP24231888A JPH0291973A JP H0291973 A JPH0291973 A JP H0291973A JP 24231888 A JP24231888 A JP 24231888A JP 24231888 A JP24231888 A JP 24231888A JP H0291973 A JPH0291973 A JP H0291973A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- high concentration
- gate electrode
- concentration oxygen
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 19
- 239000004065 semiconductor Substances 0.000 title claims description 8
- 239000001301 oxygen Substances 0.000 claims abstract description 38
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 38
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 23
- -1 oxygen ions Chemical class 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims description 21
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 18
- 229910052710 silicon Inorganic materials 0.000 claims description 18
- 239000010703 silicon Substances 0.000 claims description 18
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 13
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 13
- 238000002955 isolation Methods 0.000 claims description 11
- 238000010438 heat treatment Methods 0.000 claims 1
- 239000010408 film Substances 0.000 abstract description 35
- 238000005468 ion implantation Methods 0.000 abstract description 10
- 239000010409 thin film Substances 0.000 abstract description 10
- 238000005530 etching Methods 0.000 abstract description 5
- 238000000059 patterning Methods 0.000 abstract description 5
- 238000000137 annealing Methods 0.000 abstract description 4
- 150000002500 ions Chemical class 0.000 abstract description 3
- 239000012299 nitrogen atmosphere Substances 0.000 abstract description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 3
- 238000009792 diffusion process Methods 0.000 description 12
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000001133 acceleration Effects 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/78654—Monocrystalline silicon transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の目的〕
（産業上の利用分野）
本発明は、ＭＯａ型トランジスタを製造する技術に係わ
り、特に酸素イオン注入を用いた薄膜８０Ｉ）ランジス
タ半導体装置の製造方法に関する。[Detailed Description of the Invention] [Object of the Invention] (Industrial Field of Application) The present invention relates to a technology for manufacturing MOa transistors, and particularly to a method for manufacturing a thin film transistor semiconductor device using oxygen ion implantation. .
（従来の技術）
絶縁膜上に形成したＳ ＯＩ （Ｓｉｌｉｃｏｎ −０
ｎ−Ｉｎｓｕｌａｔｏｒ）トランジスタは、寄生容量が
小さい、ソフトエラーに強い等の利点があることが知ら
れている。更に、ＳＯＸ層の薄膜化により、移動度の増
加やスイッチング特性の改善が得られることが報告され
ティる（Ｍ、 Ｙｏｉｈｉｍｉ ｅｔ ａｌ、 。(Prior art) SOI (Silicon-0) formed on an insulating film
It is known that n-insulator transistors have advantages such as small parasitic capacitance and resistance to soft errors. Furthermore, it has been reported that increasing the mobility and improving switching characteristics can be achieved by making the SOX layer thinner (M, Yoihimi et al.).
ＩＢＤＭ Ｔｅ ｃ ｈ−Ｄ ｉｇ−＊ ｐｐ−６４０
−６４３ｅ １９８７ ）。IBM Tec h-Dig-* pp-640
-643e 1987).
ＳＯＸ層の製造方法としては、シリコン基板に酸素イオ
ン注入し高濃度酸素層を形成し、これを熱処理すること
により前記高濃度酸素層をシリコン酸化膜化しＳＯＸ層
を形成する方法が知られている。例えば、Ｇ、に、Ｃｅ
１ｌｅｒ、５ｏｌｉｄ ８ｔａｔｅ −Ｔｅａｈ、 、
ｐｐ、 ９３−９８．１９８７に製造方法が開示され
ている。As a method for manufacturing the SOX layer, a method is known in which oxygen ions are implanted into a silicon substrate to form a high concentration oxygen layer, and this is heat treated to turn the high concentration oxygen layer into a silicon oxide film to form an SOX layer. . For example, G, to, Ce
1ler, 5olid 8tate-Teah, ,
A manufacturing method is disclosed in pp. 93-98.1987.
しかしながら、上記製造方法により８０Ｉ層を薄膜化す
るとソース、ドレイン領域のＳＯＸ層も薄膜化するため
ソース、）″レインの拡散層抵抗が増加し、また、コン
タクト、ホールをエツチング技術で開孔する際拡散層も
エツチングされ配線が形成できないという問題があった
。However, when the 80I layer is made thinner by the above manufacturing method, the SOX layer in the source and drain regions is also made thinner, which increases the resistance of the source and drain diffusion layers. There was a problem in that the diffusion layer was also etched and wiring could not be formed.
（発明が解決しようとする課題）
このように、従来のＳＯＸ層の薄膜化ではソース、ドレ
インの拡散層抵抗の増加およびコンタクト、ホール形成
での拡散層のエツチングの問題があった。(Problems to be Solved by the Invention) As described above, the conventional thinning of the SOX layer has the problems of increased resistance of the source and drain diffusion layers and etching of the diffusion layers when forming contacts and holes.
本発明は上記事情を考慮してなされたもので、８０Ｉ層
の薄膜化に伴なう拡散層抵抗の増加およびコンタクト、
ホール形成による拡散層のエツチングの問題のない薄膜
８０Ｉ）ランジスタの製造方法の提供を目的としている
。The present invention has been made in consideration of the above circumstances, and includes an increase in diffusion layer resistance due to thinning of the 80I layer, and contact,
The object of the present invention is to provide a method for manufacturing a thin film transistor (80I) without the problem of etching the diffusion layer due to hole formation.
（課題を解決するための手段）
上記課題を解決するために１本発明は、ＳＯＩ構造を実
現する際ゲート電極を形成した後に酸素イオン注入を行
うことにより、ＳＯＸ層のソース。(Means for Solving the Problems) In order to solve the above problems, one aspect of the present invention is to form the source of the SOX layer by implanting oxygen ions after forming the gate electrode when realizing the SOI structure.
ドレイン膜厚を該ゲート電極下のチャネル領域に比べて
厚く形成して薄膜８０Ｉ）ランジスタを実現するようＫ
したものである。The drain film is formed thicker than the channel region under the gate electrode to realize a thin film transistor.
This is what I did.
（作用）
本発明によれば、ゲート電極を形成した後に酸素イオン
注入を行い、それをアニールすることにより酸素がイオ
ン注入された分布に従って埋め込み酸化膜を形成できる
ので、該ゲート電極下のチャネル領域の８０Ｉ層に比べ
てソース、ドレイン膜厚を厚く形成することが可能とな
る。(Operation) According to the present invention, by performing oxygen ion implantation after forming the gate electrode and annealing it, a buried oxide film can be formed according to the distribution of oxygen ions implanted, so that the channel region under the gate electrode can be formed. It is possible to form the source and drain films thicker than the 80I layer.
（実施例） 以下、本発明の詳細を図示の実施例によって説明する。(Example) Hereinafter, details of the present invention will be explained with reference to illustrated embodiments.
第１図は本発明の第１の実施例に係わる薄膜８０Ｉ ）
ランジスタの製造工程を示す断面図である。まず、第１
図（ａ） Ｋ示すごとくｐ型シリコン基板１１において
、通常の素子分離工程、例えばＬＯＣＯ８法により素子
分離酸化膜１２を形成する。FIG. 1 shows a thin film 80I according to the first embodiment of the present invention.
FIG. 3 is a cross-sectional view showing the manufacturing process of the transistor. First, the first
As shown in Figure (a) K, an element isolation oxide film 12 is formed on a p-type silicon substrate 11 by a normal element isolation process, for example, the LOCO8 method.
その後ゲート酸化膜１３を例えば２Ｑｎｍ形成し、その
上に多結晶シリコン膜を０．３μｍ堆積し周知のパター
ニング技術によりゲート電極１４を形成する。次いで、
第１図Φ）に示すごとく酸素イオンを例えば加速重圧４
００ＫＶで濃度１０１＠０ｒｒａイオン注入し、シリコ
ン基板中に高濃度酸素層１６を形成する。この場合、ゲ
ート電極を通してイオン注入を行っているため、ゲート
電極下のシリコン基板内の高濃度酸素層に比べて、他の
素子領域のシリコン基板内の高濃度酸素層を深く形成で
きる。Thereafter, a gate oxide film 13 is formed to a thickness of, for example, 2Q nm, and a polycrystalline silicon film is deposited thereon to a thickness of 0.3 μm, and a gate electrode 14 is formed by a well-known patterning technique. Then,
As shown in Figure 1 Φ), oxygen ions are accelerated under a heavy pressure of 4
Ions are implanted at a concentration of 101 @ 0 rra at 00 KV to form a high concentration oxygen layer 16 in the silicon substrate. In this case, since ion implantation is performed through the gate electrode, the high concentration oxygen layer in the silicon substrate in other element regions can be formed deeper than the high concentration oxygen layer in the silicon substrate under the gate electrode.
次いで、第１図（Ｃ） Ｋ示すごとく窒素雰囲気中で１
１００°Ｃでアニールし、前記高濃度酸素ｌ１１１１６
をシリコン酸化膜化し、シリコン基板中にシリコン酸化
膜埋め込み領域層１７を・形成する。次いで、第１図（
ｄ） Ｋ示すごとく例えばイオン注入技術によりソース
、ドレイン領域１８を形成する。この後、周知の技術で
配線を形成しトランジスタを作成するＯ
これＫより、ゲート電極下のチャネル領域の８ＩＯ層の
膜厚（シリコン酸化膜埋め込み領域層１７の上部からシ
リコン基板表面までの厚さ）を１０〜５０ｎｍと薄膜と
した場合でもソース、ドレイン膜厚はそれ以上厚く形成
でき、拡散層抵抗の増加およびコンタクト、ホール形成
での拡散層の工、チングの問題のない薄膜ＳＯＩ ）ラ
ンジスタを実現することが可能となる。Then, as shown in Fig. 1(C) K, 1
Annealed at 100°C, the high concentration oxygen l11116
is converted into a silicon oxide film, and a silicon oxide film buried region layer 17 is formed in the silicon substrate. Next, Figure 1 (
d) As shown in K, source and drain regions 18 are formed by, for example, ion implantation technology. After this, wiring is formed using a well-known technique to create a transistor. From this, the thickness of the 8IO layer in the channel region under the gate electrode (thickness from the top of the silicon oxide film buried region layer 17 to the silicon substrate surface) ) is made into a thin film of 10 to 50 nm, the source and drain films can be made thicker than that, and there is no problem of increase in diffusion layer resistance, processing of the diffusion layer during contact or hole formation, or chipping. It becomes possible to realize this.
第２図は本発明の第２の実施例に係わる薄膜８０Ｉ）ラ
ンジスタの製造工程を示す断面図である。まず、第２図
（ａ）に示すごとくｐ型シリコン基板３１において、ゲ
ート酸化膜３２を例えば２０ｎｍ形成し、その上に多結
晶シリコン膜を０．３μｍ堆積し周知のパターニング技
術によりゲート電極３３を形成する。次いで、レジスト
膜２２を０．４μｍ堆積し該レジスト膜の平坦化を行い
、次いで、周知のパターニング技術により素子分離領域
に前記レジスト膜３４を残置する。次いで、第２図Φ）
に示すごとく酸素イオンを例えば加速電圧４００ＫＶで
濃度１０１°Ｃｍ１イオン注入し、シリコン基板中に高
濃度酸素層３６を形成する。次いで、第２図（Ｃ）Ｋ示
すごとく窒素雰囲気中で１１００°Ｃでアニールし、前
記高濃度酸素層３６をシリコン酸化膜化し、シリコン基
板中にシリコン酸化膜埋め込み領域層３７を形成し、次
いで、例えばイオン注入技術によりソース、ドレイン領
域３８を形成する。この後、周知の技術で配線を形成し
トランジスタを作成する。FIG. 2 is a sectional view showing the manufacturing process of a thin film transistor (80I) according to a second embodiment of the present invention. First, as shown in FIG. 2(a), on a p-type silicon substrate 31, a gate oxide film 32 is formed to a thickness of, for example, 20 nm, a polycrystalline silicon film is deposited to a thickness of 0.3 μm thereon, and a gate electrode 33 is formed using a well-known patterning technique. Form. Next, a resist film 22 is deposited to a thickness of 0.4 μm and the resist film is planarized, and then the resist film 34 is left in the element isolation region using a well-known patterning technique. Next, Fig. 2 Φ)
As shown in FIG. 3, oxygen ions are implanted at a concentration of 101°Cm1 at an acceleration voltage of 400 KV, for example, to form a high concentration oxygen layer 36 in the silicon substrate. Next, as shown in FIG. 2(C)K, annealing is performed at 1100° C. in a nitrogen atmosphere to convert the high concentration oxygen layer 36 into a silicon oxide film, forming a silicon oxide film buried region layer 37 in the silicon substrate, and then , the source and drain regions 38 are formed by, for example, ion implantation technology. Thereafter, wiring is formed using a well-known technique to create a transistor.
これにより、ゲート電極下のチャネル領域に比べてソー
ス、ドレイン膜厚を厚く形成でき、拡散抵抗の増加およ
びコンタクト、ホール形成での拡散層のエツチングの問
題のない薄膜５ＯＩ）ランジスタを実現することが可能
となる。また、酸素イオン注入で素子分離と８０Ｉ構造
を同時に形成でき、工程を大幅に簡略化することができ
る。As a result, the source and drain films can be formed thicker than the channel region under the gate electrode, and a thin film 5OI) transistor can be realized without the problem of increased diffusion resistance and etching of the diffusion layer when forming contacts and holes. It becomes possible. Furthermore, element isolation and the 80I structure can be formed at the same time by oxygen ion implantation, and the process can be greatly simplified.
第３図は酸素イオン注入で素子分離と８０Ｉ構造を同時
に形成できる薄膜８０Ｉ）ランジスタの製造工程を示す
断面図である。まず、第３図（ａ）に示すごとくｐ型シ
リコン基板２１において、レジストｌＩ［２２ヲ０．４
μｍ堆積し周知のパターニング技術により素子分離領域
に前記レジスト膜２２を残置する。その後、第３図Φ）
Ｋ示すごとく酸素イオンを例えば加速電圧４００ ＫＶ
で濃度１０１９ ＣｒＴＰイオン注入し、シリコン基板
中に高濃度酸素層２４を形成する。次いで、第３図（Ｃ
）に示すごとく窒素雰囲気中で１１００°Ｃでアニール
し、前記高濃度酸素層２４をシリコン酸化膜化し、シリ
コン基板中にシリコン酸化膜埋め込み領域層２５を形成
する。この後、周知の技術で素子領域２３にゲート、ソ
ース、ドレイン及び配線を形成しトランジスタを作成す
る。FIG. 3 is a sectional view showing the manufacturing process of a thin film 80I) transistor that can simultaneously form element isolation and an 80I structure by oxygen ion implantation. First, as shown in FIG. 3(a), a resist lI [22 0.4
The resist film 22 is deposited to a thickness of .mu.m and left in the element isolation region by a well-known patterning technique. After that, Fig. 3Φ)
As shown in K, oxygen ions are accelerated at an acceleration voltage of 400 KV, for example.
CrTP ions are implanted at a concentration of 1019 to form a high concentration oxygen layer 24 in the silicon substrate. Next, Figure 3 (C
), annealing is performed at 1100° C. in a nitrogen atmosphere to convert the high concentration oxygen layer 24 into a silicon oxide film, thereby forming a silicon oxide film buried region layer 25 in the silicon substrate. Thereafter, a gate, source, drain, and wiring are formed in the element region 23 using a well-known technique to create a transistor.
これにより、酸素イオン注入で素子分離と８０Ｉ構造を
同時に形成でき、工程を大幅に簡略化することができる
。As a result, element isolation and the 80I structure can be formed at the same time by oxygen ion implantation, and the process can be greatly simplified.
以上述べたように本発明によれば、ゲート電極下のチャ
ネル領域に比べてソース、ドレイン膜厚を厚く形成でき
、拡散層抵抗の増加およびフンタクト、ホール形成での
拡散層のエツチングの問題のない薄膜５ＯＩ）ランジス
タを実現することが可能となる。また、酸素イオン注入
で素子分離とＳＯＩ構造を同時に形成でき、工程を大幅
に簡略化することができる。As described above, according to the present invention, the thickness of the source and drain films can be formed thicker than that of the channel region under the gate electrode, and there is no problem of increased resistance of the diffusion layer and etching of the diffusion layer during hole formation. It becomes possible to realize a thin film (5OI) transistor. Furthermore, element isolation and the SOI structure can be formed at the same time by oxygen ion implantation, and the process can be greatly simplified.
第１図は本発明の第１の実施例の製造工程を示す断面図
、第２図は本発明の第２の実施例の製造工程を示す断面
図、第３図は本発明の他の製造工程を示す断面図である
。
１１．２１．３１・・・ｐ型シリコン基板、１２・・・
素子分離酸化膜、
１３．３２・・・ゲート酸化膜、
１４．３３・・・ゲート電極、
１５１２３Ｓ３５・・・ＳＯＩ層、
１６．２４．３６・・・高濃度酸素層、１７．２５．３
７・・・シリコン酸化膜埋め込み領域層、
１８％３８・・・ソース、ドレイン領域、２２．３４・
・・レジスト膜。
代理人 弁理士 則 近 憲 佑
同 松 山 光 之Fig. 1 is a sectional view showing the manufacturing process of the first embodiment of the present invention, Fig. 2 is a sectional view showing the manufacturing process of the second embodiment of the invention, and Fig. 3 is a sectional view showing the manufacturing process of the second embodiment of the invention. It is a sectional view showing a process. 11.21.31...p-type silicon substrate, 12...
Element isolation oxide film, 13.32... Gate oxide film, 14.33... Gate electrode, 15123S35... SOI layer, 16.24.36... High concentration oxygen layer, 17.25.3
7... Silicon oxide film buried region layer, 18%38... Source, drain region, 22.34.
...Resist film. Agent Patent Attorney Noriyuki Chika Yudo Hikaru Matsuyama
Claims (3)
ート電極を形成する工程と、該ゲート電極を通して高濃
度酸素イオン注入を行い前記ゲート電極下のシリコン基
板内他の素子領域のシリコン基板に高濃度酸素層を形成
する工程と、続いてこれを熱処理することにより前記高
濃度酸素層をシリコン酸化膜埋め込み領域層に変える工
程とを含むことを特徴とする半導体装置の製造方法。(1) A step of forming a gate electrode in a method for manufacturing a SOIMOS type semiconductor device, and implanting high concentration oxygen ions through the gate electrode to form a high concentration oxygen layer in the silicon substrate in another element region within the silicon substrate under the gate electrode. 1. A method of manufacturing a semiconductor device, comprising the steps of: forming a silicon oxide layer; and then converting the high concentration oxygen layer into a silicon oxide buried region layer by subjecting the high concentration oxygen layer to a heat treatment.
レジスト膜を素子分離領域に形成するとともに素子領域
にゲート電極を形成する工程と、前記レジスト膜とゲー
ト電極とを通して高濃度酸素イオン注入を行い前記レジ
スト膜直下のシリコン基板内、前記ゲート電極下のシリ
コン基板内および他の素子領域のシリコン基板内高濃度
酸素層を形成する工程と、続いてこれを熱処理すること
により前記高濃度酸素層をシリコン酸化膜埋め込み領域
層に変える工程とを含むことを特徴とする半導体装置の
製造方法。(2) In a method for manufacturing a SOIMOS type semiconductor device,
A step of forming a resist film in the element isolation region and forming a gate electrode in the element region, and implanting high-concentration oxygen ions through the resist film and the gate electrode into the silicon substrate directly under the resist film and under the gate electrode. A step of forming a high concentration oxygen layer in the silicon substrate and in other element regions, and a step of subsequently heat-treating the layer to convert the high concentration oxygen layer into a silicon oxide film buried region layer. A method for manufacturing a featured semiconductor device.
レジスト膜を素子分離領域に形成する工程と、該レジス
ト膜を通して高濃度酸素イオン注入を行い前記レジスト
膜直下にもシリコン基板内に高濃度酸素層を形成する工
程と、これを熱処理することにより前記高濃度酸素層を
シリコン酸化膜埋め込み領域層に変える工程とを含むこ
とを特徴とする半導体装置の製造方法。(3) In a method for manufacturing a SOIMOS type semiconductor device,
a step of forming a resist film in the element isolation region; a step of implanting high concentration oxygen ions through the resist film to form a high concentration oxygen layer in the silicon substrate also directly under the resist film; A method of manufacturing a semiconductor device, comprising the step of converting a high concentration oxygen layer into a silicon oxide buried region layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63242318A JP2755614B2 (en) | 1988-09-29 | 1988-09-29 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63242318A JP2755614B2 (en) | 1988-09-29 | 1988-09-29 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0291973A true JPH0291973A (en) | 1990-03-30 |
| JP2755614B2 JP2755614B2 (en) | 1998-05-20 |
Family
ID=17087426
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63242318A Expired - Fee Related JP2755614B2 (en) | 1988-09-29 | 1988-09-29 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2755614B2 (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH036040A (en) * | 1989-06-01 | 1991-01-11 | Sharp Corp | Semiconductor device |
| EP0461362A2 (en) * | 1990-04-17 | 1991-12-18 | Canon Kabushiki Kaisha | Process for preparing a thin film semiconductor device |
| JPH0436648U (en) * | 1990-07-23 | 1992-03-27 | ||
| EP0460605B1 (en) * | 1990-06-08 | 1997-01-08 | Seiko Epson Corporation | Thin film transistor and method of manufacturing it |
| US6475868B1 (en) * | 1999-08-18 | 2002-11-05 | Advanced Micro Devices, Inc. | Oxygen implantation for reduction of junction capacitance in MOS transistors |
| KR100436291B1 (en) * | 1999-11-09 | 2004-06-16 | 주식회사 하이닉스반도체 | Method of manufacturing a transistor in a semiconductor device |
| JP2006173642A (en) * | 2000-12-05 | 2006-06-29 | Seiko Instruments Inc | Semiconductor device and method of manufacturing the same |
| CN110246896A (en) * | 2018-03-07 | 2019-09-17 | 三星电子株式会社 | Semiconductor device and the method for manufacturing the semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5745947A (en) * | 1980-09-03 | 1982-03-16 | Toshiba Corp | Mos type semiconductor integrated circuit |
| JPS62111445A (en) * | 1985-11-08 | 1987-05-22 | Matsushita Electronics Corp | Manufacture of semiconductor device |
-
1988
- 1988-09-29 JP JP63242318A patent/JP2755614B2/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5745947A (en) * | 1980-09-03 | 1982-03-16 | Toshiba Corp | Mos type semiconductor integrated circuit |
| JPS62111445A (en) * | 1985-11-08 | 1987-05-22 | Matsushita Electronics Corp | Manufacture of semiconductor device |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH036040A (en) * | 1989-06-01 | 1991-01-11 | Sharp Corp | Semiconductor device |
| EP0461362A2 (en) * | 1990-04-17 | 1991-12-18 | Canon Kabushiki Kaisha | Process for preparing a thin film semiconductor device |
| US5510640A (en) * | 1990-04-17 | 1996-04-23 | Cannon Kabushiki Kaisha | Semiconductor device and process for preparing the same |
| EP0460605B1 (en) * | 1990-06-08 | 1997-01-08 | Seiko Epson Corporation | Thin film transistor and method of manufacturing it |
| JPH0436648U (en) * | 1990-07-23 | 1992-03-27 | ||
| US6475868B1 (en) * | 1999-08-18 | 2002-11-05 | Advanced Micro Devices, Inc. | Oxygen implantation for reduction of junction capacitance in MOS transistors |
| KR100436291B1 (en) * | 1999-11-09 | 2004-06-16 | 주식회사 하이닉스반도체 | Method of manufacturing a transistor in a semiconductor device |
| JP2006173642A (en) * | 2000-12-05 | 2006-06-29 | Seiko Instruments Inc | Semiconductor device and method of manufacturing the same |
| CN110246896A (en) * | 2018-03-07 | 2019-09-17 | 三星电子株式会社 | Semiconductor device and the method for manufacturing the semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2755614B2 (en) | 1998-05-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR930010121B1 (en) | Process for forming high and low voltage cmos transistors on a single integrated circuit chip | |
| US4422885A (en) | Polysilicon-doped-first CMOS process | |
| JPS63244776A (en) | Manufacture of insulated-gate field-effect transistor | |
| JPH0291973A (en) | Manufacture of semiconductor device | |
| JPH0799259A (en) | Bi-cmos soi structure containing longitudinal bipolar transistor and preparation thereof | |
| JP2730535B2 (en) | Method for manufacturing semiconductor device | |
| JP2596117B2 (en) | Method for manufacturing semiconductor integrated circuit | |
| KR100244402B1 (en) | Method of forming a trench isolation in a semiconductor device | |
| JP2002299590A (en) | Method of manufacturing semiconductor substrate and semiconductor device | |
| JPS62285468A (en) | Manufacture of ldd field-effect transistor | |
| JPH04343437A (en) | Manufacture of semiconductor device | |
| JPH0472770A (en) | Manufacture of semiconductor device | |
| KR0167664B1 (en) | Method of fabricating semiconductor device | |
| JP3344162B2 (en) | Method for manufacturing field effect semiconductor device | |
| US20030178679A1 (en) | Semiconductor device and method of manufacturing the same | |
| KR100303356B1 (en) | SOI device having double gate structure and method of manufacturing the same | |
| JPS60134469A (en) | Manufacture of semiconductor device | |
| JPH05275529A (en) | Method of manufacturing semiconductor integrated circuit | |
| JPH05160404A (en) | Manufacture of semiconductor device | |
| KR0147255B1 (en) | Method for manufacturing mosfet | |
| KR100357173B1 (en) | Method for manufacturing thin film transistor | |
| JP2926817B2 (en) | Method for manufacturing semiconductor device | |
| JPH04260331A (en) | Manufacture of semiconductor device | |
| JPH0964361A (en) | Manufacture of semiconductor device | |
| JPS61252656A (en) | Manufacture of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |