JPS61252656A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain an SOI structure, which has excellent characteristics of an interface between an insulating film and a semiconductor layer to such a degree that a basis insulating film can be utilized as a gate insulating film, by forming the insulating film at a part of at least the upper layer or the lower layer of a microbridge, and forming a laminated structure of a semiconductor and the insulator. CONSTITUTION:An SiO2 film 8 is formed on a single crystal Si substrate 7. The film is isolated into rectangular islands by using a photolithography technology. A polycrystalline Si film is deposited on the film. Thereafter, the film is transformed into a single crystal Si film 9 by scanning a laser beam. A mask is applied on the film and etching is performed. Thus the SOI region is isolated into several islands. Then the SiO2 film is selectively etched, and an Si microbridge 30 is formed. The bridge undergoes thermal oxidation, and the surface is coated with the SiO2 film 8 having excellent quality. Thereafter, an MOSFET, which uses the SiO2 8 as a gate oxide film 4, is formed on the microbridge 30 by using normal processes.

Description

[Detailed Description of the Invention] (Field of Application of the Invention) The present invention relates to a method of manufacturing a semiconductor device, and in particular, the present invention relates to a method for manufacturing a semiconductor device, and in particular, the interface between the layered structure of a semiconductor and an insulator is improved to the extent that it can be used as a channel region and a gate insulating film of MO5FET for LSI. The present invention relates to a method for manufacturing a semiconductor device that can form an SOI structure with good characteristics.

[Background of the invention]

The development of electronic computers and communication equipment has been remarkable, and in particular recently, attempts have been made to realize more advanced functions by assembling multiple electronic computers into a network using communication lines. It really feels like the dawn of the information age. Therefore, the development of these devices is now a requirement of the times.
There is an extremely high demand for ultra-high speed and ultra-high integration of large-scale integrated circuits (LSI), which are the basic components. Until now, the main method to meet this demand has been miniaturization of elements. However, from now on, S OI (Sili'con
0nInsulator: Stacked integrated circuits and new structure transistors using the structure (single crystal Si on an insulator) are thought to be the key players. Examples of such devices are shown in FIGS. 8(A) and 8(B).

FIG. 8(A) is a cross-sectional view of a laminated integrated circuit, and FIG.
B) is JF Gibbons (J, F.

Gibbons) and K.F.
IEEE Electron Devices Letters (IEEE Electr) by
on DavisesLatters), Vol.
117 of EDL-1, No. 6 (June 1980)
The paper “One Gate Wide C” written on page 118
MOS inverter-on-laser recrystallized polysilicon J (One-Gate-Wide CMO
3Inverter on La5ar-Recrys
tallized polysilicon: single gate CMOS formed on laser recrystallized polysilicon
This is a joint gate CMO8, which is one of the new structure transistors shown by (Inverter). In each case, a MOS field effect transistor (MOSFET) formed in a Si layer 6 on an insulating film 5 is used as a basic element. In Figure 8 (A), the part surrounded by the dashed line is the MOSFE.
It is T. Note that the joint gate CMO3 is the ninth gate CMO3.
As shown in the conceptual diagrams in Figures (A) to (C), there are two MO
Complementary type M in which SFETs share one gate electrode 1
It is O8FET (0MO5).

Conventional S○ tank structure formation technology can be roughly divided into two methods: a method of forming single crystal Si on an insulating film or an insulating substrate, and a method of forming single crystal Si on an insulating film or substrate;
There is a method of forming an insulating layer in the i-substrate. As an example of the former, polycrystalline S deposited on an insulating film such as S io2
i is laser annealing or electron beam annealing,
There are techniques for crystallization using strip heaters, annealing, etc. An example of the latter is a technique in which a damaged layer is formed in a substrate by proton implantation and selectively oxidizes the damaged layer, which is easily oxidized, or a technique in which an Si layer is formed in a Si substrate by oxygen ion implantation. etc. At present, these techniques have made it possible to form SOI with good crystallinity that can be used to form MOSFETs. However, the SOI formed by either method also has a Si layer 6
The electrical characteristics of the interface between the MOSFET and the insulating film 5 are not good. Therefore, when a MOSFET is formed as shown in FIG. 8(A),
The interface 32 between the insulating film 5 and the Si layer 6 formed thereon becomes a path for leakage current between the source 2 and drain 3, resulting in extremely unsatisfactory device performance.

Therefore, in order to avoid this problem, a method has been devised in which impurities are introduced into this interface 32 by ion implantation to form a channel stopper, and quite good results have been obtained.

However, the joint gate CMO shown in FIG. 8(B)
As in the upper layer MOSFET 8, the base insulating film 5 is
When used as a thin gate insulating film 4 with a thickness of 100 nm, the interface 33 between the base insulating film 5 and the Si layer 6 formed thereon is
The above problem becomes even more serious because a channel is formed in the channel, and the above method also fails and the problem remains unsolved.゛ [Object of the Invention] An object of the present invention is to provide an S layer with good interface characteristics between the insulating film and the semiconductor layer so that the underlying insulating film can be used as a gate insulating film.
The purpose is to provide an O-groove structure.

[Summary of the invention]

For example, silicon (Si) and oxygen (0) are chemically compatible, and the chemical reaction between the two, i.e., the oxidation of the Si substrate, in particular, causes ○ to diffuse into the substrate and form a 5i-0 bond where it meets Si. By oxidizing the structure of forming a SiO□ layer/Si layer structure with extremely good interfacial properties. In other words, (1) there is solid Si at the beginning, and by oxidizing it, a SiO film is formed; ■ At that time, 0 is supplied by diffusion, and the two points are S with good interface characteristics.
i/Sin is the condition for creating the system. Looking at the conventional SOIO technology from this perspective, the method of forming a Si layer on an insulating film does not satisfy (■) in the first place, and
In the method of forming the Sio layer in the i-substrate, 0 is introduced by ion implantation, so the condition (2) is not satisfied. Therefore, it is difficult to form a good interface.

The present invention is based on the above considerations using silicon as an example.

This method was devised as a method that satisfies the conditions (1) and (2) above.

That is, by first forming a double-sided beam or cantilever beam (micro bridge: hereinafter referred to as a micro bridge) made of semiconductor material, and then oxidizing or nitriding, or depositing an insulator, The present invention is characterized in that an insulating film is formed on at least part of the upper layer or the lower layer of the microbridge to form a laminated structure of a semiconductor and an insulator.

[Embodiments of the invention]

The present invention will be explained in detail below.

Example 1 This example is an example in which a MO8FET was fabricated on a Si layer on an insulator.

As shown in FIG. 1(A), on a single crystal Si substrate 7,
A SiO2 film 8 with a thickness of 7000 nm was formed and separated into rectangular islands using conventional photolithography techniques.

At this time, other insulating films such as Si and N4 may be used instead of the Sin film. In addition, the shape of the island is circular, square,
A polycrystalline Si film 9 of 3500 mm thick is deposited on this, which may have a rectangular or other suitable shape, and then laser
This was made into a single crystal by scanning the beam. That is, the SOI structure was formed by a conventional SOI formation technique using laser annealing. In this case, any other conventional SOI technology, such as SOI technology using strip heater annealing or SOI technology using planar phase growth of Si, may be used.
Next, by applying a mask to this and etching it, the SOI region was separated into several islands as shown in FIG. 1(B) (two islands are shown in the figure). ), and then selectively etching the 5in2 film 8 to form a Si microbridge 30 as shown in FIG. 1(C). This is subjected to thermal oxidation and its surface is covered with a high-quality Sio film 8 with a thickness of 450 people, and then
- A MOSFET using this Sio film 8 as the gate oxide film 4 was fabricated on the microbridge 30 using a conventional process. FIG. 1(D) shows a cross-sectional view of the result.

Note that plasma oxidation or the like may be used instead of thermal oxidation, and other insulating films such as Si, N4, etc. may be used instead of 5in2. Furthermore, if the polycrystalline SL is buried in the void 31 under the microbridge 30 after this, as shown in FIG. 1(E).
As shown in the figure, the gate 1 can also be formed in the lower layer.

Example 2 In this example, a MOSFET was fabricated on a Si substrate, and a microbridge 81 was formed thereon.

A MOSFET was fabricated on this bridge to fabricate a laminated integrated circuit.

First, as shown in FIG. 2(A), a gate electrode 1. is formed on a Si substrate 7 using a normal process. A MOSFET consisting of a source region 2, a gate region 3, and a gate insulating film 4 was manufactured. On top of that, CVD method (Che+5ical Va.
per 'Deposition) by Sin, membrane 8
This was deposited to a thickness of approximately 1.3 mm, patterned into a rectangular shape in the same manner as in Example 1 using a known photolithography technique, and a polycrystalline Si film 9 of 3,500 mm thick was deposited on it. The deposited Si was made into a single crystal by scanning with a laser beam. At this time, the SOI that illuminates the laser beam
It goes without saying that the technology is not limited to this, but may also be the 100I technology that uses an electron beam, the SOI technology that uses solid phase growth, and others.

Now, some parts of this rectangular S○ area were etched away by etching using a mask to form the shape shown in FIG. 2(B). However, at this time, d>W/2 (see Figure 2 (B)).

Care was taken to satisfy the following conditions: W is Sin remaining in the shaved region, thickness of the film 8, and W is the width of the SOI region that was not scraped. Specifically, w=0.84, d='0.8
It was set to 11m. Next, by isotropic selective etching, S
in, SOI by etching the film 8 by 0.5p.
Remove SLo, 8 directly under Siio in the structure, and add the second
As shown in the figure (C>), an SL microbridge 30 was formed. At this time, the etching depth of the film 8 was set to S
Since it does not reach the gate oxide film of the MOSFET on the i-substrate 7, there is no fear that this FET will be damaged.

Since d>W/2, such etching was possible. Next, as shown in Figure 2 (D), a thin Sin film 8 with a thickness of 450 mm was formed by thermal oxidation. Then, using this 5un2 film 8 as the gate oxide film 4, a MOSFET was fabricated on the microbridge using a normal process. The point that plasma oxidation or other methods may be used for oxidation is as follows.
This is the same as in Example 1.

Thereafter, by low-pressure CVD, the void under the microbridge was filled with Sio, and the entire surface of the substrate was covered with -8io, film 8. Thereafter, although not shown, a multilayer integrated circuit is completed by forming through holes and wiring using M. In this example, semiconductor layers with different conductivity types are formed in the upper and lower layers. Then, a CMOS inverter was formed by electrically connecting both gates, and one side of the high concentration impurity layer of the upper MOSFET and one side of the high concentration impurity layer of the lower MOSFET. It goes without saying that the connection between the high-concentration impurity regions in the upper and lower layers may be made by forming both impurity layers directly, as shown in FIG. 2(E), without using wiring. do not have.

Example 3 The structure shown in FIG. 2(E) was formed by the process shown in Example 2. Thereafter, the Sio and film 8 were etched using a mask, leaving only the Sio and the film 8 on the microbridge (FIG. 3(A)).

Next, as shown in FIG. 3(B), by using selective epitaxial growth, a single crystal Si film 25 was deposited and planarized only on the exposed Si region up to the height of the microbridge. Note that this single crystal S up to the height of the SiO□ film 8
By depositing i, a flatter structure can be obtained.

After this, using the process shown in Example 2, a microbridge was formed again, a MOSFET was formed in the layer, and the SIO and film provided on the surface of the structure shown in FIG. 3(B) were formed. Although not shown in Figure 8, through holes were formed and wiring was performed to complete a three-layer integrated circuit. however,
In this example, instead of M wiring, polycrystalline S with high impurity concentration is used.
i was used.

Example 4 This example uses the present invention to construct a joint gate CMO8.
This is an example of creating a . At this time, the source and drain regions were formed on the gate electrode in both the upper and lower layers by self-alignment.

As shown in FIG. 4(A), single crystal Si of n-type conductivity
A substrate 7 was prepared, and boron ion implantation 11 was performed thereon using a mask 10 made of resist to form a P+ type region 2. This area will eventually become the underlying MOS
This becomes the source region of the FET.

Next, as shown in FIG. 4(B), a conventional SOIO technique using laser annealing similar to that in Example 1 was used to form an SOIO structure so as to partially overlap the above P+ type region. . At this time, as in the first embodiment, other SOIO techniques may be used. Furthermore, boron ions were implanted into the deposited single crystal Si film 9 to make it p-type conductivity. Next, by applying a mask to this and etching it, the SOIO region was separated into several islands as shown in FIG. 1(B) of the first embodiment. Next, a 513N4 film was deposited on the surface of the substrate by the CVD method, and this was etched using a mask to form the shape shown in Figure 4(C) (only one island region is shown in the figure). This Si3N4 film 14 is used as a mask for ion implantation to form the source and drain, and for positioning for forming the gate electrode. That is, first, boron was implanted here at acceleration energies of 500 keV and 200 keV to form a P+ type region 2.3 as shown in FIG. 4(D). The P+ type region 2, which overlaps with the P+ type region previously formed on the substrate before forming the SO tank structure, is the lower layer MO of the joint gate CMO8.
As the source region 2 of 8FET, also the other P+
The type region will be used as the drain region 3 of the lower layer MO8FET, and an acceleration energy of 200 kaV is applied here.
Phosphorus ions were implanted into the deposited Si film (Fig.
As shown in E), regions 12 and 13 of 04'' conductivity type were formed.As the source region 12 of the MOSFET formed in the upper layer of the n+ type region 12 in contact with the source region 2 in the lower layer, the drain region 3 in the lower layer and the drain region 3 in the lower layer were formed. Contacting n+ type region 13
Next, as shown in FIG.
A mask IO was formed as shown in the figure by applying 0 and cutting a pattern using photolithography.

This is then subjected to selective etching of the Si3N film and SOI
The 13N4 film around the four peripheries of the island was removed, and then the resist 10
was removed to form the shape shown in FIG. 4(G).

By the way, when a sample is exposed to plasma, the sample surface is covered with an electric field region called a sheath. Inside the sheath, positive ions are accelerated toward the sample, so if plasma etching is performed in a region with sufficiently low gas pressure that the mean free path of the ions is greater than the thickness of the sheath, the positive ions will be accelerated toward the sample. Etching progresses only in this direction. By utilizing this property and selectively etching the Sin film 8 of the sample, the fourth
As shown in Figure (H), the Si, N, and film 8 are scraped away leaving behind the shadowed portions of the Si, N, and film 14, and a Si microbridge is formed. The remaining SiO□ film 8 is a dummy gate. Subsequently, Si,
N, the film 14 is removed, and then, as shown in FIG. 4(I), the sample surface is heated to a thickness of 5 in
As shown in FIG. 4(J), the CV
Deposit Si, N, films 14 and 16 by method D, and then
When anisotropic etching 15 is performed, 5isN4 is removed by removing the Si and N4 film 16 filled under the microbridge.
Membrane 14 is removed.

Then, when selective etching of the Sio film was performed, S10. which was under the microbridge. After the film 17 was removed, thermal oxidation was performed to form a SiO□ film with a thickness of 250 mm on the lower surface of the microbridge and the surface of the substrate immediately below it, as shown in FIG. 4(K). This is the gate oxide film 4 of this joint gate CMO8. After this, in the previous step shown in FIG. 4(J), SL,
In the same way as the N film 16 was filled under the microbridge and anisotropically etched, a high impurity concentration was deposited by CVD followed by anisotropic etching, as shown in FIG. 4(K). A polycrystalline Si film 1 was filled under the microbridge. This is joint gate CMO8
This is the gate electrode 1. Due to the above.

The main parts of the device are complete.

Next, processing is performed to enable electrical connection to the gate 1 and the sources 12 and 2 of the upper and lower layers, respectively.First, as shown in FIG. 4(L), the surface of the sample is A resist 18 is applied. Using photolithography technology, the resist in the area surrounded by the dashed line in FIG. 4(L) is removed, and the sample surface is etched until the gate electrode 1 buried under the microbridge is exposed. Thereafter, by removing the resist 18, the sample has the shape shown in FIGS. 4(M) and 4(N). Figure 4 (N)
As can be seen from the top view, the gate electrode 1 is exposed in a trapezoidal shape. This is because the mask 14 had such a shape when forming the dummy gate, as shown in FIG. 4(H).

Since wiring is performed in this trapezoidal region, contact resistance can be reduced. However, in applications where there is no problem even if the contact resistance of the gate is somewhat high, it goes without saying that the shape of the gate electrode 1 does not need to be shaped like a trapezoid that widens toward the end. Note that since the dummy gate mask is also a mask for ion implantation for forming the source and drain, the shapes of the end portions of the source and drain are naturally the same. In this process, the gate electrode 1
and the source 12 of the upper layer MOSFET.
The separation from source 2 of the lower layer MOSFET has been completed.

Finally, as shown in FIG. 4(0), a Sio film 8 is deposited by bias sputtering, a contact hole is opened by etching using a mask, and a joint gate is formed by wiring using a ferrule. CMO8 has been completed. In addition.

It goes without saying that the joint gate CMO5 in which the conductivity type is replaced with nvp as shown in this embodiment can be manufactured by a similar process.

Example 4 (2) This example is a simplified version of Example 4. In other words, if it is necessary to keep the parasitic capacitance between the source, drain, and gate extremely small, the device of Example 4 is necessary, whereas if this is not a problem, the device of this example is effective. becomes.

The structure shown in FIG. 4(E) was formed using the same process as described in Example 4. The Si and N4 films 14 were then removed by selective etching, and then another selective etching method was used. The SiO□ film 8 was removed. By thermally oxidizing this, a layer of Si with a thickness of 250 nm was deposited on the surface of the sample.
o. Film 8 was formed. next.

By low pressure CVD method, on the substrate surface, micro bridge,
and polycrystalline S with high impurity concentration under the microbridge.
An i-film 22 was formed and the structure shown in FIG. 4(P) (cross-sectional view) was formed using anisotropic etching to remove the area other than the area on the microbridge and the area to be used later as an extraction electrode of the gate electrode. The polycrystalline Si film 22 on the substrate was removed. In addition, in Example 4, FIG. 4(L), (
In the same way as shown in step M), apply a resist, partially remove it, and perform etching using the resist as a mask to separate the source 12 of the upper layer MOSFET and the lower layer MOS.
The FET was separated from the source 2 (FIG. 4 (Q)).

After that, in the same way as in Example 4, the sample is covered with a passivation film (Sing film 8), a contact hole is opened in this, and primary wiring is performed to form a joint gate CM.
In this example, where O3 is completed, the conductivity type is set to nyP.
It goes without saying that the replaced joint gate CMO8 can be manufactured using a similar process.

Example 5 In the process shown in Example 4, the ion implantation 11 shown in FIG. For ion implantation, ions forming the same conductivity type are selected, and the upper and lower source regions 12 and 2 are implanted.
By omitting the process of separating the channels, a single gate 1 can simultaneously drive the upper and lower channels.
SFET was fabricated. This corresponds to doubling the channel width without increasing the parasitic capacitance of the source and drain compared to the conventional MOSFET, and therefore, twice the value of the transconductance g, l+ was obtained.

Example 6 In this example, one of the MOSFETs with the new structure described above was manufactured using the present invention.

The structure shown in FIG. 1(C) was formed by the same process as described in Example 1, and the conductivity type of the deposited Si film 9 was made the same as that of the substrate 7 by ion implantation, and then by thermal oxidation. It was covered with an oxide film 8 having a thickness of 250 mm. next,
A polycrystalline Si film 22 with a high impurity concentration was deposited by the CVD method, and a mask 10 was formed thereon as shown in FIG. 5(A). By performing anisotropic etching on this,
After the 0th order, leaving the polycrystalline Si film 22 only under the mask 10 and under the microbridge, the fifth As shown in FIG. (B), the polycrystalline Si film 22 is
was removed. Then, the mask 10 is removed and the mask 10 shown in FIG.
), (D), thermal oxidation results in 5 on the surface of Si.
A source 2 and a drain 3 were formed in the microbridge by forming an oxide film 8 of 0.00% and implanting ions using the polycrystalline Si film 22 as a mask. Note that in applications where the parasitic capacitance between the source 2, drain 3, and gate electrode 1 does not pose much of a problem, ordinary anisotropic etching may be used instead of etching using a sheath electric field. In that case, the polycrystalline S under the microbridge
All the i-films 22 are arranged in a row, and the finished device has the form shown in FIGS. 5(E) and 5(F). Further, although thermal oxidation is used in this embodiment, plasma oxidation, magnetic field microwave plasma CVD, etc. may be used instead.

Example 7 In the process of Example 6, before the ion implantation for forming the source 2 and drain 3 in the microbridge, ions having the same conductivity type as the source 2 and drain 3 of the microbridge were implanted into the substrate. A MOSFET having the structure shown in FIG. 6 was formed by inserting a step of implanting with high acceleration energy reaching 7. With this configuration, in this embodiment, the transfer conductance gm can be reduced to 3
I was able to more than double it. .

Example 8 In the process of Example 6, deposited S by ion implantation
Instead of the process of making the conductivity type of the i-film 9 the same as that of the substrate 7, a process of selecting and implanting ions that make the conductivity type of the deposited Si film 9 opposite to that of the substrate 7 is performed, and Before ion implantation to form the source 12 and drain 13 in the microbridge source 1.
2. A process was inserted in which ions of a conductivity type opposite to that of the drain 13 were selected and implanted with high acceleration energy to reach the substrate 7, and the sources 2 and 12 and the drains 3 and 13 were further formed. Thereafter, a step of removing part of the source region 12 of the deposited Si 9 by etching using a mask to separate it from the source 2 formed on the substrate 1 was inserted, thereby producing a MOSFET of the form shown in FIG. This is because the upper layer MO8FET is M
This is a joint gate CMO8 which is an OSFET.

Several examples have been described above, and among them, Example 1
(Fig. 1 (D)), Example 2 (Fig. 2 (D)), Example 6 (Fig. 5 (D)), Example 7 (Fig. 6), Example 8
(Figure 7) shows the upper layer MOSFET and the lower layer MOSFET.
An air layer is used for interlayer insulation with the ET or the substrate 7, and a 5in2. It goes without saying that other insulators such as Si and N4 may be filled. However, the lower the dielectric constant of the glabellar insulating film, the better. Therefore, vacuum, which has the lowest dielectric constant, is preferred, followed by nitrogen or air, which is similar to vacuum. In addition, in the above example, when mounting the fabricated device, a method of sealing with dry nitrogen was used.Also, in the above example, a device with a two-layer or three-layer structure of a deposited Si layer and a Si substrate was fabricated. It goes without saying that a device with four or more layers can be manufactured by stacking several stages of microbridges on top of this and using the method described in the above embodiment.

Furthermore, in Example 2 and its multi-stage structure device,
It goes without saying that elements other than MO8FET, such as capacitors, can be fabricated in the microbridge or on the substrate.

In the above example, the interface state density between the Si film formed on the insulator and the insulator was able to be extremely small, about 2×10-1 layer cm-". As a result, the channel stopper was placed here. M formed on the Si film even if it is not formed
The leakage current between the source and drain of the OSFET was able to be reduced to the same level or smaller than that of a MOSFET fabricated on an SL substrate.

〔Effect of the invention〕

As explained above, according to the present invention, the base insulating film and
The interface characteristics with the semiconductor layer formed on the insulating film can be significantly improved. Due to this.

MOSFET without forming a channel stopper at the interface
It was possible to prevent leakage current between the source and drain of the ET, and to establish a basic process for a MOSFET in which the underlying insulating film is the gate insulating film.

[Brief explanation of drawings]

FIGS. 1(A) to (E) are views showing a first embodiment of the present invention, FIGS. 2(A) to (E) are views showing a second embodiment of the present invention, and FIG. A) and (B) are diagrams showing the third embodiment of the present invention, FIGS. 4(A) to (Q) are diagrams showing the fourth embodiment of the present invention, and FIGS. 5(A) to ( F) is a diagram showing the sixth embodiment of the present invention, FIG. 6 is a diagram showing the seventh embodiment of the present invention,
FIG. 7 is a diagram showing the eighth embodiment of the present invention, FIG. 8(A)
8(B) is a cross-sectional view showing the basic structure of future stacked integrated circuits, FIG. 8(B) is a cross-sectional view showing the future new structured transistor,
Figures (A) to (C) are diagrams showing the concept of the configuration of the joint gate CMO8. 1... Gate electrode 2... Source region 3...
- Drain region 4... Gate insulating film 5... Base insulating film 6... Si film 7 in SOI structure... Si substrate 8... SiO2 film 9
... Single crystallized deposited Si film 1G... Mask 11... Ion implantation 12... Source region 13 of upper layer MO8FET...
Drain region 14 of upper layer MO8FET...Si, N4
Film 15...Anisotropic etching 16...813N4 film filled under the microbridge 17...
SiO□ film 18 filled under the microbridge...
Resist 19...Gate electrode terminal 20...
・Source electrode terminal 21 of upper layer MO5FET...lower layer M
O8FET source electrode terminal 22...high impurity concentration polycrystalline Si film 23...source electrode terminal 24...
Drain electrode terminal 30...micro bridge

Claims (1)

[Claims] By forming a double-sided beam or cantilever made of semiconductor material, and then oxidizing or nitriding, or depositing an insulator, at least the upper or lower layer of the double-sided beam or cantilever is 1. A method of manufacturing a semiconductor device, comprising the step of forming an insulating film on a portion or the entire surface to form a laminated structure of a semiconductor and an insulator.