JPH079993B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a MIS (metal-insulating film-semiconductor) type field effect transistor (FET) and a method for manufacturing the same, and particularly to a semiconductor and an insulator. The laminated structure with
TECHNICAL FIELD The present invention relates to a semiconductor device capable of forming an SOI structure having good interface characteristics that can be used as a channel region and a gate insulating film of a MISFET for use in a semiconductor device, and a manufacturing method thereof.

BACKGROUND OF THE INVENTION The development of electronic computers and communication devices has been remarkable, and in particular, recently, attempts have been made to realize more advanced functions by connecting a plurality of electronic computers to a network using communication lines. There is a strong sense of the dawn of the information age. Therefore, the development of these devices is now a demand of the times,
The demand for ultra-high speed and ultra-high integration of the large-scale integrated circuit (LSI) that is the basic component is extremely large. Until now, the main method to meet this demand has been the miniaturization of elements. However, in the future, it is considered that stacked integrated circuits and new-structure transistors using SOI (Silicon On Insulator: single crystal Si on insulator) will play a key role. Examples of these devices are shown in FIGS. 8 (A) and 8 (B).

FIG. 8A is a cross-sectional view of a laminated integrated circuit in which LSIs formed on a normal plane are laminated with an insulating film interposed therebetween, and the degree of integration increases by the number of layers. Figure 8 (B) is the IEEE Electron Device by the JF Gibbons and KFLee.
s Letters), Vol.EDL-1, No.6 (June 1980) 117-118
Paper "One-Gate-Wide CMOS Inverter on Laser-Recry"
stallized Polysilicon: Joint gate CM which is one of the new structure transistors shown by single gate CMOS inverter formed on laser recrystallized polycrystalline silicon.
OS. In both cases, MI formed on the Si layer 6 on the insulating film 5
SFET (In this case, the insulating film is an oxide film ( O xide), so MO
Called SFET) is the basic element. In FIG. 8A, the portion surrounded by the alternate long and short dash line is the MOSFET. In addition,
The joint gate CMOS is a complementary MOSFET (CMOS) in which two upper and lower MOSFETs share one gate electrode 1 as shown in the conceptual diagrams of FIGS. 9 (A) to 9 (C). MOSFET
Since the interlayer connection of the gate electrodes is not required, the integration degree is further improved as compared with the case of simply stacking.

When the MOSFET is formed on the SOI layer, if the lower surface of the source / drain region is designed to be in contact with the I layer (insulator) having a low dielectric constant, the MOSFET of the conventional structure in which the lower part of the source / drain region is composed of a semiconductor Compared with, the parasitic capacitance of the source and drain regions can be reduced. Therefore, the operation speed of the device can be increased.

The conventional SOI structure forming technology is roughly classified into a method of forming single crystal Si on an insulating film or an insulating substrate and a method of forming an insulator layer in the single crystal Si substrate. As an example of the former, the polycrystalline Si deposited on the insulating film such as SiO ₂
There is a technique of crystallizing by annealing, electron beam annealing, strip heater annealing, or the like. Examples of the latter include a technique of forming a damaged layer in the substrate by proton implantation and selectively oxidizing the easily damaged oxidized layer, or a technique of implanting oxygen ions into the Si substrate to form a Si layer.
There is a technique for forming an O ₂ layer. Nowadays, these technologies have enabled the formation of SOI with good crystallinity for MOSFET formation. However, the SOI formed by either method has poor electrical characteristics at the interface between the Si layer 6 and the insulating film 5. Therefore, when a MOSFET is formed as shown in FIG. 8A, the interface 32 between the insulating film 5 and the Si layer 6 formed thereon forms a current path between the source 2 and the drain 3, and this This increases the leakage current between the source and drain regions and increases the power consumption when the device is off. In LSI, signals flow to required elements when needed, so
When viewed as a whole, a large number of elements are in the off state, and the power consumption when the off state determines the power consumption of the entire LSI chip. L
In order to suppress the heat generation of SI and operate it without malfunction, the leakage current must be suppressed to 10 ^-10 A / μm or less, and the increase of the leakage current due to the poor interface is a problem. The leakage current has the property of increasing as the temperature rises. SOI
-In the case of MOSFET, since the heat conductivity of the insulating film is low, heat tends to accumulate, so in order to keep the leakage current during steady operation within the above value, the leakage current value at the beginning of current application should be as low as possible. Is desirable.

Therefore, in order to avoid this problem, a method has been devised in which impurities are introduced into the interface 32 by ion implantation to form a channel stopper, and quite good results have been obtained. However, in this method, some of the introduced impurities reach the facing gate insulating film interface due to the depthwise expansion of the impurity concentration due to ion implantation and the heat treatment during device manufacturing, and the threshold voltage of the MOSFET is increased. Make it difficult to control. In particular, it is difficult to apply to future SOI-MOSFETs where the junction between the source and drain regions becomes shallow and the Si layer becomes thin accordingly. Further, in particular, when the base insulating film 5 is used as the thin gate insulating film 4 having a thickness of 5 to 100 nm like the MOSFET in the upper layer of the joint gate CMOS shown in FIG. 8B,
Since the channel is formed at the interface 33 between the base insulating film 5 and the Si layer 6 formed thereon, the above problem becomes more serious.

As mentioned above, the problem of leakage current is that the SOI-MOSFET
The application of SOI to LSI has been hampered as an unavoidable obstacle in applying LSI to LSI.

[Object of the Invention]

An object of the present invention is to provide a semiconductor device having a MISFET having a small parasitic capacitance in the source and drain regions and a leakage current of 10 ⁻¹⁰ A / μm or less, and a method for manufacturing the same.

[Outline of Invention]

For example, silicon (Si) and oxygen (O) are chemically compatible with each other, and a chemical reaction between them, that is, oxidation of a Si substrate, especially O 2
Where Si penetrates into the substrate by diffusion and encounters Si,
Oxidation that forms an O bond forms a SiO ₂ layer / Si layer structure with very good interfacial properties. In other words, first, there is solid Si, which is oxidized to form a SiO ₂ film. At that time, the two points that O is supplied by diffusion are the conditions for forming a Si / SiO ₂ system having good interface characteristics. Looking at the conventional SOI technology from such a viewpoint, the method of forming the Si layer on the insulating film does not satisfy the requirement in the first place, and the method of forming the SiO ₂ layer in the Si substrate introduces O by ion implantation. I have not met because I am doing. Therefore, it is difficult to form a good interface.

The present invention was devised as a method satisfying the above conditions, based on the above consideration with silicon as an example. That is, the method for manufacturing a semiconductor device of the present invention comprises the steps of forming a cantilever beam or a cantilever beam (a minute bridge: hereinafter referred to as a microbridge) made of a semiconductor, and then performing the above-mentioned oxidation or nitridation. The upper and lower surfaces of the beam are
A step of covering with a second insulating film, and thereafter, at least one of the first and second insulating films is used as a gate insulating film, and the upper surface and the lower surface of the source and drain regions respectively have the first and second insulating films. MIS in contact with two insulating films respectively
Forming a type field effect transistor on the beam.

Further, the semiconductor device of the present invention includes a cantilever beam or a cantilever beam made of a semiconductor, and first and second insulating films that cover the upper surface and the lower surface of the beam, respectively.
At least one of the insulating films is a gate insulating film, and
A MIS type field effect transistor is formed on the beam such that the upper and lower surfaces of the source and drain regions are in contact with the first and second insulating films, respectively.

Further, the space between the beam and the substrate supporting the beam is vacuumed or filled with air or an inert gas.

That is, if the accumulation of heat during the operation of the SOI-MISFET can be reduced, the reliability of reducing the leakage current is improved. Therefore, in the present invention, a gas insulator is used for the I layer of SOI in place of a normal solid insulator. When gas is used, there is convection, and heat dissipation is good. Of course, also in this case, the lower surface of the semiconductor beam must be covered with an oxide film or a nitride film according to the method of the present invention in order to maintain good electrical characteristics of the interface. Therefore, the gate insulating film is made thin enough not to hinder the heat conduction from the semiconductor beam to the insulating gas. However, on the surface where the high impurity concentration regions such as the source and drain regions are exposed, the film formation rate of the insulating film is accelerated by the impurity effect, and the thickness becomes about three times as large as that of the gate insulating film. However, up to this level, there is no problem in heat dissipation.

Example of Invention

 Examples of the present invention will be described below.

Example 1 This example is an example in which a MOSFET is formed on a Si layer on an insulator.

As shown in FIG. 1 (A), a SiO ₂ film 8 having a thickness of 7,000 Å was formed on a single crystal Si substrate 7, and this was separated into rectangular islands by using a normal photolithography technique. At this time, Si
Instead of the O ₂ film, another insulating film such as Si ₃ N ₄ may be used.
The shape of the island may be circular, square, rectangular, or any other suitable shape. Polycrystalline Si film 9 with a thickness of 3500Å
It was deposited and then single crystallized by scanning with a laser beam. That is, the SOI structure was formed by the conventional SOI forming technique using laser annealing. In this case, SOI technology by strip heater annealing,
Alternatively, any other conventional SOI technique such as SOI technique utilizing solid phase growth of Si may be used. Next, a mask is applied to this and the SOI region is first etched by etching.
As shown in Figure (B), it was separated into several islands (2 in the figure).
One is illustrated). Then, the SiO ₂ film 8 was selectively etched to form a Si microbridge 30 as shown in FIG. 1 (C). This is subjected to thermal oxidation to cover the surface with a good quality 450 Å thick SiO ₂ film 8 and then a MOSFET using this SiO ₂ film 8 as the gate oxide film 4 is formed on the microbridge 30 using a normal process. It was made. Figure 1 (D)
A sectional view of the result is shown in FIG. In addition, instead of thermal oxidation,
Plasma or the like may be used oxide, which instead of SiO ₂ Si
_It may be replaced with another insulating film such as ₃ N ₄ . After that, if polycrystalline Si is embedded in the void 31 under the microbridge 30, the gate 1 can be formed in the lower layer as shown in FIG. 1 (E).

Example 2 In this example, a MOSFET was formed on a Si substrate, a microbridge was formed of Si on the MOSFET, a MOSFET was formed on the bridge, and a laminated integrated circuit was produced.

First, as shown in FIG. 2 (A), a MOSFET including a gate electrode 1, a source region 2, a gate region 3 and a gate insulating film 4 was formed on a Si substrate 7 by using a normal process.
On top of that, Si is formed by CVD (Chemical Vaper Deposition).
An O ₂ film 8 is deposited to a thickness of about 1.3 μm, and this is patterned into a rectangular shape by a known photolithography technique in the same manner as in Example 1, and a polycrystalline Si film 9 is deposited to a thickness of 3500 Å on the rectangular Si film 9. The deposited Si was single crystallized by scanning with a laser beam. At this time, needless to say, not only the SOI technique using the laser beam but also the SOI technique using the electron beam, the SOI technique using the solid phase growth, or the like may be used. By the way, the rectangular SOI regions were cut away by etching using a mask to form the shape shown in FIG. 2 (B).
However, at this time, d> W / 2 (see FIG. 2B. (D) is the thickness of the SiO ₂ film 8 remaining in the removed region, and W was not removed.
Width of SOI area. ) Was careful to meet the condition. Specifically, W = 0.8 μm and d = 0.8 μm. Next, the SiO ₂ film 8 is 0.5 μm thick by isotropic selective etching.
The SiO ₂ film 8 immediately below the Si film 9 in the SOI structure was removed by etching, and a Si microbridge 30 was formed as shown in FIG. 2 (C). At this time, since the etching depth of the SiO ₂ film 8 does not reach the gate oxide film of the MOSFET on the Si substrate 7, there is no fear of damaging the FET.
Since d> W / 2, this is the reason why such etching was possible. Next, as shown in FIG. 2 (D), a thin SiO ₂ film 8 having a thickness of 450 Å is formed by thermal oxidation, and then this SiO ₂ film is formed.
_{2 The} film 8 was used as the gate oxide film 4 and a MOSFET was formed on the microbridge using a normal process. Similar to the first embodiment, plasma oxidation or the like may be used for the oxidation.

After that, the voids under the microbridge were filled with SiO ₂ by the low pressure CVD method, and the entire surface of the substrate was covered with the SiO ₂ film 8. After that, though not shown, through holes were formed and wiring was formed using Al to complete a multilayer integrated circuit. In this embodiment, semiconductor layers having different conductivity types are formed in the upper and lower layers, and electrically between the gates and between one of the high-concentration impurity layers of the upper MOSFET and one of the high-concentration impurity layers of the lower MOSFET. Connected to form a CMOS inverter. Needless to say, the connection between the high-concentration impurity regions in the upper and lower layers may be formed by directly overlapping both impurity layers as shown in FIG. 2E without using wiring. .

Example 3 The structure shown in FIG. 2 (E) was formed by the process shown in Example 2. After that, the SiO ₂ film 8 was etched using a mask, leaving only the SiO ₂ film 8 on the microbridges (FIG. 3 (A)). Next, as shown in FIG. 3 (B),
By using the selective epitaxial growth method, the single crystal Si film 25 was deposited to the height of the microbridge and planarized only on the region where Si was exposed. By depositing this single crystal Si up to the height of the SiO ₂ film 8, a flatter structure can be obtained. After that, by using the process shown in Example 2, a microbridge was formed again, a MOSFET was formed in the layer, and the structure shown in FIG. 3B was formed. Provided on the surface
Although not shown, a through hole is formed in the SiO ₂ film 8,
Wiring was performed to complete a three-layer integrated circuit. However, in this example, polycrystalline Si having a high impurity concentration was used instead of Al wiring.

Example 4 This example is an example of manufacturing a joint gate CMOS using the present invention. At this time, the source and drain regions are above,
The lower layer was formed on the gate electrode by self-alignment.

As shown in FIG. 4 (A), prepared conductivity type monocrystalline Si substrate 7 of n-type, performs ion implantation 11 of boron using a mask 10 made of resist to a p ⁺ -type region 2 Formed. This region eventually becomes the source region of the underlying MOSFET. Next, as shown in FIG. 4 (B), an SOI structure is formed so as to partially overlap with the p ⁺ -type region by using the conventional SOI technique using laser annealing similar to that of the first embodiment. did. At this time, another SOI technique may be used as in the first embodiment. Further, the deposited single crystal Si film 9 was ion-implanted with boron to have a p-type conductivity type. Then, by masking this and etching, the SOI region was separated into some islands as shown in FIG. 1 (B) of the first embodiment. Next, on the substrate surface
A Si ₃ N ₄ film was deposited by the CVD method, this was etched using a mask, and formed into a shape as shown in FIG. 4 (C) (only one island region is shown in the figure. ). This Si ₃ N
_{The four} films 14 are used as a mask for ion implantation for forming a source and a drain, and for positioning the gate electrode formation. That is, first, boron was implanted at acceleration energy of 500 keV and 200 keV to form p ⁺ type regions 2 and 3 as shown in FIG. 4 (D). The p ⁺ type region 2 formed by overlapping the p ⁺ type region previously formed on the substrate before forming the SOI structure is a joint gate.
The CMOS is used as the source region 2 of the lower MOSFET, and the other p ⁺ type region is used as the drain region 3 of the lower MOSFET. Next, phosphorus ions were implanted at an acceleration energy of 200 keV to form n ⁺ conductivity type regions 12 and 13 in the deposited Si film 9 as shown in FIG. 4 (E). N ⁺ type region 12 in contact with the source region 2 in the lower layer makes MOSF in the upper layer
As the source region 12 of the ET, the n ⁺ type region 13 which is in contact with the lower drain region 3 is used as the upper drain region 13. Next, as shown in FIG. 4 (F), a resist 10 was applied to the surface of the substrate, and a mask 10 was formed as shown by cutting the pattern using a photolithography technique. Selective etching of Si ₃ N ₄ film is performed on this, and S
The Si ₃ N ₄ film around the OI island was removed, and then the resist 10 was removed to obtain the shape shown in FIG. 4 (G). By the way, when the sample is exposed to plasma, the surface of the sample is covered with an electric field region called a sheath. In the sheath, positive ions are accelerated toward the sample, so if plasma etching is performed in a region where the gas free pressure is sufficiently low and the mean free path of ions is equal to or greater than the thickness of the sheath, the ions are perpendicular to the surface of the object. Etching proceeds only in the direction. By selectively etching the SiO ₂ film 8 of this sample by utilizing this property, as shown in FIG. 4 (H), the SiO ₂ film 8 is scraped off except the shadowed portion of the Si ₃ N ₄ film 14. And Si microbridges are formed. The remaining
The SiO ₂ film 8 is a dummy gate. Subsequently, the Si ₃ N ₄ film 14 is removed by selective etching, and then FIG.
As shown in Fig. 3, the surface of the sample is thermally oxidized to a thickness of 1000 Å Si.
It was covered with an O ₂ film 8. Next, as shown in FIG. 4 (J), CV
The the Si ₃ N ₄ film 14 is deposited by method D, then, when the anisotropic etching 15, Si ₃ N ₄ except min the Si ₃ N ₄ film 16 filled in under the microbridge film 14 Are removed. Then, when the SiO ₂ film is selectively etched, the SiO ₂ film 17 under the microbridge is removed. Next, by thermal oxidation, as shown in FIG. 4 (K), a 250 Å-thick SiO film is formed on the lower surface of the microbridge and the substrate surface immediately below it.
_Two films were formed. This is the gate oxide film 4 of this joint gate CMOS. Thereafter, in the previous step shown in FIG. 4 (J), the CVD method was used to deposit the Si ₃ N ₄ film 16 under the microbridges and then anisotropically etch the same as the anisotropic etching. As shown in FIG. 4 (K), the polycrystalline Si film 1 having a high impurity concentration is formed by the reactive etching.
Was filled under the microbridge. This is the gate electrode 1 of the joint gate CMOS. By the above, the main part of the device was completed.

Therefore, next, processing is performed to enable electrical connection to the gate 1 and the sources 12 and 2 of the upper and lower layers, respectively. First, as shown in FIG. 4 (L), a resist 18 is applied to the surface of the sample. By using the photolithography technique, the resist in the region surrounded by the alternate long and short dash line in FIG. 4 (L) is removed, and the sample surface is etched until the gate electrode 1 buried under the microbridge is exposed. After that, if the resist 18 is removed, the sample is shown in FIG.
It has a shape shown in (N). As can be seen from the top view of FIG. 4 (N), the gate electrode 1 is exposed in a trapezoidal shape.
This is because the mask 14 when the dummy gate was formed had such a shape as shown in FIG. 4 (H).

Since the wiring is performed in this trapezoidal region, the contact resistance can be reduced. However, it is needless to say that it is not necessary to form the gate electrode 1 into such a divergent trapezoidal shape in applications where there is no problem even if the contact resistance of the gate is somewhat large. Since the mask for the dummy gate is also a mask for ion implantation for forming the source and drain, the source and drain end portions are naturally shaped like this. In this process, the gate electrode 1
Exposed part of, and the source 12 of the upper MOSFET and the lower
Separation from the source 2 of the MOSFET is completed. Finally, as shown in FIG. 4 (O), SiO _{2 was formed} by the bias sputtering method.
The film 8 was deposited, a contact hole was opened by etching using a mask, and wiring was performed using Al, whereby a joint gate CMOS was completed. It goes without saying that the joint gate CMOS in which the conductivity types shown in this embodiment are replaced by n and p can be manufactured by the same process.

Example 4- (2) This example is a simplified version of Example 4. That is, when it is necessary to suppress the parasitic capacitance between the source and the drain and the gate to be extremely small, the device of the fourth embodiment is required, while when this does not cause much problem, the device of the present embodiment is effective. Becomes

By the same method as the process described in Example 4, the structure shown in FIG. 4 (E) was formed. Next, the Si ₃ N ₄ film 14 was removed by a selective etching method, and then the SiO ₂ film 8 was removed by another selective etching method. By thermally oxidizing this, a SiO ₂ film 8 having a thickness of 250 Å was formed on the surface of the sample. Next, a high-impurity-concentration polycrystalline Si film 22 was formed on the surface of the substrate, on the microbridges, and under the microbridges by the low-pressure CVD method to obtain the structure shown in FIG. 4 (P) (cross-sectional view). Next, anisotropic etching was used to remove the polycrystalline Si film 22 on the microbridge and on the substrate other than the portion used as a lead electrode of the gate electrode later. In addition to this, in Example 4, FIG.
In the same manner as shown in (M), application of resist and partial removal thereof and etching using the resist as a mask were performed to separate the source 12 of the upper layer MOSFET from the source 2 of the lower layer MOSFET. (Fig. 4 (Q)). After that, the sample was treated with a passivation film (SiO ₂ film 8) in the same manner as in Example 4.
The joint gate CMOS was completed by covering it with, making a contact hole in it, and then wiring. It goes without saying that, also in this embodiment, a joint gate CMOS in which the conductivity types are switched between n and p can be manufactured by the same process.

Example 5 In the process shown in Example 4, the ion implantation 11 shown in FIG. 4 (A) is omitted, the conductivity type of the deposited Si film 9 is selected to be the same as the conductivity type of the substrate 7, and the source and drain are formed. All ions forming the same conductivity type are selected for the ion implantation for, and the step of separating the source regions 12 and 2 of the upper and lower layers is omitted, so that one gate 1 drives the channels of the upper and lower layers at the same time. A MOSFET that can be used was manufactured. This is equivalent to doubling the channel width without increasing the parasitic capacitance of the source and drain as compared with the conventional MOSFET, and therefore the transfer conductance gm of double the value was obtained.

Example 6 In this example, one of the new-structure MOSFETs described above was manufactured by using the present invention.

The structure shown in FIG. 1C is formed by the same method as the process described in the first embodiment, and is deposited by ion implantation.
The conductivity type of the Si film 9 was made the same as that of the substrate 7, and this was covered with an oxide film 8 having a thickness of 250 Å by thermal oxidation. Next, a polycrystalline Si film 22 having a high impurity concentration was deposited by the CVD method, and a mask 10 was formed thereon as shown in FIG. 5 (A). By anisotropically etching this, the polycrystalline Si film 22 was left only under the mask 10 and under the microbridges. Next, as shown in FIG. 5 (B), the shadowed portion of the mask 10 is removed by anisotropic etching utilizing the sheath electric field used when forming the dummy gate of the fourth embodiment. The polycrystalline Si film 22 was removed while remaining. Then, the mask 10 is removed, and as shown in FIGS. 5 (C) and (D), a 500Å oxide film 8 is formed on the surface of Si by thermal oxidation, and the polycrystalline Si film 22 is used as a mask for ion implantation. By doing so, the source 2 and the drain 3 were formed in the microbridge. In the case of an application in which the parasitic capacitance between the source 2 and the drain 3 and the gate electrode 1 does not matter so much, the usual anisotropic etching may be used instead of the etching using the sheath electric field. In that case, all of the polycrystalline Si film 22 under the microbridge remains, and the finished form of the device is as shown in FIGS. 5 (E) and 5 (F). Further, although thermal oxidation was used in this example, instead of this, plasma oxidation, magnetic field microwave plasma CVD
Etc. may be used.

Example 7 In the process of Example 6, before the ion implantation for forming the source 2 and the drain 3 in the microbridge, the ions having the same conductivity type as the source 2 and the drain 3 of the microbridge are transferred to the substrate. A step of implanting with high acceleration energy to reach 7 was inserted to form a MOSFET having the structure shown in FIG. With this configuration, the transfer conductance gm can be tripled or more in this embodiment.

Example 8 Si deposited by ion implantation in the process of Example 6
Instead of the step of making the conductivity type of the film 9 the same as that of the substrate 7, deposition
A step of selecting ions for making the conductivity type of the Si film 9 opposite to the conductivity type of the substrate 7 and implanting the ions is performed, and before the ion implantation for forming the source 12 and the drain 13 in the microbridge, A process of selecting ions having a conductivity type opposite to the conductivity type of the source 12 and drain 13 of the bridge and implanting them with high acceleration energy to reach the substrate 7 is further inserted, and further, the sources 2 and 12 and the drains 3 and 13 are inserted. Then, the source 2 formed on the substrate 1 by removing a part of the source region 12 of the deposited Si 9 by etching using a mask
A MOSFET of the form shown in FIG. 7 was produced by inserting a step of separating This is a joint gate CMOS in which the upper layer MOSFET is the MOSFET described in the sixth embodiment.
Is.

As described above, some of the embodiments have been described.
(FIG. 1 (D)), Example 2 (FIG. 2 (D)), Example 6 (FIG. 5 (D)), Example 7 (FIG. 6), Example 8
In (Fig. 7), an air layer is used for interlayer insulation between the upper MOSFET and the lower MOSFET or the substrate 7, but here
It goes without saying that other insulating materials such as SiO ₂ and Si ₃ N ₄ may be filled. However, the smaller the dielectric constant of the interlayer insulating film, the better. Therefore, vacuum having the smallest dielectric constant is preferable, and nitrogen or air corresponding to the vacuum is preferable next. In addition, in the above-mentioned example, when mounting the manufactured element, a method of sealing with dry nitrogen was adopted.

In addition, in the above-mentioned embodiment, a device having a two-layer or three-layer structure of a deposited Si layer and a Si substrate was manufactured. If several microbridges are further stacked on this device, four layers are obtained by using the method described in the above-mentioned embodiment. It goes without saying that the above device can be manufactured. Furthermore, it goes without saying that in the device of Example 2 and its multi-stage structure, elements other than MOSFETs, such as capacitors, can be fabricated in the microbridge or on the substrate.

In the above example, the interface state density between the Si film formed on the insulator and the insulator could be made extremely small, about 2 × 10 ⁻¹⁰ cm ⁻² . As a result, even if the channel stopper is not formed here, the leakage current between the source and drain of the MOSFET formed on the Si film is produced on the Si substrate.
Could be as small as or smaller than.

〔The invention's effect〕

As described above, according to the present invention, a base insulating film,
The interface characteristics with the semiconductor layer formed on the insulating film are significantly improved, and the leak current between the source and drain regions transmitted through the interface can be suppressed to 10 ⁻¹⁰ A / μm or less. As a result, it became possible to operate the SOI-MISFET with low power consumption and to use the underlying insulating film as a gate insulating film, and the basic process of MISFET with low power consumption and high speed operation was established.

[Brief description of drawings]

1 (A) to (E) are views showing a first embodiment of the present invention, FIGS. 2 (A) to (E) are views showing a second embodiment of the present invention, and FIG. A) and (B) are diagrams showing a third embodiment of the present invention, FIGS. 4 (A) to (Q) are diagrams showing a fourth embodiment of the present invention, and FIGS. F) is a diagram showing a sixth embodiment of the present invention, FIG. 6 is a diagram showing a seventh embodiment of the present invention,
FIG. 7 is a diagram showing an eighth embodiment of the present invention, and FIG. 8 (A).
Is a cross-sectional view showing the basic structure of a future laminated integrated circuit, FIG. 8B is a cross-sectional view showing a future new-structure transistor, and FIG.
FIGS. 9A to 9C are views showing the concept of the structure of the joint gate CMOS. DESCRIPTION OF SYMBOLS 1 ... Gate electrode, 2 ... Source region 3 ... Drain region, 4 ... Gate insulating film 5 ... Base insulating film 6 ... Si film in SOI structure 7 ... Si substrate, 8 ... SiO ₂ film 9 ... Single crystallized deposited Si film 10 ... Mask, 11 ... Ion implantation 12 ... Source region of upper layer MOSFET 13 ... Drain region of upper layer MOSFET 14 ... Si ₃ N ₄ film, 15 ... Anisotropic etching 16 ... Si ₃ N ₄ film filled under microbridge 17 ... SiO ₂ film filled under the microbridge 18 ... Resist, 19 ... Gate electrode terminal 20 ... Source electrode terminal of upper layer MOSFET 21 ... Source electrode terminal of lower layer MOSFET 22 ... Polycrystalline Si film with high impurity concentration 23 ... Source Electrode terminal, 24 ... Drain electrode terminal 30 ... Micro bridge

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H01L 27/088 27/12 F 29/78 7514-4M H01L 29/78 301 X 8934-4M 27 / 08 102 E

Claims (3)

[Claims] 1. A step of forming a cantilever beam or a cantilever beam made of a semiconductor material, and a step of coating the upper and lower surfaces of the beam with a first insulating film and a second insulating film, respectively, by oxidation or nitriding. And further thereafter, at least one of the first and second insulating films is used as a gate insulating film, and a source,
The upper surface and the lower surface of the drain region are respectively
And a step of forming MIS type field effect transistors in contact with the second insulating film on the beam, respectively. 2. A cantilevered beam or a cantilevered beam made of a semiconductor, and a first beam for covering an upper surface and a lower surface of the beam, respectively.
A second insulating film, wherein at least one of the first and second insulating films serves as a gate insulating film, and the upper and lower surfaces of the source and drain regions respectively have the first and second insulating films. A semiconductor device having MIS type field effect transistors which are respectively in contact with the beam are formed on the beam. 3. The semiconductor device according to claim 2, wherein a space between the beam and a substrate supporting the beam is vacuumed or filled with air or an inert gas.