JPH04280456A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To easily form a via hole low in resistivity and small in installation area by providing an SOI element substrate with a through hole covered with an oxide film and a conductor, and electrically connecting the conductor to the wiring provided on an element formation layer and the supporting substrate. CONSTITUTION:For a Silicon on Insulator(SOI) element substrate, a silicon element formation layer 3 is provided, across a buried insulating layer 2, on the silicon supporting substrate 1. And a through hole 13 is provided, which pierces the element formation layer 3 and the buried insulating layer 2 and the inside of which is covered with an oxide film 8A, and then a selectively deposited conductor 10 is made by stopping this through hole 13. The conductor 10 is electrically connected to the wiring 11 on the element formation layer 3 and the supporting substrate 1. Moreover, the via hole 14 is made of a metal small in resistivity and contact resistance. Hereby, a via hole 14 low in wiring resistance and small in installation area can be formed easily.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to semiconductor devices, particularly SOI
The present invention relates to a structure of a via hole connecting surface wiring and a silicon support substrate in an element substrate and a method for manufacturing the same.

[0002] SOI element substrates, in which a silicon element formation layer is provided on a silicon support substrate with an insulating film sandwiched between them, are expected to be suitable for high-speed, high-integration integrated circuit substrates because of their complete insulation isolation. .

[0003] However, SOI with complete isolation
In an element substrate, in order to control the potential between the element formation layer on which the element is formed and the support substrate, it is necessary to establish electrical continuity between the wiring provided on the element formation layer and the support substrate. .

[0004] Therefore, in order to short-circuit the wiring on the element forming layer and the SOI element substrate, there is a need for a via hole that has low electrical resistance and can be formed in a small area.

[0005]

2. Description of the Related Art The structure of a conventional via hole and its manufacturing method will be explained with reference to FIG. FIG. 3 is a cross-sectional view of a conventional embodiment, showing transistors, via holes, and wiring formed on an SOI element substrate.

Referring to FIG. 3, a conventional via hole 34 uses impurity-doped polysilicon 35 as a conductive material. By using such polysilicon 35, the conventional via hole 34 inevitably has the following structure.

That is, since polysilicon 35 has a high specific resistance, the diameter of via hole 34 must be increased in order to lower the wiring resistance. In addition, since the ohmic contact between the polysilicon 35 and the support substrate 1 has a high contact resistance,
Ohmic contact surface 3 with a larger area than the via hole 34
6 is required. Therefore, the ohmic contact surface 3 between the polysilicon 35 forming the via hole 34 and the supporting substrate 1
6, it is necessary to over-etch the buried insulating layer 2 to widen the contact area. Therefore, a substantially large area is required to install the via hole.

Furthermore, polysilicon 35 and element forming layer 3
Since the area 38 where the via hole 34 is to be formed must be insulated and isolated by the trench insulation part 31 filled with an oxide film and the field oxidation part 32, the area 38 must be insulated and isolated. Since this insulated region must be specially provided for the via hole, the area required for forming the via hole increases significantly.

Conventionally, the following manufacturing process has been used to form a via hole with such a structure. First, simultaneously with the formation of the transistor regions 39 and 40, the via hole region 38 is formed by providing a trench insulating section 31 and a field oxidation section 32.

Next, a hole to become a via hole 34 is formed in the element forming layer 3 by photo-etching. Next, the buried insulating layer 2 is over-etched using isotropic etching.

Next, the holes are filled with impurity-doped polysilicon 35 by repeating alternately the deposition of polysilicon and the implantation of impurity ions. Next, the polysilicon deposited on the element forming layer 3 is removed.

Next, after depositing an oxide film 33 and providing an opening in the oxide film 33 on the doped polysilicon 35, the wiring 1
1 will be provided. Finally, a PSG (phosphide glass) layer 6 is provided as a protective film.

In such a process, the buried insulating layer 2 is over-etched, which tends to cause damage to the element forming layer 3, and when polysilicon is buried in the over-etched part of the buried insulating layer 2, cavities are generated. resistance tends to increase.

Furthermore, the alternating polysilicon deposition and ion implantation steps and the removal of the polysilicon deposited on the element forming layer 3 require a lot of time.

[0015]

[Problem to be solved by the invention] Conventional via holes are
Since polysilicon with high resistivity is used and an isolated region is required, a large area is required to form a via hole. For this reason, it is not possible to achieve high integration of semiconductor integrated circuits, and also it is not possible to provide via holes close to circuit elements such as transistors, resulting in the problem that high speed cannot be achieved.

Furthermore, the formation of via holes requires over-etching, which tends to cause breakage and defects, and there are also problems in that it takes a long time to deposit and form polysilicon.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device and a method for manufacturing the same, in which a via hole with low wiring resistance and a small installation area can be easily formed.

[0018]

[Means for Solving the Problems] FIG. 1 is a process diagram of an embodiment of the present invention, and shows a via hole forming process in a sectional view. Note that FIG. 1(f) shows a completed via hole.

Referring to FIG. 1, the structure of the present invention to achieve the above object is as follows: A first structure includes an element forming layer made of silicon on a supporting substrate 1 made of silicon with an embedded insulating layer 2 sandwiched therebetween. SOI (Silicon
(on Insulator) In the element substrate, there is a through hole 13 that penetrates the element forming layer 3 and the buried insulating layer 2 and whose inner surface is covered with an oxide film 8A, and a conductive film selectively deposited to fill the through hole 13. conductor 10, and the conductor 1
0 is characterized in that it is electrically connected to the wiring 11 provided on the element forming layer 3 and the support substrate 1, and the second structure is characterized in that the conductor 10 is made of tungsten. , copper, titanium, and aluminum, and the third structure is characterized in that the element forming layer 3 and the buried insulating layer 2 are formed by anisotropic RIE (reactive ion etching). a step of drilling a hole 12 that reaches the support substrate 1 through the hole 1;
2 and the bottom surface of the hole 12 in contact with the supporting substrate 1, and removing the oxide film 8B on the bottom surface of the hole 12 by anisotropic RIE to form the through hole 1.
3, a step of selectively growing the conductor 10 from the bottom surface of the through hole 13 by CVD (chemical vapor deposition method) to fill the through hole 13, and a step of forming the wiring 11 on the conductor 10. and a step of providing the element forming layer 3 on the element forming layer 3 in contact with the element forming layer 3.

[0020]

[Operation] The operation of the structure of the present invention will be explained with reference to FIG. The via holes according to the first and second configurations of the present invention are made of a metal having a low resistivity, for example, in the second configuration, Cu, Al,
The conductor 10 is composed of Ti and W as materials.

Therefore, the wiring resistance can be made sufficiently low even with a via hole having a small cross section. Furthermore, the contact resistance between the metal constituting the conductor 10 and the silicon support substrate 1 is different from that of the conventional ohmic contact between polysilicon and the support substrate due to the formation of the high impurity concentration region 9 near the surface of the support substrate 1. can be significantly lower in comparison.

Therefore, even if the contact area is small, the contact resistance is sufficiently low, so there is no need to over-etch the buried insulating layer to widen the bottom surface of the via hole in order to increase the contact area as in the conventional method.

Therefore, the cross-sectional area of the via hole 14 including the contact portion with the substrate 1 can be reduced. Further, in the via hole 14 according to the present invention, the inner surface of the through hole 13 is covered with an oxide film 8A and is insulated from the silicon element forming layer 3.

Therefore, there is no need to provide a special insulated region to form the via hole 14. Therefore, the area required to form the via hole 14 can be made smaller than that of a conventional via hole because an insulation isolation region is not required.

According to the third configuration of the present invention, since there is no need for over-etching, RIE, which has strong anisotropy, can be used to form the holes 12 for forming the via holes 14.

Therefore, the element forming layer is not damaged due to over-etching, and the via hole 14 can be formed precisely. Further, in the present invention, a configuration is adopted in which, prior to depositing the conductor 10 by CVD, the surfaces other than the bottom surface of the through hole 13 are covered with oxide films 4 and 8A.

Therefore, the conductor 1 that does not grow on the oxide film
0 selectively grows only from the bottom surface of the through hole 13, and is deposited sequentially upward from the bottom of the via hole 14, filling the through hole 13.

[0028] Therefore, defects such as cavities are less likely to occur. Also,
When the conductor is deposited, the surface of the element forming layer 3 is covered with an oxide film or nitride film and no conductor is deposited, so the process of removing it by photo-etching as in the prior art polysilicon is not necessary, and the formation of the via hole 14 is eliminated. becomes easier.

[0029]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be explained based on an embodiment with reference to FIG. The SOI element substrate used had a support substrate 1 made of silicon, a buried insulating layer 2 made of an oxide film with a thickness of 300 nm sandwiched therebetween, and an element formation layer 3 made of silicon with a thickness of 4 μm provided thereon.

First, referring to FIG. 1(a), the surface of the element forming layer 3 is thermally oxidized to form an oxide film 4 having a thickness of 30 nm. Next, a nitride film 5 with a thickness of 200 nm and a thickness of 1500 nm are formed.
After depositing the PSG layer 6 and the resist 7, the resist 7
is exposed and patterned.

Next, the patterned resist 7
As shown in FIG. 1(a), the PSG layer 6,
The nitride film 5 is patterned.

Next, after removing the resist 7 and the PSG layer 6, referring to FIG. 1(b), holes 1 are formed in the element forming layer 3 by RIE using HBr gas using the nitride film 5 as a mask.
2, the buried insulating layer 2 on the bottom of the hole 12 is removed by RIE using a mixed gas of CF4 and H2, thereby completing the hole 12. Note that the PSG layer 6 may be removed after the hole 12 is completed.

Next, referring to FIG. 1C, oxide films 8A and 8B having a thickness of, for example, 30 nm are formed on the exposed silicon surface of the hole 12 by thermal oxidation or CVD. When using CVD, there is no problem even if an oxide film is formed on the surface of the nitride film.

Next, impurity ions are implanted through the oxide film 8B formed at the bottom of the hole 12. This is to form a high concentration region 9 of impurities in order to reduce contact resistance. For example, phosphorus ions are accelerated at a voltage of 70 keV.
The injection amount is 1 x 1016 cm-2.

Next, referring to FIG. 1(d), the nitride film 5
Using the oxide film 8B on the bottom of the hole 12 as a mask, CF4
The through holes 13 are formed by RIE using a mixed gas of H2 and H2.

Next, the nitride film 5 is removed using hot phosphoric acid. Next, the oxide film 8 is etched using isotropic dry etching.
By etching several nanometers of the surface of A and the high concentration region 9, the natural oxide film formed on the bottom surface of the through hole 13 is removed. This isotropic dry etching is performed using, for example, NF3 at a flow rate of 10 sccm and H2 at a flow rate of 100 sccm.
This can be achieved by turning a mixed gas of 10 to 50 W into plasma under high frequency power of 10 to 50 W and exposing it for 20 seconds.

Following the above steps, referring to FIG. 1(e), a conductor 10 is selectively grown on the bottom surface of the through hole 13 by CVD, and the through hole 13 is filled with the conductor 10. Conductor 1
The conditions for selective growth of 0 are, for example, a flow rate of 7 s for W metal.
A mixed gas of WF6 at a flow rate of 4.9 sccm, SiH4 at a flow rate of 4.9 sccm, and H2 at a flow rate of 1000 sccm is passed, and the pressure is 0.2 torr and the substrate temperature is 280 to 290°C. It goes without saying that the present invention is applicable to any good conductor that can be selectively grown.

Next, referring to FIG. 1(f), the wiring 11
The via hole 14 is completed by connecting it to the conductor 10 using, for example, an Al-1% Si alloy deposited by sputtering.

FIG. 2 is a sectional view of an embodiment of the present invention.
It shows a part of a semiconductor integrated circuit in which a via hole 14 is formed in an I-element substrate. This integrated circuit has a MOS transistor region 39 and a bipolar transistor region 40.
After insulating and forming a trench insulating part 31 filled with an oxide film and a field oxidizing part 32, a through hole (shown as 13 in FIG. 1) is formed, an active region of the transistor is formed, and then a via hole 14 is formed. Then, electrodes and wiring 11 are formed.

In this embodiment, the via hole 14 is provided adjacent to the MOS transistor region 39 as part of the insulation isolation. Therefore, since it can be provided close to the transistor, the performance of the element can be improved.

[0041] Furthermore, there is an effect that the substantial area required for forming the via hole 14 can be reduced. Furthermore, according to the present invention, regardless of insulation isolation,
Since the via hole 14 can be formed at any position, the degree of freedom in design is increased.

[0042]

[Effects of the Invention] As explained above, according to the present invention, the via holes are made of a metal with low specific resistance and contact resistance, and are insulated with an oxide film, so that over-etched and insulated regions can be avoided. Since it is not necessary to provide a via hole, it is possible to easily form a via hole with low wiring resistance and a small installation area, which greatly contributes to improving the performance of semiconductor devices.

[Brief explanation of the drawing]

[Figure 1] Example process diagram of the present invention

[Figure 2] Cross-sectional view of an embodiment of the present invention

[Figure 3] Cross-sectional view of conventional embodiment

[Explanation of symbols]

1 Support board 2 Embedded insulation layer 3 Element formation layer 4 Oxide film 5 Nitride film 6 PGS layer 7 Resist 8A, 8B Oxide film 9 High concentration area 10 Conductor 11 Wiring 12 Hole 13 Through hole 14 Beer hall 31 Trench insulation part 32 Field oxidation section 33 Oxide film 34 Beer hall 35 Polysilicon 36 Ohmic contact surface 37 Contact surface 38 Via hole formation area 39 MOS transistor area 40 Bipolar transistor area

Claims (3)

[Claims] 1. An SOI (Silicon o
nInsulator) In the element substrate, a through hole (13) whose inner surface is covered with an oxide film (8A) that penetrates the element forming layer (3) and the buried insulating layer (2); A conductor (10) is buried and selectively deposited, and the conductor (10) is connected to the wiring (11) provided on the element forming layer (3) and the supporting substrate (1). A semiconductor device characterized by being electrically connected. 2. The semiconductor device according to claim 1, wherein the conductor (10) is made of any one of tungsten, copper, titanium, and aluminum. 3. A hole (12) is formed by anisotropic RIE (reactive ion etching) to penetrate the element forming layer (3) and the buried insulating layer (2) and reach the support substrate (1).
) and forming an oxide film (8A, 8
B) and the hole (12
) by removing the oxide film (8B) on the bottom surface of the through hole (13).
), a step of filling the through hole (13) by selectively growing the conductor (10) from the bottom surface of the through hole (13) by CVD (chemical vapor deposition); 3. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of providing a conductor (11) on the element formation layer (3) in contact with the conductor (10).