JPS63170922A - Wiring method - Google Patents

Abstract

PURPOSE:To provide a contact hole of predetermined diameter with good controlability by selectively forming an opening to a polycrystal silicon formed on a gate insulation film of substrate, etching a gate insulation film with such polycrystal silicon layer used as the mask and forming wirings covering the exposed region of etched semiconductor substrate and the upper part of gate insulation film. CONSTITUTION:A polycrystalline silicon layer 5 is provided between a photoresist layer 3 and an oxide film 2, the polycrystalline Si layer 5 is patterned by the dry etching and an oxide film 2 of the buried contact part is removed by the wet etching using such opening. In this case, damage by ion bombardment at the time of dry etching remains only on the oxide film 2 and is never generated at the surface of Si substrate 1 under such oxide film. Moreover, there is no chance of generating over-etching due to invasion of HF solution to the interface of such elements. Thereby, the buried contact can be formed between the polycrystal Si layer 4 and the Si substrate 1.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an electrode wiring method for a semiconductor device.

[Summary of the invention]

The present invention provides a method for making contact between the wiring layer and the semiconductor substrate by opening a window in the gate oxide film on the semiconductor substrate and providing a wiring layer. A St layer is formed, an opening is selectively formed in the polycrystalline Si, and the gate insulating film is etched using the polycrystalline St layer as a mask, and the exposed portion of the etched semiconductor substrate and the gate insulating film are etched. By forming wiring over the top, it is possible to open a contact hole of a desired diameter with good controllability.

[Conventional technology]

A buried contact, also called a diffusion contact, is a means for connecting an active region of a semiconductor device, such as a source and drain region, to the outside, and is formed of a polycrystalline semiconductor material. Forming connection leads and buried contacts using such polycrystalline semiconductor materials is advantageous for integration in that the number of mask steps can be reduced compared to forming conventionally used metal contacts. (Tokuko Showa 5
(No. 47852).

A conventional method for forming buried contacts will be explained based on FIG. First, a thick field oxide film 2 is formed on a P-type Si substrate l to separate device regions into islands, and then thermal oxidation is performed to form a thin oxide film 2' that will become a gate insulating film on the exposed surface of the substrate in the device region. (Figure 2A).

Next, a photoresist layer 3 is formed and buried contacts (
Photoresist layer 3 in the area where direct contact is to be formed
remove. After this, the wafer is immersed in a buffered HF solution,
The gate oxide film 2' at the buried contact portion is removed (FIG. 2B).

Finally, after growing a polycrystalline St layer 4 or a silicide layer over the entire surface by CVD, P is doped and the Si
It is diffused into the substrate to form an N″ region 6. This forms a buried contact between the Si substrate 1 and the polycrystalline St layer 4 (or silicide layer) (FIG. 2C).
(Unexamined Japanese Patent Publication No. 112372/1982) [Problems to be Solved by the Invention] As the integration of semiconductor devices progresses, the size of the window to be opened in photoresist has become smaller, and the thickness of photoresist has generally increased to 1. ~1.57151), which is not much different. When the diameter a of the opening in the photoresist layer shown in FIG. 2B becomes about 11 m, the aspect ratio a/'b with the thickness b of the photoresist layer becomes 1 or less. In such a state, the etching solution cannot be reliably circulated around the contact forming portion, and some of the several million contacts that exist in one device are not completely etched. As a result, a problem has arisen in that highly integrated semiconductor devices cannot be manufactured with good yield.

On the other hand, since the adhesion between the photoresist and the oxide film is generally not good, as shown in Figure 2B, the buffered HF solution seeps into the gap between the photoresist layer 3 and the oxide film 2, causing the buried contact to become unnecessarily deep. There was also the problem of increasing the size.

Note that instead of wet etching using a buffered HF solution in the step shown in FIG. The remaining problem is that this leads to an increase in contact resistance. This damage formed on the Si surface is removed by etching with ammoniated water, but at this time the oxide film is also removed. For these reasons, conventionally, buried contacts have not been formed by dry etching.

[Means for solving problems]

The present invention provides a method for making contact between the wiring layer and the semiconductor substrate by opening a window in the gate oxide film on the semiconductor substrate and providing a wiring layer. A Si layer is formed, an opening is selectively formed in the polycrystalline Si, and the gate insulating film is etched using the polycrystalline St layer as a mask. The above problem was solved by forming wiring over the top.

[For production]

In the contact forming method of the present invention, as shown in FIG. The oxide film 2 at the buried contact portion is removed by wet etching using the opening. The damage caused by ion bombardment during dry etching in Figure 1C is due to the damage to the oxide film 2.
There is no damage to the surface of the Si substrate 1 underneath.

In addition, in the wet etching process shown in Figure 1, since there is no interface between the photoresist layer and the oxide film, the HF solution enters the interface and causes overetching, unlike in conventional contact formation methods. No worries.

〔Example〕

The contact forming method of the present invention will be explained based on FIGS. 1A to 1E.

A. After forming a thick field oxide film 2 by a conventional method, a 500-layer gate oxide film 2' is grown by thermal oxidation.

B. A polycrystalline Si layer 5 of 500 layers is formed over the entire surface by CVD.

A C photoresist film 3 is formed, and openings are made in portions corresponding to buried contacts. Using this patterned photoresist film 3 as a mask, the polycrystalline Si layer 5 is subjected to RIE.
Dry etching by method etc.

D After removing the photoresist film 3, the wafer is immersed in a buffer 11F solution to remove the gate oxide film 2' and expose the surface of the Si substrate 1.

E After growing the polycrystalline Si layer 4 by CVD method, P
is doped into this, and the P is diffused into the Si substrate I to form N.
” 85 region 6 is formed. This forms a buried contact between the polycrystalline Si layer 4 and the Si substrate 1. Note that a material such as silicide used for the gate electrode may be used instead of polycrystalline 5ilJO. It is also possible to do so.

Although the polycrystalline Si layer 5 is not doped with a dopant,
Since this polycrystalline Si layer 5 is thin, the resistance can be sufficiently reduced by the diffusion of P doped into the polycrystalline Si layer-4.
This polycrystalline Si layer 4.5 does not cause any problem as a wiring electrode.

Furthermore, when the thickness of the polycrystalline Si layer 5 is 1000 Å or more, when patterning the wiring layer made of the polycrystalline Si layer 4.5 shown in FIG. Since there is a problem that the polycrystalline Si layer 5 becomes extremely thin, it is desirable that the thickness of the polycrystalline Si layer 5 is 1000 Å or less.

The present invention can also be applied to an oxide film for forming an ion implantation mask that is formed by thermal oxidation on the source and drain regions after forming the gate electrode.

〔Effect of the invention〕

In the method of the present invention, when the gate oxide film in the contact area is removed by etching with a strong solution, the mask is not a photoresist as in the conventional method but a thin polycrystalline Si layer, so the following effects can be obtained. It will be done.

(i) Since the ratio between the diameter of the buried contact and the thickness of the thin polycrystalline Si layer that is the mask material is much smaller than 1,
The permeability of the HF solution into the buried contacts is extremely good, and the production yield is significantly improved.

(ii) The mask material is not photoresist but polycrystalline St.
Therefore, the adhesion between the mask and the oxide film is significantly improved compared to conventional manufacturing methods.

Therefore, the HF solution does not penetrate between the mask and the oxide film and enlarge the buried contact, and a contact hole of a desired diameter can be formed with good controllability.

[Brief explanation of the drawing]

1A to 1E illustrate the wiring method of the present invention. 2A-2C illustrate a conventional contact formation method.

Claims (1)

[Claims] A step of forming a polycrystalline silicon layer on a gate insulating film formed on a semiconductor substrate; a step of selectively forming an opening in the polycrystalline silicon layer; and a step of forming an opening in the polycrystalline silicon layer. A wiring method comprising: etching a gate insulating film using as a mask; and forming a wiring layer covering the exposed portion of the etched semiconductor substrate and the upper part of the gate insulating film.