JPS5943832B2 - Manufacturing method of semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and an object of the present invention is to provide a structure with a flatter surface and fewer steps, and to increase the height of the semiconductor device by making the contact portion between the semiconductor and metal wiring the required minimum size. An object of the present invention is to provide a method for manufacturing a highly densified semiconductor device.

First, according to FIG. 1, a conventional so-called silicon gate M
An example of a method for manufacturing an OS type field effect transistor will be described.

A field oxide film 2 is uniformly formed to a thickness of about 0.7μ on one main surface of a semiconductor substrate 1 of one conductivity type, for example, a P type (first
Diagram a).

After removing the field oxide film on the source, drain and gate regions and exposing the part 3 on the semiconductor substrate 1 b)
A gate oxide film 4 is formed on the exposed portion 3 of the semiconductor substrate to a thickness of approximately 0.1μ.
After forming a polycrystalline silicon film uniformly over the entire surface, a polycrystalline silicon pattern 5 is formed on the gate region and field oxide film.This polycrystalline silicon pattern 5 is used to etch the gate oxide film. , e exposing a portion 6 of the semiconductor substrate. Thereafter, impurities of a conductivity type opposite to that of the semiconductor substrate 1, for example, an n-type, are diffused to form a source 7 and a drain 8. Thereafter, a thermal oxide film and a silicon dioxide film 9 are formed by CVD. Open the windows for making contact and form windows 10, 11, and 12. Then, by forming the source, gate, and drain electrode wirings 13, 14, and 15, by using the polycrystalline silicon film 5 as a gate in this way, self-aligned diffusion of the source and drain can be achieved. Regarding the extension part of the gate electrode 5 provided on the field oxide film 2 to form the polycrystalline silicon film, the portion shown in FIG. The etching of the field oxide film 2 during this process produces a large step as shown in FIG. 2c.

Furthermore, when silicon oxide film 9 is formed by the CVD method, the thickness grown on polycrystalline silicon is larger than the thickness grown on field oxide film 2, which tends to further increase the step difference. Because of these steps, for example, when another metal wiring such as Al is provided across a polycrystalline silicon film for a gate, the metal becomes thinner at the steps and wire breaks are likely to occur. Metal wiring of similar thickness was required. In order to form a pattern on such thick metal wiring, the pattern structure had to have a large margin. Also, when forming contact windows 10, 11, and 12 in the silicon dioxide film, the impurity diffusion layers 7, 8 and the polycrystalline silicon pattern 5 are used to absorb mask misalignment and variations in window size. ' to the required contact windows 10, 11,
It had to be larger than 12. As described above, the conventional method shown in FIG. 1 creates a step on the surface and requires a large contact area, which hinders high density and high integration.

The present invention has been made in view of these circumstances, and is intended to achieve higher density.

An embodiment of the present invention will be described with reference to FIGS. 3 and 4. FIG. For the sake of simplicity, a MOS field effect transistor, which is a basic element of a semiconductor device, will now be explained. A first insulating layer, such as a silicon dioxide film, is formed on one main surface of a semiconductor substrate of one conductivity type, such as a P-type silicon substrate 21.
After forming a layer of approximately 0.1 μm in an oxygen atmosphere at a temperature of 100° C., holes are formed in the source and drain contact portions 22 by ordinary photolithography to form first insulating layers 23 and 24 having a first pattern. The semiconductor substrate 21 is exposed (FIG. 3a).

Next, a polycrystalline silicon film 25 having a thickness of approximately 4000λ is formed on the silicon dioxide films 23, 24 and the exposed portion 22 of the semiconductor substrate by thermal decomposition of SiH4, SiCl4, or the like.

In this case, depending on the growth conditions, a single crystal silicon film grows on the exposed substrate portion 22 for source and drain contacts, but since this does not change the effect of the present invention in any way, a polycrystal silicon film will be used in the following explanation. treated as This polycrystalline silicon film 25 is used to connect the gate electrode, source, drain, and metal wiring, so it must have high electrical conductivity. For this reason, the polycrystalline silicon film 25 may be grown so as to contain n-type impurities in advance, or, of course, the n-type impurity may be diffused after the polycrystalline silicon film is grown. Next, approximately 1,000 oxidation-resistant films 26, such as Si3N4 films, are formed on the polycrystalline silicon film.The oxidation-resistant film 26, polycrystalline silicon film 25, and first insulating layer are selected using a BO normal photolithography technique. The oxidation-resistant film 27, 2
8, 29, C forming a second pattern consisting of polycrystalline silicon films 30, 31, 32 and gate oxide film 23;

That is, 30 and 32 are source and drain contact regions, and 31 is a gate electrode. Next, a silicon dioxide film 40 is formed as a fourth layer on the entire surface by, for example, vapor phase growth (CVD) of SlH4 and 02 or thermal oxidation to a thickness of, for example, about 0.5μ to serve as a mask for impurity diffusion. A silicon dioxide film 4 is formed by photolithography over the gate region 31, source and drain contact regions, and part of the source and drain regions 30 and 32.
0 is selectively removed to form windows 41 and 42.

At this time, the silicon dioxide film 40 is applied not only to the field region but also to the source and drain contact regions 30, 3.
2, it is sufficient that the windows 41 and 42 where the source and drain regions are to be formed are opened, and the photoetching accuracy may be poor by the width of the second pattern. Next, in order to form the source and drayage regions 43 and 44, an impurity having a conductivity type opposite to that of the substrate, such as an n-type impurity, is introduced through the windows 41 and 42 by thermal diffusion or ion implantation. Remove with ammonium hydrofluoric acid monofluoride etching solution.

At this time, the silicon nitride film is hardly etched. Next, as a second insulating layer, a silicon dioxide film 50 which becomes a field part is formed in a high temperature and humid oxygen atmosphere of about 1100 degrees Celsius.
E to form about 0.8μ. When silicon becomes a silicon dioxide film, the volume approximately doubles, so the surface of the polycrystalline silicon films 30, 31, 32, which are the first conductor layers, and the second insulating layer 5
The height is almost the same as the surface of 0. Also, at this time, when forming the silicon dioxide film 50, the polycrystalline silicon films 30, 31,
A diffusion layer 51 in which 32 n-type impurities are diffused into the semiconductor substrate and electrically connected to the source and drain regions 43 and 44.
, 52 are formed. Next, oxidation-resistant films 27, 28, 29
By removing the polycrystalline silicon film to expose the polycrystalline silicon film and forming metal wiring layers 60, 61, 62 such as Al, the MOS transistor shown in FIG. 3f is fabricated.

Note that a photoresist film may be used instead of the fourth layer silicon dioxide film 40, and impurity diffusion into the source and drain regions may be performed by ion implantation. In this case, the silicon dioxide formation step and etching step by CVD method can be omitted, reducing the number of steps.

FIG. 4 shows a schematic structure of a MOS transistor according to the method shown in FIG. 3, which corresponds to that shown in FIG.

According to the above method, the source and drain contact portions and the gate region are determined by the second photolithography process, that is, as shown in FIG. It is now possible to achieve the minimum dimensions necessary for a contact without being affected by variations in dimensions. Further, by embedding the field oxide film 50 between the polycrystalline semiconductors, the unevenness of the surface before the metal wiring pattern is formed can be reduced to about 0.2 μm or less. As a result, it has become possible to form fine patterns even with thin metal wiring without disconnection. Furthermore, since the contact windows for the source and drain can be formed by selectively removing the silicon nitride films 27, 28, and 29, pinholes are not generated when etching a thick silicon oxide film as in the conventional method.

When opening the windows 41 and 42 for the source and drain regions, the polycrystalline silicon film 25 and the thin silicon dioxide film 23 are
, 24 are removed to expose the semiconductor substrate 21, impurity layers for the source and drain can be formed by thermal diffusion or ion implantation. The depth and concentration of this impurity layer are determined by the thickness of the polycrystalline silicon film 25 and the thin silicon dioxide film 2.
Uniform source, drain, and diffusion layers 51 and 52 can be easily formed without being affected by variations in the thicknesses of layers 3 and 24. As described above, the present invention enables higher density due to smaller contact portions, higher density and higher integration due to patterning of metal wiring on a nearly flat surface, and further increases the density and integration of gates and wiring. Parasitic capacitance is also reduced due to the reduction in area, and an IC suitable for higher speeds can be realized.

As an example of high density, if we compare the areas in FIGS. 2 and 4 when the gate area and the contact area are based on the same dimensions, the area ratio is approximately 36.3%, and it is easy to see that the present invention You can see the advantage.

[Brief explanation of drawings]

Figures 1a to 1 are explanatory diagrams of a MOS field effect transistor in a conventional semiconductor integrated circuit, Figure 2a is a schematic plan view of the same transistor, and Figures B and c are B-B' and CC lines of a. FIG.

Claims (1)

[Claims] 1. After forming a gate insulating film on one main surface of a semiconductor substrate of one conductivity type, forming a first pattern exposing the semiconductor substrate in source and drain contact areas, and forming a first pattern on the entire surface opposite to the semiconductor substrate. A step of sequentially forming a two-layer film of a polycrystalline silicon film containing conductivity-type impurities and an oxidation-resistant film, and removing the two-layer film and the gate insulating film other than the source/drain contact portion and the gate electrode portion. a step of removing and forming a second pattern; a step of forming a source/drain region between the gate electrode and the source/drain contact portion; and diffusing impurities in the polycrystalline silicon film into the semiconductor substrate; forming a field oxide film using the oxidation-resistant film having the second pattern as a mask, and then removing the oxidation-resistant film to form a wiring layer connected to the polycrystalline silicon film. A method for manufacturing a featured semiconductor device.