KR20020030338A - Manufacturing method for semiconductor device - Google Patents
Manufacturing method for semiconductor device Download PDFInfo
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- KR20020030338A KR20020030338A KR1020000060928A KR20000060928A KR20020030338A KR 20020030338 A KR20020030338 A KR 20020030338A KR 1020000060928 A KR1020000060928 A KR 1020000060928A KR 20000060928 A KR20000060928 A KR 20000060928A KR 20020030338 A KR20020030338 A KR 20020030338A
- Authority
- KR
- South Korea
- Prior art keywords
- gate
- semiconductor device
- silicide
- forming
- polycrystalline silicon
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title abstract description 23
- 238000004519 manufacturing process Methods 0.000 title description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 31
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 26
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 238000000034 method Methods 0.000 claims abstract description 16
- 239000012535 impurity Substances 0.000 claims abstract description 14
- 229910052751 metal Inorganic materials 0.000 claims abstract description 10
- 239000002184 metal Substances 0.000 claims abstract description 10
- 150000002500 ions Chemical class 0.000 claims abstract description 7
- 238000005468 ion implantation Methods 0.000 claims abstract description 5
- 229920005591 polysilicon Polymers 0.000 claims description 19
- 238000000151 deposition Methods 0.000 claims description 7
- 238000010438 heat treatment Methods 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 abstract description 7
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 230000010354 integration Effects 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
Abstract
Description
본 발명은 반도체 장치 제조방법에 관한 것으로, 특히 실리사이드가 형성되는 부분의 면적을 증가시켜 실리사이드의 저항을 최소화함으로써, 반도체 장치의 고속동작이 가능하도록 한 반도체 장치 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device which enables high speed operation of a semiconductor device by minimizing silicide resistance by increasing an area of a portion where silicide is formed.
도1a 내지 도1d는 종래 반도체 장치 제조공정 수순단면도로서, 이에 도시한 바와 같이 기판(1)의 상부에 게이트산화막과 다결정실리콘을 증착하고, 그 다결정실리콘과 게이트산화막을 패터닝하여 게이트(2)를 형성하는 단계(도1a)와; 상기 게이트(2)의 측면 기판(1) 하부에 저농도 불순물 이온을 주입하여 저농도 소스 및 드레인(3)을 형성하는 단계(도1b)와; 상기 게이트(2)의 측면에 측벽(4)을 형성한 후, 고농도 불순물 이온을 주입하여 상기 측벽(4)의 측면 기판(1) 하부에 고농도 소스 및 드레인(5)을 형성하는 단계(도1c)와; 상기 구조의 상부전면에 금속을 증착하고, 열공정을 통해 상기 게이트(2)와 고농도 소스 및 드레인(5)의 상부에 실리사이드(6)를 형성하는 단계(도1d)로 구성된다.1A to 1D show a process cross-sectional view of a conventional semiconductor device manufacturing process. As shown therein, a gate oxide film and a polycrystalline silicon are deposited on an upper portion of a substrate 1, and the polycrystalline silicon and the gate oxide film are patterned to form a gate 2. Forming step (FIG. 1A); Implanting low concentration impurity ions into the lower side substrate (1) of the gate (2) to form a low concentration source and drain (3); After the sidewall 4 is formed on the side of the gate 2, a high concentration of impurity ions are implanted to form a high concentration source and drain 5 under the side substrate 1 of the sidewall 4 (FIG. 1C). )Wow; Depositing a metal on the upper surface of the structure, and forming silicide 6 on the gate 2 and the high concentration source and drain 5 through a thermal process (FIG. 1D).
이하, 상기와 같이 구성된 종래 반도체 장치 제조방법을 좀 더 상세히 설명한다.Hereinafter, a method of manufacturing a conventional semiconductor device configured as described above will be described in more detail.
먼저, 도1a에 도시한 바와 같이 기판(1)의 상부전면에 게이트산화막을 증착하고, 그 게이트산화막의 상부전면에 다결정실리콘을 증착한다.First, as shown in FIG. 1A, a gate oxide film is deposited on the upper surface of the substrate 1, and polycrystalline silicon is deposited on the upper surface of the gate oxide film.
그 다음, 사진식각공정을 통해 상기 다결정실리콘과 그 하부의 게이트산화막을 패터닝하여 게이트(2)를 형성한다.Next, the gate 2 is formed by patterning the polysilicon and the gate oxide layer under the photolithography process.
그 다음, 도1b에 도시한 바와 같이 불순물 이온을 저농도로하여 상기 기판(1)에 주입하여 상기 게이트(2)의 측면 기판(1) 하부에 위치하는 저농도 소스 및 드레인(3)을 형성한다.Next, as shown in FIG. 1B, impurity ions are implanted at a low concentration into the substrate 1 to form a low concentration source and drain 3 positioned under the side substrate 1 of the gate 2.
그 다음, 도1c에 도시한 바와 같이 상기 구조의 상부전면에 절연막을 증착하고, 그 절연막을 건식식각하여 상기 게이트(2)의 측면에 절연막 측벽(4)을 형성한다.Next, as shown in FIG. 1C, an insulating film is deposited on the upper surface of the structure, and the insulating film is etched dry to form an insulating film sidewall 4 on the side of the gate 2.
그 다음, 상기 구조에 불순물을 고농도로 주입하여 상기 측벽(4)의 측면 기판(1) 하부에 위치하는 고농도 소스 및 드레인(5)을 형성한다.Then, impurities are injected into the structure at a high concentration to form a high concentration source and drain 5 located under the side substrate 1 of the side wall 4.
그 다음, 도1d에 도시한 바와 같이 상기 구조의 상부전면에 텅스텐 등의 금속을 증착하고, 고온으로 열처리하여 상기 금속과 실리콘인 게이트(2)와 고농도 소스 및 드레인(5)이 반응하도록 하여 실리사이드(6)를 형성하고, 그 실리사이드(6) 형성후 잔존하는 금속을 제거한다.Then, as shown in FIG. 1D, a metal such as tungsten is deposited on the upper surface of the structure and heat-treated at a high temperature so that the gate 2 and the highly concentrated source and drain 5 which are the metal and silicon react with each other. (6) is formed and metal remaining after the silicide (6) formation is removed.
이와 같이 반도체 장치를 제조하고, 상기 게이트(2)와 고농도 소스 및 드레인(5)에 배선을 실시하기 위해서는 그 배선과 상기 게이트(2) 또는 고농도 소스 및 드레인(5)을 접촉시킬때 그 접촉저항을 낮추기 위해 실리사이드(6)를 형성한다.In order to manufacture a semiconductor device and to wire the gate 2 and the highly concentrated source and drain 5 in this manner, the contact resistance when the wiring and the gate 2 or the highly concentrated source and drain 5 are brought into contact with each other. In order to lower the silicide (6) is formed.
그러나, 반도체 장치의 집적화가 심화될 수록 게이트(2)의 면적이 줄어들고, 고농도 소스 및 드레인(5)의 면적 및 깊이가 축소되어 그 상부에 형성되는 실리사이드(6)의 면적 및 두께가 줄어들게 되어 저항이 증가하게 된다.However, as the integration of semiconductor devices increases, the area of the gate 2 is reduced, the area and depth of the high concentration source and drain 5 are reduced, and the area and thickness of the silicide 6 formed thereon is reduced. Will increase.
상기한 바와 같이 종래 반도체 장치 제조방법은 반도체 장치의 집적화가 심화되어 실리사이드의 형성위치의 면적이 축소됨으로써, 실리사이드의 두께 및 면적이 감소하여 저항이 상대적으로 증가하고, 이에 따라 반도체 장치의 동작속도가 저하되는 문제점이 있었다.As described above, in the conventional semiconductor device manufacturing method, the integration of the semiconductor device is intensified and the area of the silicide formation site is reduced, so that the thickness and area of the silicide are reduced, so that the resistance is relatively increased, thereby increasing the operating speed of the semiconductor device. There was a problem of deterioration.
이와 같은 문제점을 감안한 본 발명은 반도체 장치의 집적도가 심화되는 경우에도 실리사이드의 형성면적을 일정면적 이상 확보할 수 있는 반도체 장치 제조방법을 제공함에 그 목적이 있다.In view of the above problems, an object of the present invention is to provide a method for manufacturing a semiconductor device capable of securing a predetermined area or more of silicide formation even when the degree of integration of a semiconductor device is increased.
도1a 내지 도1d는 종래 반도체 장치의 제조공정 수순단면도.1A to 1D are cross-sectional views of a manufacturing process of a conventional semiconductor device.
도2a 내지 도2d는 본 발명 반도체 장치의 제조공정 수순단면도.2A to 2D are cross-sectional views of a manufacturing process of the semiconductor device of the present invention.
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
1:기판2:분리구조1: Substrate 2: Separation Structure
3:게이트4:저농도 소스 및 드레인3: gate 4: low concentration source and drain
5:제1측벽6:다결정실리콘층5: first side wall 6: polycrystalline silicon layer
7:제2측벽8:고농도 소스 및 드레인7: second side wall 8: high concentration source and drain
9:실리사이드9: silicide
상기와 같은 목적은 기판의 상부에 게이트를 형성한 후, 불순물 이온을 주입하여 저농도 소스 및 드레인을 형성하고, 상기 게이트의 측면에 그 게이트의 측면 상부측이 노출되도록 제1측벽을 형성하는 단계와; 상기 구조의 상부전면에 다결정실리콘을 화학증착하여 상기 게이트와 저농도 소스 및 드레인 영역의 상부측에 다결정실리콘층을 형성함으로써 표면적을 증가시키는 단계와; 상기 제1측벽의 측면과 게이트의 상부에 위치하는 다결정실리콘층의 측면에 위치하는 제2측벽을 형성하고, 불순물 이온주입공정을 통해 상기 제2측벽의 하부 기판영역에 고농도 소스 및 드레인을 형성하는 단계와; 상기 구조의 상부전면에 금속을 증착하고 열처리하여 상기 다결정실리콘층에 실리사이드를 형성하는 단계로 구성함으로써 달성되는 것으로, 이와 같은 본 발명을 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.The purpose of the above is to form a gate on top of the substrate, implant the impurity ions to form a low concentration source and drain, and to form a first side wall to expose the upper side of the gate side of the gate; ; Chemically depositing polysilicon on the top surface of the structure to form a polysilicon layer on top of the gate and low concentration source and drain regions to increase surface area; Forming a second side wall positioned on the side of the first side wall and a side of the polysilicon layer positioned on the gate, and forming a high concentration source and drain in the lower substrate region of the second side wall through an impurity ion implantation process; Steps; This is achieved by forming a silicide on the polysilicon layer by depositing and heat-treating a metal on the upper surface of the structure, which will be described in detail with reference to the accompanying drawings.
도2a 내지 도2d는 본 발명 반도체 장치의 제조공정 수순단면도로서, 이에 도시한 바와 같이 기판(1)의 일부영역에 얕은 트랜치형 분리구조(2)를 형성하고, 그분리구조(2)에 의해 분리되는 기판(1)의 중앙부에 게이트(3)를 형성한 후, 불순물 이온을 주입하여 저농도 소스 및 드레인(4)을 형성하고, 상기 게이트(3)의 측면에 그 게이트(3)의 측면 상부측이 노출되도록 제1측벽(5)을 형성하는 단계(도2a)와; 상기 구조의 상부전면에 다결정실리콘을 화학증착하여 상기 게이트(3)와 기판(1) 영역에 다결정실리콘층(6)을 형성함으로써 표면적을 증가시키는 단계(도2b)와; 상기 제1측벽(5)의 측면과 게이트(3)의 상부에 위치하는 다결정실리콘층(6)의 측면에 위치하는 제2측벽(7)을 형성하고, 불순물 이온주입공정을 통해 상기 제2측벽(2)의 하부 기판(1)영역에 고농도 소스 및 드레인(8)을 형성하는 단계(도2c)와; 상기 구조의 상부전면에 금속을 증착하고 열처리하여 상기 다결정실리콘층(6)에 실리사이드(9)를 형성하는 단계(도2d)로 구성된다.2A to 2D are cross-sectional views of a manufacturing process of the semiconductor device according to the present invention. As shown in FIG. After the gate 3 is formed in the center of the substrate 1 to be separated, impurity ions are implanted to form a low concentration source and drain 4, and the upper side of the gate 3 is formed on the side of the gate 3. Forming a first side wall 5 such that the side is exposed (Fig. 2A); Chemically depositing polysilicon on the upper surface of the structure to increase the surface area by forming a polysilicon layer (6) in the region of the gate (3) and the substrate (1); The second side wall 7 is formed on the side of the first side wall 5 and the side of the polysilicon layer 6 located on the gate 3, and the second side wall is formed through an impurity ion implantation process. Forming a high concentration source and drain 8 in the region of the lower substrate 1 of (2) (FIG. 2C); And depositing a metal on the upper surface of the structure and heat treatment to form a silicide 9 in the polysilicon layer 6 (Fig. 2d).
이하, 상기와 같이 구성된 본 발명 반도체 장치 제조방법을 좀 더 상세히 설명한다.Hereinafter, the semiconductor device manufacturing method of the present invention configured as described above will be described in more detail.
먼저, 도2a에 도시한 바와 같이 기판(1)에 트랜치를 형성하고, 그 트랜치 내에 산화막을 채워 얕은 트랜치형 분리구조(2)를 형성한다.First, as shown in FIG. 2A, a trench is formed in the substrate 1, and an oxide film is filled in the trench to form a shallow trench type isolation structure 2.
그 다음, 상기 구조의 상부전면에 게이트산화막과 다결정실리콘을 순차적으로 증착하고, 사진식각공정을 통해 패터닝하여 게이트(3)를 형성한다.Next, a gate oxide film and polysilicon are sequentially deposited on the upper surface of the structure, and patterned through a photolithography process to form a gate 3.
그 다음, 불순물 이온주입공정을 통해 상기 형성한 게이트(3)의 측면 기판(1)의 하부에 저농도 소스 및 드레인(4)을 형성한다.Then, a low concentration source and drain 4 are formed in the lower portion of the side substrate 1 of the formed gate 3 through an impurity ion implantation process.
그 다음, 상기 구조의 상부전면에 절연막을 증착하고, 그 절연막을 건식식각하여 상기 게이트(3)의 측면에 제1측벽(5)을 형성한다. 이때 제1측벽(5)을 식각하는 공정은 정상적인 측벽 형성공정에 비하여 과도한 식각을 행하여, 상기 제1측벽(5)의 상부측에서 게이트(3)의 상부 측면 일부가 노출되도록 한다.Next, an insulating film is deposited on the upper surface of the structure, and the insulating film is dry etched to form a first side wall 5 on the side of the gate 3. At this time, the process of etching the first side wall 5 is excessively etched as compared to the normal side wall forming process, so that a part of the upper side of the gate 3 is exposed on the upper side of the first side wall 5.
그 다음, 도2b에 도시한 바와 같이 상기 구조에 화학증착법으로 다결정실리콘을 증착하여 다결정실리콘층(6)을 형성한다. 이때의 화학증착법은 하지막이 다결정실리콘인 영역에만 증착이되며, 이에 따라 상기 게이트(3)와 저농도 소스 및 드레인(4)의 상부측에만 형성된다.Next, as shown in FIG. 2B, polycrystalline silicon is deposited on the structure by chemical vapor deposition to form a polycrystalline silicon layer 6. At this time, the chemical vapor deposition method is deposited only in the region where the underlying film is polycrystalline silicon, and thus is formed only on the upper side of the gate 3 and the low concentration source and drain 4.
또한, 상기 게이트(3)는 상부 뿐만 아니라 측면의 일부도 노출되어 있으므로, 상기 다결정실리콘층(6)이 상부 및 측면에도 형성되어 그 게이트(3)의 상부면의 면적을 증가시키게 되고, 기판(1)의 상부측에 형성되는 다결정실리콘층(6) 또한 그 일부가 분리구조(2)의 상부일부에 위치하게 된다.In addition, since the gate 3 is exposed not only to the top but also to a part of the side surface, the polysilicon layer 6 is formed on the top and side surfaces, thereby increasing the area of the top surface of the gate 3, A part of the polysilicon layer 6 formed on the upper side of 1) is also located at an upper part of the separation structure 2.
이에 따라 이후의 실리사이드 형성시 그 실리사이드가 반도체 장치와 접하는 영역의 면적이 증가된다.This increases the area of the region where the silicide is in contact with the semiconductor device during subsequent silicide formation.
그 다음, 도2c에 도시한 바와 같이 상기 구조의 상부전면에 절연막을 증착하고, 그 절연막을 건식식각하여 상기 제1측벽(5)과 게이트(3) 상에 위치하는 다결정실리콘층(6)의 측면에 제2측벽(7)을 형성한다.Then, as shown in FIG. 2C, an insulating film is deposited on the upper surface of the structure, and the insulating film is dry etched to form the polysilicon layer 6 positioned on the first side wall 5 and the gate 3. The second side wall 7 is formed on the side.
그 다음, 분순물 이온을 고농도로 주입하여 상기 제2측벽(7)의 측면 기판(1)의 하부에 고농도 소스 및 드레인(8)을 형성한다.Then, the impurities are implanted at a high concentration to form a high concentration source and drain 8 under the side substrate 1 of the second side wall 7.
그 다음, 도2d에 도시한 바와 같이 상기 구조의 상부전면에 금속을 증착하고, 고온으로 열처리하여 상기 금속과 상기 형성한 다결정실리콘층(6)이 반응하도록 하여 실리사이드(9)를 형성한다.Next, as shown in FIG. 2D, a metal is deposited on the upper surface of the structure and heat-treated at a high temperature to allow the metal and the polysilicon layer 6 to be formed to form a silicide 9.
상기한 바와 같이 본 발명 반도체 장치 제조방법은 실리사이드가 형성될 영역의 상부에 그 실리사이드의 면적을 증가시킬 수 있는 다결정실리콘층을 미리 형성하고, 실리사이드를 형성하여 반도체 장치의 집적도가 심화되는 경우에도 일정한 면적 이상의 실리사이드 형성면적을 확보함으로써, 저항의 증가를 방지하여 반도체 장치의 동작속도가 저하되는 것을 방지하는 효과가 있다.As described above, the semiconductor device manufacturing method of the present invention is formed even if the polysilicon layer capable of increasing the area of the silicide is formed in advance on the region where the silicide is to be formed, and the silicide is formed to increase the degree of integration of the semiconductor device. By securing a silicide formation area of more than an area, there is an effect of preventing the increase of the resistance and reducing the operation speed of the semiconductor device.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20040025949A (en) * | 2002-09-17 | 2004-03-27 | 아남반도체 주식회사 | Method for forming gate of semiconductor element |
| KR100481551B1 (en) * | 2002-09-23 | 2005-04-07 | 동부아남반도체 주식회사 | Method for forming sidewall spacers disposed around a gate in fabricating semiconductor element |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20040025949A (en) * | 2002-09-17 | 2004-03-27 | 아남반도체 주식회사 | Method for forming gate of semiconductor element |
| KR100481551B1 (en) * | 2002-09-23 | 2005-04-07 | 동부아남반도체 주식회사 | Method for forming sidewall spacers disposed around a gate in fabricating semiconductor element |
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