JPS63275181A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS63275181A JPS63275181A JP11181787A JP11181787A JPS63275181A JP S63275181 A JPS63275181 A JP S63275181A JP 11181787 A JP11181787 A JP 11181787A JP 11181787 A JP11181787 A JP 11181787A JP S63275181 A JPS63275181 A JP S63275181A
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- high melting
- gate
- film
- self
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 20
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 238000002844 melting Methods 0.000 claims abstract description 17
- 230000008018 melting Effects 0.000 claims abstract description 16
- 238000009792 diffusion process Methods 0.000 claims abstract description 15
- 229910052751 metal Inorganic materials 0.000 claims abstract description 15
- 239000002184 metal Substances 0.000 claims abstract description 15
- 238000000034 method Methods 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 12
- 238000001947 vapour-phase growth Methods 0.000 claims description 3
- 239000012535 impurity Substances 0.000 abstract description 7
- 238000001020 plasma etching Methods 0.000 abstract description 3
- 229910052785 arsenic Inorganic materials 0.000 abstract description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 abstract description 2
- 238000005530 etching Methods 0.000 abstract description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052721 tungsten Inorganic materials 0.000 abstract description 2
- 239000010937 tungsten Substances 0.000 abstract description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 229910052698 phosphorus Inorganic materials 0.000 abstract 1
- 239000011574 phosphorus Substances 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 28
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 230000005684 electric field Effects 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000002784 hot electron Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法に関し、特に、ゲート電
極にシリコンを用いた絶縁ゲート型電界効果トランジス
タの製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing an insulated gate field effect transistor using silicon for the gate electrode.
近年、半導体集積回路の高集積化につれ、半導体装置内
で使用される絶縁ゲート型電界効果トランジスタ（以下
、Ｉ ＧＦＥＴと記す）のホットエレクトロンによって
生する特性劣化が信頼性上極めて重大な問題となってい
る。この原因は、微細化により素子内部の電界強度か増
大したことによるものである。In recent years, as semiconductor integrated circuits have become more highly integrated, the deterioration of characteristics caused by hot electrons in insulated gate field effect transistors (hereinafter referred to as IGFETs) used in semiconductor devices has become an extremely serious problem in terms of reliability. ing. The reason for this is that the electric field strength inside the element increases due to miniaturization.
こうした問題に対処する一方法として、ドレイン拡散層
近傍における電界強度を緩和することが考えられる。こ
のためＦＥＴのソース・トレイン拡散層のチャネル側の
端部に低濃度拡散層を配置した各種のトランジスタが提
案されている。One possible way to deal with these problems is to reduce the electric field strength near the drain diffusion layer. For this reason, various transistors have been proposed in which a low concentration diffusion layer is disposed at the channel side end of the source train diffusion layer of the FET.
例えば、第４図（ｆ）に示すようなＬＤＤ （Ｌｉｇｈ
ｔｌｙ口ｏｐｅｄ Ｄｒａｉｎ）構造を有するＦＥＴは
、ゲート電極１４’Ａに自己整合的にｎ一層１６及び１
７を形成した後、ケート電極１４Ａの側面に例えば、酸
化膜によるサイドウオール２４Ａを形成し、この後、ｎ
＋層１９と２０をゲート電極１４Ａ及びサイドウオール
２４Ａに対して自己整合的に形成するものである。これ
により、ソース・ドレイン拡散層の端部に低濃度の拡散
層が配置され、ドレイン端での電界強度の緩和をはかる
ことができる。For example, an LDD (Light
The FET having the (opened drain) structure has two layers 16 and 1 in self-alignment with the gate electrode 14'A.
7, a sidewall 24A made of, for example, an oxide film is formed on the side surface of the gate electrode 14A.
The + layers 19 and 20 are formed in a self-aligned manner with respect to the gate electrode 14A and the sidewalls 24A. As a result, a low concentration diffusion layer is placed at the end of the source/drain diffusion layer, and the electric field strength at the drain end can be relaxed.
以下このような耐ホツトエレクトロン構造を有するＩＧ
ＦＥＴの製造方法を第４図（ａ）〜（ｆ）を用いて説明
する。The following is an IG having such a hot electron resistant structure.
A method for manufacturing an FET will be explained using FIGS. 4(a) to 4(f).
まず、第４図（ａ）に示すように、ｐ形シリコン基板１
１上に、素子分離のための厚い二酸化ケイ素（Ｓｉ０２
）膜１３を、通常の選択酸化法により形成し、次いで、
ゲート酸化膜１２を介して、多結晶シリコン膜１４を気
相成長法により堆積する。さらに、通常のフォトリソグ
ラフィにより、ゲート電極となる領域をおおうレジスト
・パターン１５を形成する。First, as shown in FIG. 4(a), a p-type silicon substrate 1
1, a thick silicon dioxide (Si02
) The film 13 is formed by a normal selective oxidation method, and then
A polycrystalline silicon film 14 is deposited via the gate oxide film 12 by vapor phase growth. Furthermore, a resist pattern 15 is formed by ordinary photolithography to cover the region that will become the gate electrode.
次に第４図（ｂ）に示すように、このレジスト・パター
ン１５をマスクに不要な領域の多結晶シリコンを選択的
にエツチングし、ゲート電極１４Ａを形成する。Next, as shown in FIG. 4(b), using this resist pattern 15 as a mask, unnecessary areas of polycrystalline silicon are selectively etched to form a gate electrode 14A.
次に、第４図（ｃ）に示すように、形成されたゲート電
極１４Ａに対し、自己整合的にｎ形不純物をイオン注入
し、ｎ一層１６及び１７を形成する。Next, as shown in FIG. 4(c), n-type impurity ions are implanted into the formed gate electrode 14A in a self-aligned manner to form n-layers 16 and 17.
次に、第４図（ｄ）に示すように、全面に気相成長法に
より酸化膜２４を形成する。Next, as shown in FIG. 4(d), an oxide film 24 is formed on the entire surface by vapor phase growth.
次に第４図（ｅ）に示すように、反応性イオンエツチン
グにより、酸化膜２４を異方性エツチングし、ゲート電
極１４Ａの側面に、酸化膜からなるサイドウオール２４
Ａを形成する。続いて、このゲート領域に対して、自己
整合的にｎ＋層１９．２０をイオン注入により形成する
。Next, as shown in FIG. 4(e), the oxide film 24 is anisotropically etched by reactive ion etching to form a side wall 24 made of an oxide film on the side surface of the gate electrode 14A.
Form A. Subsequently, n+ layers 19 and 20 are formed in the gate region by ion implantation in a self-aligned manner.
次に、第４図（ｆ）に示すように、通常の工程により、
ＰＳＧ膜２１及びアルミ配線２２を形成しＩＧＦＥＴを
完成させる。Next, as shown in FIG. 4(f), through the normal process,
A PSG film 21 and aluminum wiring 22 are formed to complete the IGFET.
上述した従来のＩＧＦＥＴの製造方法では、ゲート電極
の側面にサイドウオールを形成する方法として、酸化膜
のイオンエツチングを行なうか、この工程は、基板に対
して著しいプラズマダメージを与え、これか接合リーク
等を引起こす。このため特性の再現性が悪くなり、半導
体装置の製造歩留り及び信頼性が低下するという問題点
がある。In the conventional IGFET manufacturing method described above, ion etching of the oxide film is performed to form sidewalls on the sides of the gate electrode, or this process causes significant plasma damage to the substrate and may cause junction leakage. etc. Therefore, there is a problem in that the reproducibility of the characteristics deteriorates, and the manufacturing yield and reliability of the semiconductor device decreases.
本発明の目的は、基板へのダメージをなくし、製造歩留
り及び信頼性の向上した半導体装置の製造方法を提供す
ることにある。An object of the present invention is to provide a method for manufacturing a semiconductor device that eliminates damage to a substrate and improves manufacturing yield and reliability.
本発明の半導体装置の製造方法は、一導電形半導体基板
上にケート酸化膜を介して多結晶シリコンからなるゲー
ト電極を形成し、該ゲート電極に自己整合的に低濃度の
逆導電形拡散層を形成するＬＤＤ構造のソース・トレイ
ンを有する半導体装置の製造方法であって、前記ゲート
電極の少くとも側壁部に高融点金属層を形成したのち該
高融点金属層を含むケート電極に自己整合的に高濃度の
逆導電形拡散層を形成するものである。The method for manufacturing a semiconductor device of the present invention includes forming a gate electrode made of polycrystalline silicon on a semiconductor substrate of one conductivity type via a gate oxide film, and forming a low concentration diffusion layer of the opposite conductivity type on the gate electrode in a self-aligned manner. A method for manufacturing a semiconductor device having a source train having an LDD structure, wherein a high melting point metal layer is formed on at least a side wall portion of the gate electrode, and then a gate electrode including the high melting point metal layer is formed in a self-aligned manner. In this method, a highly concentrated reverse conductivity type diffusion layer is formed.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図（ａ）〜（ｇ）は本発明の第１の実施例を説明す
るための工程順に示した半導体チップの断面図である。FIGS. 1A to 1G are cross-sectional views of a semiconductor chip shown in order of steps for explaining a first embodiment of the present invention.
まず、第１図（ａ）に示すように、ｐ形シリコン基板１
１上に、素子分離のための厚いＳｉＯ２膜１３を選択酸
化法により形成し、次いで、ゲート酸化膜１２を介して
、多結晶シリコン膜１４を堆積する。次いでフォトレジ
スト膜を形成したのちパターニングし、レジストパター
ン１５を形成する。First, as shown in FIG. 1(a), a p-type silicon substrate 1
1, a thick SiO2 film 13 for element isolation is formed by selective oxidation, and then a polycrystalline silicon film 14 is deposited via the gate oxide film 12. Next, a photoresist film is formed and patterned to form a resist pattern 15.
次に第１図（ｂ）に示すように、レジスト・パターン１
５をマスクに、多結晶シリコン膜１４を反応性イオンエ
ツチングにより選択的にエツチングし、ゲート電極１４
Ａを形成する。この際、ゲート電極以外の基板表面上に
はゲート酸化膜１２が残存するようにエツチング条件を
設定する。Next, as shown in FIG. 1(b), resist pattern 1 is formed.
5 as a mask, the polycrystalline silicon film 14 is selectively etched by reactive ion etching to form the gate electrode 14.
Form A. At this time, etching conditions are set so that the gate oxide film 12 remains on the surface of the substrate other than the gate electrode.
次に第１図（Ｃ）に示すように、形成されたゲ−ト電極
１４Ａに対し、自己整合的にリン等のｎ形不純物をイオ
ン注入し、ｎ一層１６及び１７を形成する。Next, as shown in FIG. 1C, n-type impurities such as phosphorus are ion-implanted into the formed gate electrode 14A in a self-aligned manner to form n-layers 16 and 17.
次に第１図（ｄ）に示すように、少なくともゲート電極
１４Ａの側面を含む多結晶シリコン表面上のみに気相成
長法により選択的にタングステン等の高融点金属膜１８
を１０００人ないし２０００人成長させる。この場合、
高融点金属はシリコン上には成長するが、酸化股上には
成長しない。Next, as shown in FIG. 1(d), a high melting point metal film 18 such as tungsten is selectively deposited only on the polycrystalline silicon surface including at least the side surfaces of the gate electrode 14A by vapor phase growth.
to grow by 1,000 to 2,000 people. in this case,
Refractory metals grow on silicon, but not on oxidized tops.
次に第１図（ｅ）に示すように、成長した高融点金属膜
１８を含むゲート領域に対して自己整合的にヒ素等のｎ
形不純物をイオン注入しｎ＋層１９及び２０を形成する
。Next, as shown in FIG. 1(e), arsenic or other nitrogen is added in a self-aligned manner to the gate region including the grown refractory metal film 18.
N+ layers 19 and 20 are formed by ion implantation of type impurities.
以下第１図（ｆ）に示すように、注入不純物の活性化等
のための熱処理を行ったのち、基板表面上に、眉間絶縁
膜としてのＰＳＧ膜２１を形成する。As shown in FIG. 1(f), after heat treatment is performed to activate the implanted impurities, a PSG film 21 as a glabellar insulating film is formed on the surface of the substrate.
次で、通常の工程によりアルミ配線２２を形成し、第１
図（ｇ）に示ずＬＤＤｌ’ｌ造を有するＩＧＦＥＴを完
成させる。Next, aluminum wiring 22 is formed by a normal process, and the first
An IGFET having an LDD structure as shown in Figure (g) is completed.
なお、本箱１の実施例において、多結晶シリコン膜のパ
ターニング後、ｎ一層、ｎ＋層の順でソース・ドレイン
拡散層を形成したが、第３図（ａ）〜（Ｃ）に示すよう
に先にｎ＋層を形成し、次いでｎ一層を形成してもよい
。すなわちゲート電極１４Ａを形成後、第３図（ａ）に
示すように、高融点金属１８をゲート電極１４Ａ上に選
択成長し、このゲート領域に対して、自己整合的に、第
３図（ｂ）に示すようにｎ＋層１つと２０を形成する。In the example in Bookcase 1, after patterning the polycrystalline silicon film, the source/drain diffusion layers were formed in the order of the n layer and the n+ layer, but as shown in FIGS. 3(a) to (C), The n+ layer may be formed first, and then the n layer may be formed. That is, after forming the gate electrode 14A, the high melting point metal 18 is selectively grown on the gate electrode 14A as shown in FIG. ), one n+ layer and 20 are formed.
この後、高融点金属膜１８を除去し、ゲート電極１４Ａ
に対して、自己整合的にｎ一層１６と１７を形成し、第
３図（ｃ）を得る。その後は、第１図（ｆ）以下の工程
を経て、ＩＧＦＥＴを完成させる。After that, the high melting point metal film 18 is removed and the gate electrode 14A is removed.
3(c) is obtained by forming n-layers 16 and 17 in a self-aligned manner. Thereafter, the IGFET is completed through the steps shown in FIG. 1(f) and subsequent steps.
第２図（ａ）〜（ｄ）は、本発明の第２の実施例を説明
するための工程順に示した半導体チップの断面図である
。FIGS. 2(a) to 2(d) are cross-sectional views of a semiconductor chip shown in order of steps for explaining a second embodiment of the present invention.
まず、第２図（ａ）に示すようにｐ形シリコン基板１１
上に、ゲート酸化膜１２を介して多結晶シリコン膜１４
を成長した後、さらに酸化膜２３を２００人ないし５０
０人形成する。その後フォトリソグラフィによりレジス
ト・パターン１５を形成する。First, as shown in FIG. 2(a), a p-type silicon substrate 11
On top, a polycrystalline silicon film 14 is formed via a gate oxide film 12.
After growing the oxide film 23, the oxide film 23 is further grown by 200 to 50 layers.
Form 0 people. Thereafter, a resist pattern 15 is formed by photolithography.
次に第２図（ｂ）に示すように、レジスト・パターン１
５をマスクとして、酸化膜２３及び多結晶シリコン膜１
４を順次エツチングしゲート電極１４Ａを形成する。こ
の際、ゲート電極１４Ａ以外の領域上に在する５ｉ０２
膜１２が残存するようにエツチングする。Next, as shown in FIG. 2(b), resist pattern 1 is formed.
5 as a mask, oxide film 23 and polycrystalline silicon film 1
4 is sequentially etched to form a gate electrode 14A. At this time, 5i02 located on the area other than the gate electrode 14A
Etching is performed so that the film 12 remains.
次に第２図（Ｃ）に示すようにレジスト・パターン１５
を除去し形成されたゲート電極１４Ａの側面に露出した
シリコン表面のみに、タングステン等の高融点金属膜１
８を選択成長させる。そして成長した高融点金属膜１８
を含むゲート領域に対して自己整合的にｎ形不純物をイ
オン注入しｎ＋層１９と２０を形成する。Next, as shown in FIG. 2(C), a resist pattern 15 is formed.
A high melting point metal film 1 such as tungsten is applied only to the silicon surface exposed on the side surface of the gate electrode 14A formed by removing the
Select and grow 8. And the grown high melting point metal film 18
N+ layers 19 and 20 are formed by ion-implanting n-type impurities in a self-aligned manner into the gate region including the gate region.
次に第２図（ｄ）に示すようにゲート電極１４Ａの側面
に成長した高融点金属膜１８を除去したのちｎ形不純物
をイオン注入し、ゲート電極１４Ａに対して自己整合的
にｎ一層１６及び１７を形＝９−
成する。以下は、通常の工程によりＩＧＦＥＴを完成さ
せる。Next, as shown in FIG. 2(d), after removing the high melting point metal film 18 grown on the side surface of the gate electrode 14A, n-type impurities are ion-implanted, and the n-layer 16 is self-aligned to the gate electrode 14A. and form 17=9-. The IGFET is then completed using the usual steps.
この第２の実施例においては最終的に高融点金属膜１８
を除去するため、第１図に示した第１の実施例に比べ、
ゲート電極近傍ので段差がゆるやかになるという利点か
ある。In this second embodiment, the high melting point metal film 18 is finally
In order to eliminate this, compared to the first embodiment shown in FIG.
This has the advantage that the difference in level becomes gentle near the gate electrode.
以上説明したように本発明はＩＧＦＥＴのソース・ドレ
イン拡散層を高濃度の拡散層とチャネル領域との間に低
濃度の拡散層を配したＬＤＤ構造とする際、低濃度の拡
散層を形成するためのサイドウオールを、高融点金属の
選択成長により形成するため、従来のように酸化膜のエ
ッチパックによりサイドウオールを形成する方法で問題
となる基板に対するプラズマ・ダメージが全くないとい
う効果がある。従って半導体装置の製造歩留り及び信頼
性は向上する。As explained above, in the present invention, when the source/drain diffusion layer of an IGFET has an LDD structure in which a low concentration diffusion layer is arranged between a high concentration diffusion layer and a channel region, the low concentration diffusion layer is formed. Since the sidewalls are formed by selective growth of a high-melting point metal, there is no plasma damage to the substrate, which is a problem with the conventional method of forming sidewalls by etch-packing an oxide film. Therefore, the manufacturing yield and reliability of semiconductor devices are improved.
第１図（ａ）〜（ｇ）及び第２図（ａ）〜（−１０＝
ｄ）は本発明の第１及び第２の実施例を説明するための
工程順に示した半導体チップの断面図、第３図（ａ）〜
（Ｃ）は第１の実施例の他の工程を説明するための断面
図、第４図（ａ）〜（ｆ）は従来の半導体装置の製造方
法を示す半導体チップの断面図である。
１１・・・ｐ形半導体基板、１２・・・ゲート酸化膜、
１３・・・Ｓ ｉ ０２膜、１４・・・多結晶シリコン
膜、１４Ａ・・・ゲート電極、１５・・・レジストパタ
ーン、１６．１７・・・ｎ一層、１８・・・高融点金属
膜、１９゜２０・・・ｎ＋層、２１・・・ＰＳＧ膜、２
２・・・アルミ配線、２３．２４・・・酸化膜、２４Ａ
・・・サイドウオール。
□□−−
１ｌ−
（５４シFIGS. 1(a) to (g) and FIGS. 2(a) to (-10=d) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining the first and second embodiments of the present invention. , Figure 3(a)~
(C) is a cross-sectional view for explaining another process of the first embodiment, and FIGS. 4(a) to (f) are cross-sectional views of a semiconductor chip showing a conventional method of manufacturing a semiconductor device. 11...p-type semiconductor substrate, 12... gate oxide film,
13...S i 02 film, 14... Polycrystalline silicon film, 14A... Gate electrode, 15... Resist pattern, 16.17... N single layer, 18... High melting point metal film, 19°20...n+ layer, 21...PSG film, 2
2...Aluminum wiring, 23.24...Oxide film, 24A
...side wall. □□-- 1l- (54shi
Claims (2)
結晶シリコンからなるゲート電極を形成し、該ゲート電
極に自己整合的に低濃度の逆導電形拡散層を形成するＬ
ＤＤ構造のソース・ドレインを有する半導体装置の製造
方法であって、前記ゲート電極の少くとも側壁部に高融
点金属層を形成したのち該高融点金属層を含むゲート電
極に自己整合的に高濃度の逆導電形拡散層を形成するこ
とを特徴とする半導体装置の製造方法。(1) A gate electrode made of polycrystalline silicon is formed on a semiconductor substrate of one conductivity type via a gate oxide film, and a low concentration diffusion layer of the opposite conductivity type is formed on the gate electrode in a self-aligned manner.
A method for manufacturing a semiconductor device having a DD structure source/drain, wherein a high melting point metal layer is formed on at least the side wall portion of the gate electrode, and then a high concentration metal layer is formed in a self-aligned manner on the gate electrode including the high melting point metal layer. 1. A method of manufacturing a semiconductor device, comprising forming an opposite conductivity type diffusion layer.
の範囲第１項記載の半導体装置の製造方法。(2) A method for manufacturing a semiconductor device according to claim 1, wherein the high melting point metal is formed by a vapor phase growth method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11181787A JPS63275181A (en) | 1987-05-07 | 1987-05-07 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11181787A JPS63275181A (en) | 1987-05-07 | 1987-05-07 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63275181A true JPS63275181A (en) | 1988-11-11 |
Family
ID=14570903
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11181787A Pending JPS63275181A (en) | 1987-05-07 | 1987-05-07 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63275181A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02177442A (en) * | 1988-12-28 | 1990-07-10 | Ricoh Co Ltd | Manufacture of semiconductor device |
| WO1991002379A1 (en) * | 1989-07-27 | 1991-02-21 | Seiko Instruments Inc. | Misfet and method of producing the same |
| US7009262B2 (en) | 2002-09-27 | 2006-03-07 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
| US7569436B2 (en) | 2002-09-27 | 2009-08-04 | Semiconductor Energy Laboratory Co., Ltd. | Manufacturing method of semiconductor device |
-
1987
- 1987-05-07 JP JP11181787A patent/JPS63275181A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02177442A (en) * | 1988-12-28 | 1990-07-10 | Ricoh Co Ltd | Manufacture of semiconductor device |
| WO1991002379A1 (en) * | 1989-07-27 | 1991-02-21 | Seiko Instruments Inc. | Misfet and method of producing the same |
| US7009262B2 (en) | 2002-09-27 | 2006-03-07 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
| US7422933B2 (en) | 2002-09-27 | 2008-09-09 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing semiconductor device |
| US7569436B2 (en) | 2002-09-27 | 2009-08-04 | Semiconductor Energy Laboratory Co., Ltd. | Manufacturing method of semiconductor device |
| US7648863B2 (en) | 2002-09-27 | 2010-01-19 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4786609A (en) | Method of fabricating field-effect transistor utilizing improved gate sidewall spacers | |
| JPH05206451A (en) | Mosfet and its manufacture | |
| US5396099A (en) | MOS type semiconductor device having a high ON current/OFF current ratio | |
| US5115296A (en) | Preferential oxidization self-aligned contact technology | |
| JPS63257231A (en) | Manufacture of semiconductor device | |
| JPS63275181A (en) | Manufacture of semiconductor device | |
| US6221745B1 (en) | High selectivity mask oxide etching to suppress silicon pits | |
| JPS6197967A (en) | Semiconductor device and manufacture thereof | |
| JPH06204173A (en) | Manufacture of semiconductor device | |
| KR0170436B1 (en) | Method of manufacturing mosfet | |
| JPH07297275A (en) | Manufacture of semiconductor device | |
| JPH0127589B2 (en) | ||
| JPS6138858B2 (en) | ||
| KR100347149B1 (en) | Manufacturing method for semiconductor device | |
| JPH0227737A (en) | Manufacture of semiconductor device | |
| JP2623711B2 (en) | Semiconductor device | |
| JPS6156448A (en) | Manufacture of complementary semiconductor device | |
| JPS6154661A (en) | Manufacture of semiconductor device | |
| KR940000986B1 (en) | Manufacturing method of stack type cmos | |
| JP3373839B2 (en) | Semiconductor device | |
| JPH02211633A (en) | Semiconductor device and manufacture thereof | |
| JPH1126756A (en) | Manufacture of semiconductor device | |
| JPS61251164A (en) | Manufacture of bi-mis integrated circuit | |
| JPS59105367A (en) | Manufacture of metal oxide semiconductor type transistor | |
| JPH025411A (en) | Manufacture of semiconductor device |