JP2509708B2 - SOI type semiconductor device and manufacturing method thereof - Google Patents
SOI type semiconductor device and manufacturing method thereofInfo
- Publication number
- JP2509708B2 JP2509708B2 JP1230534A JP23053489A JP2509708B2 JP 2509708 B2 JP2509708 B2 JP 2509708B2 JP 1230534 A JP1230534 A JP 1230534A JP 23053489 A JP23053489 A JP 23053489A JP 2509708 B2 JP2509708 B2 JP 2509708B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- recess
- insulating film
- semiconductor
- impurity region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 50
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000012535 impurity Substances 0.000 claims description 33
- 239000004020 conductor Substances 0.000 claims description 19
- 239000000758 substrate Substances 0.000 claims description 16
- 239000011229 interlayer Substances 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 8
- 230000000149 penetrating effect Effects 0.000 claims description 5
- 239000010408 film Substances 0.000 description 101
- 239000010410 layer Substances 0.000 description 26
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 25
- 238000009792 diffusion process Methods 0.000 description 23
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- 230000005669 field effect Effects 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229910017855 NH 4 F Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
- H01L21/743—Making of internal connections, substrate contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/78654—Monocrystalline silicon transistors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Description
【発明の詳細な説明】 ［発明の目的］ （産業上の利用分野） 本発明はSOI（silicon on insulator）型半導体装
置及びその製造方法に関するもので、特に超高速、超高
集積のMOS集積回路に使用するものである。The present invention relates to an SOI (silicon on insulator) type semiconductor device and a method of manufacturing the same, and in particular, an ultrahigh-speed and ultrahigh-integrated MOS integrated circuit. Is used for.
（従来の技術） 従来、SOI型MOSトランジスタは、第４図又は第５図に
示すような断面構造をしている。ここで、１はシリコン
基板、２はSiO2膜、３は単結晶シリコン膜、４はn+領
域、５はゲート絶縁膜、６は多結晶シリコンゲート、７
は空乏層である。(Prior Art) Conventionally, an SOI type MOS transistor has a sectional structure as shown in FIG. 4 or FIG. Here, 1 is a silicon substrate, 2 is a SiO 2 film, 3 is a single crystal silicon film, 4 is an n + region, 5 is a gate insulating film, 6 is a polycrystalline silicon gate, 7
Is the depletion layer.
第４図は単結晶シリコン膜３が厚い場合（チャネル下
に空乏化しない領域が残るような場合）のMOSトランジ
スタを示すものである。この場合は、ゲート電界がゲー
ト酸化膜５と空乏層７の両方に加わるため、チャネル領
域の電界強度が大きくなる。このため、このMOSトラン
ジスタは、単結晶シリコン膜３がシリコン基板（バルク
シリコン）１より結晶性が悪い分だけ電子の電界効果移
動度が下がり、又電流駆動能力が低下するという欠点が
ある。FIG. 4 shows a MOS transistor when the single crystal silicon film 3 is thick (when there is a region not depleted below the channel). In this case, since the gate electric field is applied to both the gate oxide film 5 and the depletion layer 7, the electric field strength in the channel region becomes large. Therefore, this MOS transistor has the drawback that the field effect mobility of electrons is reduced and the current drive capability is also reduced due to the fact that the single crystal silicon film 3 has poorer crystallinity than the silicon substrate (bulk silicon) 1.
第５図は単結晶シリコン膜３が500Å程度と薄い場合
（チャネル下が全て空乏化するような場合）のMOSトラ
ンジスタを示すものである。この場合は、単結晶シリコ
ン膜３に形成される空乏層が、下地のSiO2膜２まで突き
抜けるために、SiO2膜２に印加される電圧が大きくな
る。このため、ゲート絶縁膜５に印加される電圧が小さ
くなり、電子の電界効果移動度が900〜1000cm2/V・Ｓと
バルクMOSトランジスタの1.5倍以上に向上する利点があ
る。FIG. 5 shows a MOS transistor in the case where the single crystal silicon film 3 is as thin as about 500 Å (when the whole under the channel is depleted). In this case, a depletion layer formed in the single crystal silicon film 3, in order to penetrate to the SiO 2 film 2 of the base, the voltage applied to the SiO 2 film 2 is increased. Therefore, the voltage applied to the gate insulating film 5 is reduced, and the field effect mobility of electrons is 900 to 1000 cm 2 / V · S, which is an advantage of 1.5 times or more that of the bulk MOS transistor.
ところで、単結晶シリコン膜３の薄いMOSトランジス
タでは、この単結晶シリコン膜３をさらに薄くすること
により、電子の電界効果移動度をバルクを走る電子移動
度（1350cm2/V・Ｓ）に近ずけるとが可能である。な
お、これについては、吉見 信等“薄膜SOIを用いた高
性能SOI・MOSFETの特性解析",電子情報通信学会技術研
究報告（シリコン材料・デバイス）,SDM87−154,P.13〜
P.18,1988年１月に詳しく記載されている。By the way, in a MOS transistor having a thin single crystal silicon film 3, by further thinning the single crystal silicon film 3, the field effect mobility of electrons is kept close to the electron mobility (1350 cm 2 / V · S) running in the bulk. It is possible to kick. Regarding this, Shin Yoshimi et al. “Characteristic analysis of high performance SOI / MOSFET using thin film SOI”, IEICE Technical Report (Silicon Materials / Devices), SDM87-154, P.13-
P.18, January 1988.
しかしながら、単結晶シリコン膜３が薄くなると、第
６図に示すように、RIE（reactive ion etching）等
の異方性エッチングを用いて、ドレイン又はソースとし
てのn+領域４に達するコンタクトホールを層間絶縁膜８
に開ける場合、n+領域４を突き抜けてSiO2膜２までエッ
チングしてしまう危険性が非常に高くなる。こうなる
と、Al電極９とn+領域４とのコンタクト部分の面積は、
n+領域４を突き抜けない場合に比べて、円柱状のコンタ
クトホールの半径をｒ、単結晶シリコン膜３の膜厚をｄ
とすると、πr2−２πrd＝πr2（１−2d/r）だけ減少す
る。但し、ｒ＞2dとする。即ち、単結晶シリコン膜３の
膜厚ｄが薄くなればなるほど、Al電極９とn+領域４との
コンタクト部分の面積が小さくなり、そのコンタクト抵
抗が大きくなるという欠点がある。なお、RIE等に変え
てNH4F等によるウェットエッチングを用いる場合は、コ
ンタクト整合の余裕を十分に取らなければならず、高集
積化に著しく不利となる。However, when the single crystal silicon film 3 becomes thin, as shown in FIG. 6, a contact hole reaching the n + region 4 as a drain or a source is formed by interlayer etching using anisotropic etching such as RIE (reactive ion etching). Insulating film 8
In the case of opening it at a very high level, there is a very high risk of penetrating the n + region 4 and etching the SiO 2 film 2. Then, the area of the contact portion between the Al electrode 9 and the n + region 4 is
The radius of the cylindrical contact hole is r, and the thickness of the single crystal silicon film 3 is d, as compared with the case where the n + region 4 is not penetrated.
Then, πr 2 −2πrd = πr 2 (1−2d / r) is decreased. However, r> 2d. That is, as the film thickness d of the single crystal silicon film 3 becomes thinner, the area of the contact portion between the Al electrode 9 and the n + region 4 becomes smaller and the contact resistance becomes larger. If wet etching using NH 4 F or the like is used instead of RIE or the like, a sufficient contact matching margin must be taken, which is extremely disadvantageous for high integration.
また、単結晶シリコン膜３が薄いと、そこに形成する
拡散層も必然的に薄くなるため、拡散層配線の抵抗も大
きくなる。このため、単結晶シリコン膜３を薄くするこ
とにより電子の電界効果移動度を大きくし電流駆動能力
を上げても、集積回路としての高速動作は期待できなく
なる。よって、拡散層配線を使用することが不可能にな
り、Al配線やゲート多結晶シリコンのみで集積回路を構
成しなければならず、設計の自由度が制限されパターン
が大きくなるという欠点がある。Further, if the single crystal silicon film 3 is thin, the diffusion layer formed therein is inevitably thin, and the resistance of the diffusion layer wiring also increases. Therefore, even if the single-crystal silicon film 3 is thinned to increase the field effect mobility of electrons and increase the current driving capability, high-speed operation as an integrated circuit cannot be expected. Therefore, it becomes impossible to use the diffusion layer wiring, and the integrated circuit must be configured only by the Al wiring and the gate polycrystalline silicon, which has a drawback that the degree of freedom in design is limited and the pattern becomes large.
（発明が解決しようとする課題） このように、従来は、単結晶シリコン膜が薄くなり、
コンタクトホールが前記単結晶シリコン膜に形成される
n+領域を突き抜けるため、Al電極と前記n+領域とのコン
タクト抵抗が大きくなるという欠点があった。また、前
記単結晶シリコン膜に形成される拡散層配線の配線抵抗
の増大により、拡散層配線が不可能になり、設計の自由
度が制限されパターンが大きくなるという欠点があっ
た。(Problems to be solved by the invention) As described above, conventionally, the single crystal silicon film becomes thin,
Contact holes are formed in the single crystal silicon film
Since it penetrates through the n + region, there is a drawback that the contact resistance between the Al electrode and the n + region increases. Further, there is a drawback that diffusion layer wiring becomes impossible due to an increase in wiring resistance of the diffusion layer wiring formed in the single crystal silicon film, the degree of freedom in design is limited, and the pattern becomes large.
よって、本発明は、薄い単結晶シリコン膜を有するSO
I型MOS集積回路であっても、コンタクト抵抗を大きくす
ることなく、かつ、拡散層配線の配線抵抗を大きくする
ことなく製作できるような高速、高性能、高品質のSOI
型半導体装置を提供することを目的とする。Thus, the present invention provides SO with a thin single crystal silicon film.
High-speed, high-performance, high-quality SOI that can be manufactured without increasing contact resistance and wiring resistance of diffusion layer wiring even for I-type MOS integrated circuits
An object of the present invention is to provide a semiconductor device.
［発明の構成］ （課題を解決するための手段） 上記目的を達成するために、本発明のSOI型MOS半導体
装置は、半導体基板と、この半導体基板上に形成される
絶縁膜と、この絶縁膜に形成される拡散層配線と、前記
拡散層配線及び絶縁膜上に形成される半導体膜と、この
半導体膜に形成される半導体素子とを有している。[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, an SOI-type MOS semiconductor device of the present invention includes a semiconductor substrate, an insulating film formed on the semiconductor substrate, and an insulating film formed on the semiconductor substrate. The semiconductor device includes a diffusion layer wiring formed on the film, a semiconductor film formed on the diffusion layer wiring and the insulating film, and a semiconductor element formed on the semiconductor film.
また、半導体基板と、この半導体基板上に形成され
る、凹部を有する絶縁膜と、前記凹部を埋め込むように
形成される誘電体と、前記導電体及び絶縁膜上に形成さ
れる半導体膜と、前記凹部上の前記半導体膜に形成され
る不純物領域と、前記半導体膜及び不純物領域上に形成
される層間絶縁膜と、前記層間絶縁膜を貫通し、少なく
とも前記不純物領域に達するような、前記凹部上に形成
されるコンタクトホールと、このコンタクトホールに形
成される電極配線とを有している。Further, a semiconductor substrate, an insulating film having a recess formed on the semiconductor substrate, a dielectric formed so as to fill the recess, and a semiconductor film formed on the conductor and the insulating film. The impurity region formed in the semiconductor film on the concave portion, the interlayer insulating film formed on the semiconductor film and the impurity region, and the concave portion penetrating the interlayer insulating film and reaching at least the impurity region. It has a contact hole formed above and an electrode wiring formed in this contact hole.
そして、このような半導体装置の製造方法としては、
まず、半導体基板上に絶縁膜を形成し、この絶縁膜に凹
部を形成する。また、この凹部に導電体を埋め込んで拡
散層配線を形成する。この後、前記拡散層配線及び絶縁
膜上に半導体膜を形成し、この半導体膜に半導体素子を
形成するというものである。And, as a method of manufacturing such a semiconductor device,
First, an insulating film is formed on a semiconductor substrate, and a recess is formed in this insulating film. Further, a conductor is embedded in the recess to form a diffusion layer wiring. After that, a semiconductor film is formed on the diffusion layer wiring and the insulating film, and a semiconductor element is formed on this semiconductor film.
また、半導体基板上に絶縁膜を形成し、この絶縁膜に
凹部を形成する。また、この凹部に導電体を埋め込んだ
後、前記導電体及び絶縁膜上に半導体膜を形成する。さ
らに、前記凹部上の前記半導体膜に不純物領域を形成
し、前記不純物領域及び半導体膜上に層間絶縁膜を形成
する。この後、前記凹部上に前記層間絶縁膜を貫通し少
なくとも前記不純物領域に達するようなコンタクトホー
ルを形成する。そして、このコンタクトホールに電極配
線を形成するというものである。Further, an insulating film is formed on the semiconductor substrate, and a recess is formed in this insulating film. Further, after filling the recess with a conductor, a semiconductor film is formed on the conductor and the insulating film. Further, an impurity region is formed on the semiconductor film on the recess, and an interlayer insulating film is formed on the impurity region and the semiconductor film. After that, a contact hole penetrating the interlayer insulating film and reaching at least the impurity region is formed on the recess. Then, the electrode wiring is formed in this contact hole.
（作 用） このような構成によれば、拡散層配線が半導体膜下の
絶縁膜に形成されるため、前記半導体膜が薄く形成され
ても、拡散層配線の配線抵抗が大きくなるということは
ない。また、導電体が埋め込まれた凹部上に不純物領域
が形成され、又少なくとも前記不純物領域に達するよう
なコンタクトホールが前記凹部上に形成される。このた
め、コンタクトホールが前記不純物領域を突き抜けて形
成されても、前記導電体が存在するので、その下の絶縁
膜には達することがない。この結果、コンタクト部分の
面積は小さくならず、低いコンタクト抵抗を実現でき
る。(Operation) With such a configuration, since the diffusion layer wiring is formed in the insulating film below the semiconductor film, the wiring resistance of the diffusion layer wiring increases even if the semiconductor film is formed thin. Absent. Further, an impurity region is formed on the recess in which the conductor is buried, and a contact hole reaching at least the impurity region is formed on the recess. Therefore, even if the contact hole is formed penetrating the impurity region, the conductor does not reach the insulating film thereunder because the conductor exists. As a result, the area of the contact portion is not reduced, and low contact resistance can be realized.
（実施例） 以下、図面を参照しながら本発明の一実施例について
詳細に説明する。(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.
第１図（ａ）は本発明の一実施例に係わるSOI型MOS半
導体装置の平面パターンを示すものである。また、第１
図（ｂ）は同図（ａ）のＩ−Ｉ′線に沿う断面図を示す
ものである。FIG. 1A shows a plane pattern of an SOI type MOS semiconductor device according to an embodiment of the present invention. Also, the first
FIG. 2B is a sectional view taken along the line II 'of FIG.
シリコン基板11上には膜厚約１μｍの熱酸化膜又はCV
D酸化膜（絶縁膜）12が形成されている。この熱酸化膜
又はCVD酸化膜12には所定の領域、即ちコンタクトホー
ル形成領域の直下に凹部13a、及び拡散層配線形成領域
に凹部13bがそれぞれ形成されている。この凹部13a,13b
には導電体（例えば不純物がドープされた多結晶シリン
コン）14a,14bが埋め込まれている。なお、凹部13bに埋
め込まれた導電体14bにより拡散層配線が形成される。
また、熱酸化膜又はCVD酸化膜12及び導電体14a,14b上に
500Å程度の薄い単結晶シリコン膜（半導体膜）15が形
成されている。そして、単結晶シリコン膜15には半導体
素子、例えばMOSトランジスタが形成されている。具体
的には、凹部13a,13b上の単結晶シリコン膜15にはソー
ス又はドレインとしてのn+不純物領域16が形成されてい
る。n+不純物領域16間のチャネル領域上にはゲート酸化
膜17が形成されている。ゲート酸化膜17上にはゲート電
極18が形成されている。なお、ゲート電極18は不純物が
ドープされた多結晶シリコンから構成することができ
る。そして、これらn+不純物領域16、ゲート酸化膜17及
びゲート電極18によりMOSトランジスタが構成される。
さらに、全面には層間絶縁膜19が形成されている。層間
絶縁膜19には、凹部13a上にコンタクトホール20が形成
されている。なお、コンタクトホール20は、層間絶縁膜
19を貫通し、少なくともn+不純物領域16に達するように
形成される。さらに、コンタクトホール20内にAl配線21
が形成され、n+不純物領域16とAl配線21とのコンタクト
が取られている。A thermal oxide film or CV with a thickness of about 1 μm is formed on the silicon substrate 11.
A D oxide film (insulating film) 12 is formed. In the thermal oxide film or the CVD oxide film 12, a recess 13a is formed in a predetermined region, that is, immediately below the contact hole forming region, and a recess 13b is formed in the diffusion layer wiring forming region. This recess 13a, 13b
Conductors (for example, polycrystalline silicon sillcon doped with impurities) 14a and 14b are embedded therein. The conductor 14b embedded in the recess 13b forms a diffusion layer wiring.
Further, on the thermal oxide film or the CVD oxide film 12 and the conductors 14a, 14b.
A thin single crystal silicon film (semiconductor film) 15 having a thickness of about 500Å is formed. A semiconductor element such as a MOS transistor is formed on the single crystal silicon film 15. Specifically, an n + impurity region 16 as a source or a drain is formed in the single crystal silicon film 15 on the recesses 13a and 13b. A gate oxide film 17 is formed on the channel region between the n + impurity regions 16. A gate electrode 18 is formed on the gate oxide film 17. The gate electrode 18 can be made of polycrystalline silicon doped with impurities. Then, the n + impurity region 16, the gate oxide film 17, and the gate electrode 18 form a MOS transistor.
Further, an interlayer insulating film 19 is formed on the entire surface. In the interlayer insulating film 19, a contact hole 20 is formed on the recess 13a. The contact hole 20 is an interlayer insulating film.
It is formed so as to penetrate 19 and reach at least n + impurity region 16. In addition, Al wiring 21 in the contact hole 20.
Are formed, and the n + impurity region 16 and the Al wiring 21 are contacted with each other.
次に、第１図（ａ）及び（ｂ）乃至第３図（ａ）及び
（ｂ）を参照しながら本発明に係わるSOI型MOS半導体装
置の製造方法について詳細に説明する。ここで、第２図
（ｂ）は同図（ａ）のII−II′線に沿う断面図を示し、
第３図（ｂ）は同図（ａ）のIII−III′線に沿う断面図
を示している。Next, a method of manufacturing an SOI type MOS semiconductor device according to the present invention will be described in detail with reference to FIGS. 1 (a) and (b) to FIGS. 3 (a) and (b). Here, FIG. 2B is a sectional view taken along line II-II ′ of FIG.
FIG. 3 (b) is a sectional view taken along the line III-III 'in FIG. 3 (a).
まず、第２図（ａ）及び（ｂ）に示すように、シリコ
ン基板11上に膜厚約１μｍの熱酸化膜又はCVD酸化膜12
を堆積形成する。この後、コンタクトホール形成領域の
直下及び拡散層配線形成領域となる部分の熱酸化膜又は
CVD酸化膜12をフォトリソグラフ工程により約0.5μｍエ
ッチングし、凹部13a,13bを形成する。さらに、全面に
第１の多結晶シリコン膜を堆積形成した後、不純物をド
ーピングする。また、全面エッチバックを行うことによ
り、凹部13a,13bには不純物がドープされた第１の多結
晶シリコン（導電体）14a,14bが埋め込まれる。First, as shown in FIGS. 2A and 2B, a thermal oxide film or a CVD oxide film 12 having a film thickness of about 1 μm is formed on a silicon substrate 11.
Is deposited. After this, the thermal oxide film immediately below the contact hole formation region and the portion to be the diffusion layer wiring formation region or
The CVD oxide film 12 is etched by about 0.5 μm by a photolithography process to form recesses 13a and 13b. Furthermore, after depositing a first polycrystalline silicon film on the entire surface, impurities are doped. Further, by performing the entire surface etch back, the first polycrystalline silicon (conductor) 14a, 14b doped with impurities is buried in the recesses 13a, 13b.
次に、第３図（ａ）及び（ｂ）に示すように、全面に
非結晶シリコン膜を約500Å堆積形成する。この後、レ
ーザアニール、電子ビームアニール等により前記非結晶
シリコン膜を結晶化し、単結晶シリコン膜15を形成す
る。また、この単結晶シリコン膜15をフォトリソグラフ
工程を用いて島状にエッチングすることにより、素子能
動領域を形成する。さらに、熱酸化法を用いてゲート酸
化膜18を形成した後、全面には第２の多結晶シリコン膜
を堆積形成する。また、前記第２の多結晶シリコン膜を
導電体にするためリン（Ｐ）を拡散する。この後、フォ
トリソグラフ工程を用いてゲート電極18及び多結晶シリ
コン配線（図示せず）を形成する。さらに、このゲート
電極18をマスクにしてリン又はヒ素（As）をイオン注入
し、ソース又はドレインとしてのn+不純物領域16を形成
する。Next, as shown in FIGS. 3A and 3B, an amorphous silicon film is deposited on the entire surface by about 500 liters. After that, the amorphous silicon film is crystallized by laser annealing, electron beam annealing or the like to form a single crystal silicon film 15. In addition, the single crystal silicon film 15 is etched into an island shape by using a photolithography process to form an element active region. Further, after the gate oxide film 18 is formed by using the thermal oxidation method, a second polycrystalline silicon film is deposited and formed on the entire surface. In addition, phosphorus (P) is diffused in order to make the second polycrystalline silicon film a conductor. After that, a gate electrode 18 and a polycrystalline silicon wiring (not shown) are formed by using a photolithography process. Further, phosphorus or arsenic (As) is ion-implanted using the gate electrode 18 as a mask to form an n + impurity region 16 as a source or a drain.
次に、第１図（ａ）及び（ｂ）に示すように、全面に
層間絶縁膜19を堆積形成した後、フォトリソグラフ工程
を用いて凹部13a上の層間絶縁膜19にコンタクトホール2
0を形成する。また、コンタクトホール20内にAl配線21
を形成し、n+不純物領域16とAl配線21とのコンタクトを
取る。Next, as shown in FIGS. 1A and 1B, after depositing an interlayer insulating film 19 on the entire surface, a photolithography process is used to form a contact hole 2 in the interlayer insulating film 19 on the recess 13a.
Form a 0. In addition, Al wiring 21 in the contact hole 20
To form a contact between the n + impurity region 16 and the Al wiring 21.
このような構成によれば、拡散層配線は、薄く形成さ
れた単結晶シリコン膜15に形成されることなく、熱酸化
膜又はCVD酸化膜12に形成された凹部13bに形成されてい
る。即ち、拡散層配線は、熱酸化膜又はCVD酸化膜12の
凹部13bに埋め込まれた第１の多結晶シリコン14bにより
構成される。これにより、拡散層配線の配線抵抗を小さ
くすることが可能になると共に、設計の自由度が上るた
め高集積化にとっても有利になる。According to such a configuration, the diffusion layer wiring is formed in the recess 13b formed in the thermal oxide film or the CVD oxide film 12 without being formed in the thinly formed single crystal silicon film 15. That is, the diffusion layer wiring is composed of the first polycrystalline silicon 14b embedded in the recess 13b of the thermal oxide film or the CVD oxide film 12. As a result, the wiring resistance of the diffusion layer wiring can be reduced, and the degree of freedom in design is increased, which is advantageous for high integration.
また、Al配線21とn+不純物領域16とのコンタクトをと
るためのコンタクトホール20直下には、第１の多結晶シ
リコン14aの埋め込まれた凹部13aが形成されている。こ
のため、RIE等によって形成されるコンタクトホール
は、ソース又はドレインとしてのn+不純物領域16を突き
抜けて形成されても、凹部13aに第１の多結晶シリコン1
4aが存在するため、その下の熱酸化膜又はCVD酸化膜12
に達することはない。よって、Al配線21とn+不純物領域
16とのコンタクト部分の面積が小さくなることはなく、
Al配線21とn+不純物領域16とのコンタクト抵抗が大きく
なるのを防ぐことができる。Further, a recess 13a in which the first polycrystalline silicon 14a is embedded is formed immediately below the contact hole 20 for making contact with the Al wiring 21 and the n + impurity region 16. Therefore, even if the contact hole formed by RIE or the like is formed so as to penetrate through the n + impurity region 16 as the source or the drain, the first polycrystalline silicon 1 is formed in the recess 13a.
4a is present, so thermal oxide film or CVD oxide film 12
Never reach. Therefore, the Al wiring 21 and the n + impurity region
The area of the contact part with 16 does not become small,
It is possible to prevent the contact resistance between the Al wiring 21 and the n + impurity region 16 from increasing.
なお、前記実施例では、ｎチャネルのSOI型MOS半導体
装置について述べてきたが、ｐチャネル型又は相補型の
MOS半導体装置であっても本発明を適用することができ
る。また、多結晶シリコン14a,14bは独自に不純物をド
ーピングして形成したが、イオン注入法によりn+不純物
領域16の形成と同時に形成してもよい。さらに、凹部13
a,13bに埋め込まれる導電体は多結晶シリコンに限ら
ず、単結晶シリコン、非結晶シリコン、シリサイド、ポ
リサイド、高融点金属等であってもよい。It should be noted that although the n-channel SOI type MOS semiconductor device has been described in the above-mentioned embodiment, the p-channel type or the complementary type is used.
The present invention can be applied even to a MOS semiconductor device. Further, the polycrystalline silicons 14a and 14b are formed by uniquely doping impurities, but they may be formed simultaneously with the formation of the n + impurity regions 16 by an ion implantation method. Furthermore, the recess 13
The conductor embedded in a and 13b is not limited to polycrystalline silicon, but may be single crystal silicon, amorphous silicon, silicide, polycide, refractory metal, or the like.
［発明の効果］ 以上、説明したように、本発明のSOI型半導体装置及
びその製造方法によれば、次のような効果を奏する。[Effects of the Invention] As described above, according to the SOI semiconductor device and the method for manufacturing the same of the present invention, the following effects are achieved.
薄く形成された単結晶シリコン膜に拡散層配線を形成
することなく、その直下の絶縁膜に凹部を形成し、この
凹部に拡散層配線を形成している。このため、拡散層配
線の配線抵抗が小さくなると共に、設計の自由度が向上
し、高集積化にとっても有利になる。Without forming the diffusion layer wiring in the thinly formed single crystal silicon film, a recess is formed in the insulating film immediately below the diffusion layer wiring, and the diffusion layer wiring is formed in this recess. Therefore, the wiring resistance of the diffusion layer wiring is reduced, the degree of freedom in design is improved, and this is advantageous for high integration.
また、導電体が埋め込まれた凹部上にコンタクトホー
ルを形成している。このため、コンタクトホールがソー
ス又はドレインとしてのn+不純物領域を突き抜けて形成
されても、コンタクト部分の面積が小さくなることはな
い。Further, a contact hole is formed on the recess in which the conductor is embedded. Therefore, even if the contact hole is formed through the n + impurity region as the source or the drain, the area of the contact portion is not reduced.
即ち、コンタクト抵抗を大きくすることなく、かつ、
拡散層配線の配線抵抗を大きくすることなく製作できる
ような高速、高性能、高品質のSOI型MOS半導体装置を提
供することができる。That is, without increasing the contact resistance, and
It is possible to provide a high-speed, high-performance, high-quality SOI type MOS semiconductor device that can be manufactured without increasing the wiring resistance of the diffusion layer wiring.
第１図（ａ）は本発明の一実施例に係わるSOI型MOS半導
体装置を示す平面パターン図、第１図（ｂ）は前記第１
図（ａ）のＩ−Ｉ′線に沿う断面図、第２図（ａ）は本
発明の一実施例に係わるSOI型MOS半導体装置の製造方法
を説明するための平面パターン図、第２図（ｂ）は前記
第２図（ａ）のII−II′線に沿う断面図、第３図（ａ）
は本発明の一実施例に係わるSOI型MOS半導体装置の製造
方法を説明するための平面パターン図、第３図（ｂ）は
前記第３図（ａ）のIII−III′線に沿う断面図、第４図
乃至び第６図は、それぞれ従来のSOI型MOS半導体装置を
示す断面図である。 11……シリコン基板、12……熱酸化膜又はCVD酸化膜、1
3a,13b……凹部、14a,14b……導電体、15……単結晶シ
リコン膜、17……ゲート酸化膜、18……ゲート電極、19
……層間絶縁膜、20……コンタクトホール、21……Al配
線。FIG. 1A is a plan view showing an SOI type MOS semiconductor device according to an embodiment of the present invention, and FIG.
FIG. 2A is a sectional view taken along the line II ′ of FIG. 2A, and FIG. 2A is a plan pattern diagram for explaining a method of manufacturing an SOI type MOS semiconductor device according to an embodiment of the present invention. 2B is a sectional view taken along the line II-II ′ of FIG. 2A, and FIG. 3A.
Is a plan view for explaining a method of manufacturing an SOI type MOS semiconductor device according to an embodiment of the present invention, and FIG. 3 (b) is a sectional view taken along the line III-III 'in FIG. 3 (a). 4 to 6 are cross-sectional views showing a conventional SOI type MOS semiconductor device, respectively. 11 ... Silicon substrate, 12 ... Thermal oxide film or CVD oxide film, 1
3a, 13b ... Recessed portion, 14a, 14b ... Conductor, 15 ... Single crystal silicon film, 17 ... Gate oxide film, 18 ... Gate electrode, 19
...... Interlayer insulation film, 20 ...... Contact hole, 21 ...... Al wiring.
Claims (2)
れる、凹部を有する絶縁膜と、前記凹部を埋め込むよう
に形成される導電体と、前記導電体及び絶縁膜上に形成
される半導体膜と、前記凹部上の前記半導体膜に形成さ
れる不純物領域と、前記半導体膜及び不純物領域上に形
成される層間絶縁膜と、前記層間絶縁膜を貫通し、少な
くとも前記不純物領域に達するような、前記凹部上に形
成されるコンタクトホールと、このコンタクトホールに
形成される電極配線とを具備することを特徴とするSOI
型半導体装置。1. A semiconductor substrate, an insulating film having a recess formed on the semiconductor substrate, a conductor formed so as to fill the recess, and a semiconductor formed on the conductor and the insulating film. A film, an impurity region formed on the semiconductor film on the recess, an interlayer insulating film formed on the semiconductor film and the impurity region, and penetrating the interlayer insulating film to reach at least the impurity region. An SOI having a contact hole formed on the recess and an electrode wiring formed in the contact hole
Type semiconductor device.
この絶縁膜に凹部を形成する工程と、この凹部に導電体
を埋め込む工程と、前記導電体及び絶縁膜上に半導体膜
を形成する工程と、前記凹部上の前記半導体膜に不純物
領域を形成する工程と、前記半導体膜及び不純物領域上
に層間絶縁膜を形成する工程と、前記凹部上に前記層間
絶縁膜を貫通し少なくとも前記不純物領域に達するよう
なコンタクトホールを形成する工程と、このコンタクト
ホールに電極配線を形成する工程とを具備することを特
徴とするSOI型半導体装置の製造方法。2. A step of forming an insulating film on a semiconductor substrate,
Forming a recess in the insulating film, embedding a conductor in the recess, forming a semiconductor film on the conductor and the insulating film, and forming an impurity region in the semiconductor film on the recess A step of forming an interlayer insulating film on the semiconductor film and the impurity region, a step of forming a contact hole on the recess so as to penetrate the interlayer insulating film and reach at least the impurity region, and the contact hole And a step of forming an electrode wiring on the substrate, the method for manufacturing an SOI type semiconductor device.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1230534A JP2509708B2 (en) | 1989-09-07 | 1989-09-07 | SOI type semiconductor device and manufacturing method thereof |
| PCT/JP1990/001124 WO1993017458A1 (en) | 1989-09-07 | 1990-09-04 | Soi-type semiconductor device and method of producing the same |
| US07/684,932 US5191397A (en) | 1989-09-07 | 1990-09-04 | SOI semiconductor device with a wiring electrode contacts a buried conductor and an impurity region |
| KR1019900014130A KR940002839B1 (en) | 1989-09-07 | 1990-09-07 | Soi semiconductor device and fabricating method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1230534A JP2509708B2 (en) | 1989-09-07 | 1989-09-07 | SOI type semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0395937A JPH0395937A (en) | 1991-04-22 |
| JP2509708B2 true JP2509708B2 (en) | 1996-06-26 |
Family
ID=16909256
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1230534A Expired - Lifetime JP2509708B2 (en) | 1989-09-07 | 1989-09-07 | SOI type semiconductor device and manufacturing method thereof |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP2509708B2 (en) |
| KR (1) | KR940002839B1 (en) |
| WO (1) | WO1993017458A1 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0722517A (en) * | 1993-06-22 | 1995-01-24 | Mitsubishi Electric Corp | Semiconductor device and its manufacture |
| JPH07283414A (en) * | 1994-04-05 | 1995-10-27 | Toshiba Corp | Mos-type semiconductor device |
| WO2013039126A1 (en) * | 2011-09-16 | 2013-03-21 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
| US9082663B2 (en) * | 2011-09-16 | 2015-07-14 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6194366A (en) * | 1984-10-16 | 1986-05-13 | Toshiba Corp | Thin-film transistor |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59125663A (en) * | 1983-01-05 | 1984-07-20 | Seiko Instr & Electronics Ltd | Manufacture of thin film semiconductor device |
| JPS63265464A (en) * | 1987-04-23 | 1988-11-01 | Agency Of Ind Science & Technol | Manufacture of semiconductor device |
-
1989
- 1989-09-07 JP JP1230534A patent/JP2509708B2/en not_active Expired - Lifetime
-
1990
- 1990-09-04 WO PCT/JP1990/001124 patent/WO1993017458A1/en unknown
- 1990-09-07 KR KR1019900014130A patent/KR940002839B1/en not_active IP Right Cessation
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6194366A (en) * | 1984-10-16 | 1986-05-13 | Toshiba Corp | Thin-film transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0395937A (en) | 1991-04-22 |
| WO1993017458A1 (en) | 1993-09-02 |
| KR910007140A (en) | 1991-04-30 |
| KR940002839B1 (en) | 1994-04-04 |
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