JPH0521446A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To increase a current capacity by a structure wherein a base region and a collector region are arranged around an emitter region by using the emitter region as the center. CONSTITUTION:An insulating layer 18 is formed on an n-type single-crystal silicon active layer 6 formed on a substrate 1 via an insulating layer 2. Then, an n-type subcollector region 6S is formed in the active layer 6 through the insulating layer 18; after that, the insulating layer 18 is etched; an opening which is a little larger than a base region is formed. Then, an insulating layer 20 and a polycrystalline silicon layer 70 are etched sequentially; a base-emitter opening part is formed; after that, a sidewall insulating layer 21 is formed on the side face of a base extraction electrode 7. Then, an n-type emitter region 6E is formed inside the base region; after that, an n-type polycrystalline silicon layer is deposited and patterned; an emitter electrode 9 and a collector electrode 11 are formed. An opening is formed in the insulating layer 20; a base electrode 22 is formed. Thereby, a current capacity can be increased without increasing the occupied area of an element.

Description

Detailed Description of the Invention

[0001]

The present invention relates to SOI (Silicon on Insulat)
or) structure semiconductor devices, especially lateral bipolar transistors.

2. Description of the Related Art A semiconductor substrate having an SOI structure forms an insulating layer by ion-implanting oxygen to a predetermined depth in a silicon wafer
Due to advances in manufacturing technology such as SIMOX (separation by implanted oxygen) and bonding two silicon wafers,
It is possible to reduce the thickness of silicon, which is the active layer, to about submicron.

[0003]

SO having a thin silicon layer as described above
By using the I substrate, MOS with higher integration
It is possible to suppress the short channel effect of a field effect transistor (FET) and improve gm.

On the other hand, since the load driving capability of the MOSFET is not sufficient, an integrated circuit (IC) having a so-called BiMOS structure incorporating a bipolar transistor has begun to be put into practical use. Bipolar transistors in ordinary BiMOS-ICs are vertical bipolar transistors that pass a current in the vertical direction (thickness direction of the semiconductor layer). However, the vertical bipolar transistor requires a large number of manufacturing steps. In addition, a high concentration buried layer that becomes a subcollector is required, but it is almost impossible to form such a buried layer in a submicron thin semiconductor layer.

[0005]

It is well known to form a lateral bipolar transistor in a semiconductor layer having an SOI structure. FIG. 6 is a schematic perspective view showing a conventional structure of such a lateral bipolar transistor.
That is, the active layer 3 made of, for example, single crystal silicon is formed on the support substrate 1 via the insulating layer 2.
Usually, such an active layer 3 is separated for each individual transistor. In the active layer 3, for example, a p-type base region 3B and an n-type collector region 3C and an emitter region 3E are formed on both sides so as to sandwich the base region 3B. In the base region 3B, for example, a base electrode 4 made of polycrystalline silicon doped with a high concentration of p-type impurities is formed.

As described above, for the MOSFET, it is advantageous to reduce the thickness (t) of the active layer 3 in order to suppress the short channel effect. However, for lateral bipolar transistors, the thinner active layer 3
The current that can be passed through the device becomes smaller. Therefore, in order to maintain a constant current, the emitter width (W) must be increased. As a result, the area occupied by each lateral bipolar transistor on the supporting substrate 1 becomes large, and along with this, the resistance of the base electrode 4 also increases because the length of the base electrode 4 increases. These are SOI
This is an obstacle to high integration and high performance of the structured BiMOS-IC.

According to the present invention, even if the active layer in the SOI substrate is thinned, a larger current can be made to flow even though the area occupied is equal to or smaller than that of the conventional lateral bipolar transistor, and An object is to provide a lateral bipolar transistor having a smaller base electrode resistance.

[0008]

The above object is to provide a semiconductor layer of one conductivity type formed on a supporting substrate via an insulating layer, an emitter region of one conductivity type formed in the semiconductor layer, and the semiconductor layer. A base region of opposite conductivity type formed in the semiconductor layer so as to penetrate the layer and surround the emitter region;
A semiconductor device according to the present invention comprising a collector region formed of the semiconductor layer of one conductivity type around the base region, or a semiconductor device formed on a supporting substrate via an insulating layer. Impurities are introduced into a predetermined region defined on the surface of the conductivity type semiconductor layer to form a region of the opposite conductivity type distributed from the surface to the depth reaching the insulating layer, and a predetermined region is formed in the region of the opposite conductivity type. Introducing a concentration of impurities to form a region of one conductivity type surrounded by a region of the opposite conductivity type,
An interlayer insulating layer is formed on the semiconductor layer having a region of one conductivity type, the region of the opposite conductivity type, a region surrounding the region of the opposite conductivity type, and the region formed in the region of the opposite conductivity type. An opening that exposes at least a part of the surface of the semiconductor layer in each of the regions of one conductivity type is formed in the interlayer insulating layer, and the region is formed through the opening on the interlayer insulating layer. And a step of forming an electrode connected to the surface of the semiconductor layer, in the method of manufacturing a semiconductor device according to the present invention.

[0009]

FIG. 1 is a schematic sectional view (a) and a plan view showing the principle structure of the lateral bipolar transistor of the present invention.
It is (b). That is, an n-type emitter region 6E is formed on the support substrate 1 with the insulating layer 2 interposed therebetween, for example, in the approximate center of the n-type active layer 6 so as to surround the emitter region 6E. Thus, the p-type base region 6B is formed. The n-type active layer 6 around the base region 6B becomes the collector region 6C. Around the collector region 6C, a sub-collector region 6S formed by introducing a high concentration n-type impurity
Are formed.

As described above, in the lateral bipolar transistor of the present invention, the base region and the collector region are arranged around the emitter region as the center. In this structure, it is essential that at least the base region is formed to have a depth that penetrates the active layer. Although FIG. 1 shows the case where the emitter region 6E is also formed so as to penetrate the active layer 6, it does not matter in principle that the base region 6B remains below the emitter region 6E.

A base lead electrode 7 connected to the base region 6B is formed on the active layer 6 via an interlayer insulating layer 8. On the base extraction electrode 7, the emitter region
An emitter electrode 9 connected to 6E is formed via an interlayer insulating layer 10. Further, a collector electrode 11 connected to the sub-collector region 6S is formed.

According to the above-mentioned structure of the present invention, compared with the conventional lateral bipolar transistor shown in FIG. 6 in which the collector, the base and the emitter are arranged in a straight line, even if the occupation area on the supporting substrate 1 is small, It is possible to flow the same current. In other words, it is possible to increase the degree of integration of devices while maintaining the same current capacity. Further, since the resistance of the base electrode does not increase as in the structure shown in FIG. 6, the margin for the voltage drop that occurs when the current capacity is designed large increases.

[0013]

FIG. 2 is an explanatory view of the first embodiment of the present invention. In order to lower the collector resistance in the structure of FIG. 1, the surface of the active layer 6 in the sub-collector region 6S is selectively silicified. It shows the case. In the figure,
The region marked with 12 is the silicided portion. This silicidation is possible by selectively forming a refractory metal or its silicide in the subcollector region 6S.

FIG. 3 is an explanatory view of the second embodiment of the present invention. Similarly, in order to lower the collector resistance in the structure of FIG. 1, a part of the sub-collector region 6S is silicided over the entire layer thickness. It shows the case. In the figure, the region denoted by reference numeral 13 is the silicidized portion. This silicidation can be performed by selectively growing tungsten (W) from the open side surface of the subcollector region 6S.

FIG. 3 is an explanatory view of the third embodiment of the present invention. In order to reduce the base resistance in the structure of FIG.
The case where the surface of the base lead electrode 7 is silicided is shown. In the figure, the region denoted by reference numeral 14 is the silicidized portion. This silicided base extraction electrode 7 can be formed by depositing a refractory metal or its silicide on the polycrystalline silicon layer forming the base extraction electrode 7 and patterning these with the same mask.

FIG. 5 is a sectional view of an essential part for explaining an embodiment of a method of manufacturing a lateral bipolar transistor having the structure of FIG. Referring to FIG. 1 (a), an SOI substrate including a supporting substrate 1 such as a silicon wafer and an n-type single crystal silicon active layer 6 formed on the supporting substrate 1 with an insulating layer 2 made of SiO ₂ interposed therebetween. To prepare. Active layer 6 is about
It has a thickness of 0.3 μm and its impurity concentration or resistivity is
It is 0.1 Ω-cm.

On the active layer 6, a thickness of SiO _{2 of} about 0.1 μm
An m insulating layer 18 is formed. The insulating layer 18 may be formed by any of the well-known thermal oxidation and CVD (chemical vapor deposition) methods.

Next, an n-type impurity is ion-implanted into a predetermined region of the active layer 6 through the insulating layer 18 to form a sub-collector region 6S. The ion implantation conditions are, for example, arsenic (As) as an n-type impurity, an acceleration energy of 300 KeV, and a dose of 1 × 10 ¹⁶ / cm ³ .

Then, using the well-known lithographic technique,
The insulating layer 18 is selectively etched to form a slightly larger opening including a base region 6B described later. The active layer 6 is exposed in this opening. Then, a polycrystalline silicon layer 70 doped with, for example, boron (B) as a p-type impurity is deposited on the surface of the substrate. After that, the insulating layer 20 made of, for example, SiO ₂ is deposited on the polycrystalline silicon layer 70.

Then, using the well-known lithographic technique,
The insulating layer 20 and the polycrystalline silicon layer 70 are sequentially and selectively etched to form a base / emitter opening. In this patterning, the polycrystalline silicon layer 70 is patterned into the shape of the base extraction electrode 7. The base extraction electrode 7 is in contact with the active layer 6 exposed in the opening provided in the insulating layer 18.

In the patterning of the polycrystalline silicon layer 70, it is desirable that the end of etching is performed by wet etching in order to prevent ion damage to the active layer 6 exposed in the base / emitter opening. Further, in the above, after removing the insulating layer 18 after the ion implantation for forming the sub-collector region 6S,
Another insulating layer corresponding to the insulating layer 18 may be formed on the surface of the active layer 6.

Next, as shown in FIG. 1B, a sidewall insulating layer 21 is formed on the side surface of the base lead electrode 7. The sidewall insulating layer 21 is formed on the substrate surface with a thickness of, for example, SiO _2.
A well-known technique of depositing an insulating layer of 0.3 μm and subjecting this insulating layer to anisotropic etching such as reactive ion etching (RIE) may be used. After that, p-type impurities are ion-implanted into the base / emitter opening. This ion implantation may be performed using the sidewall insulating layer 21 and the base extraction electrode 7 as a mask. The implantation conditions are, for example, boron (B) ions as an impurity, acceleration energy of 50 KeV, and dose of 3 × 10 ¹³ ions / cm ^3. And

By the above-mentioned ion implantation, the active layer 6 in the base / emitter opening is converted to p-type. If necessary, ion-implanted p-type impurity atoms may be added to the sidewall insulating layer.
A heat treatment for diffusing under 21 is performed. Further, prior to the formation of the sidewall insulating layer 21, p-type impurities may be ion-implanted into the base region, and then the order of forming the sidewall insulating layer 21 may be changed as described above. Furthermore, even if the above-mentioned anisotropic etching for forming the sidewall insulating layer 21 is performed by RIE, the region finally serving as the base is the sidewall insulating layer 21.
Since it is covered by, it is not affected by ion damage.

Next, an n-type impurity is ion-implanted into the base region to form an emitter region 6E in the active layer 6 in the base / emitter opening as shown in FIG. 1 (c).
The ion implantation conditions are, for example, arsenic (As) or phosphorus (P) as an impurity, an acceleration energy of 400 KeV, and a dose of 1
× 10 ¹⁶ pieces / cm ³ As a result, the p-type base region 6B having a thickness substantially equal to that of the sidewall insulating layer 21 is left around the emitter region 6E. According to the acceleration energy having the above value, the n-type impurity reaches the bottom of the active layer 6, so that the emitter region 6E is formed so as to be in contact with the insulating layer 2. By setting this acceleration energy to a smaller value and performing ion implantation, as described above, the emitter region 6E
Are formed so that the p-type base region 6B remains at the bottom thereof. This structure can also operate as a lateral bipolar transistor.

Then, a polycrystalline silicon layer doped with, for example, an n-type impurity is deposited on the surface of the substrate and patterned to form an emitter electrode 9 connected to the emitter region 6E as shown in FIG. 1 (d). And a collector electrode 11 connected to the sub-collector region 6S is formed. Further, after forming an opening for exposing the base lead electrode 7 in the insulating layer 20,
The base electrode 22 connected to the base extraction electrode 7 is formed through this opening, and the lateral bipolar transistor of the present invention is completed.

After the ion implantation for forming the base region 6B or the ion implantation for forming the emitter region 6E, a heat treatment for activating the impurities introduced therein is performed. The p-type impurity doped in the base extraction electrode 7 diffuses into the active layer 6 in this heat treatment to form the high concentration region 23. As a result, the connection between the base region 6B and the base lead electrode 7 becomes reliable and has low resistance.

In the above embodiment, the case of forming the npn-type lateral bipolar transistor has been described as an example, but by changing the conductivity type of each layer including the active layer 6, the pnp-type lateral bipolar transistor is changed. It is also possible to manufacture In addition, in the above-described embodiment, the surface of the polycrystalline silicon layer 70 forming a part of the active layer 6 or the base extraction electrode 7 in the sub-collector region 6S is formed by the silicide as described with reference to FIGS. It is also possible to convert. Furthermore, the lateral bipolar transistor according to the above is the same SO
It can be formed on the active layer on the I substrate in combination with MOSFETs or CMOS transistors.

[0028]

According to the present invention, it is possible to manufacture a lateral bipolar transistor having a larger current capacity than before without increasing the area occupied by the element. The base region and the emitter region can be formed in a self-aligned manner. Moreover, the thickness of the base region is controlled by the thickness of the sidewall insulating layer in the base-emitter opening, so that a thin and uniform base layer can be formed. Furthermore, it is possible to prevent the increase of base resistance and collector resistance due to the miniaturization of the device. As a result, high-performance and highly-integrated Bi composed of lateral bipolar transistor and MOSFET
It has an effect of contributing to promotion of practical use of a semiconductor device having a MOS or BiCMOS configuration.

[Brief description of drawings]

FIG. 1 is an explanatory view of the principle structure of the present invention.

FIG. 2 is an explanatory diagram of the first embodiment of the present invention.

FIG. 3 is an explanatory diagram of a second embodiment of the present invention.

FIG. 4 is an explanatory diagram of a third embodiment of the present invention.

FIG. 5 is an explanatory view of an embodiment of the manufacturing method of the present invention.

FIG. 6 is an explanatory diagram of problems in a conventional lateral bipolar transistor.

[Explanation of symbols]

1 Support substrate 7 Base extraction electrode 2, 18, 20 Insulation layer 8, 10 Interlayer insulation layer 3, 6 Active layer 9 Emitter electrode 3B, 6B Base region 11 Collector electrode 3C, 6C Collector region 12, 13, 14 Silicided Part 3E, 6E Emitter region 21 Sidewall insulating layer 4, 22 Base electrode 23 High concentration region 6S Subcollector region 70 Polycrystalline silicon layer

Claims (5)

[Claims] 1. A one-conductivity-type semiconductor layer formed on a supporting substrate with an insulating layer interposed therebetween, a one-conductivity-type emitter region formed in the semiconductor layer, and the emitter region penetrating the semiconductor layer. A semiconductor region comprising a base region of opposite conductivity type formed in the semiconductor layer so as to surround the semiconductor layer, and a collector region formed of the semiconductor layer of the one conductivity type around the base region. apparatus. 2. The semiconductor device according to claim 1, wherein the emitter region is formed so as to penetrate the semiconductor layer. 3. An electrode formed on the semiconductor layer, the electrode having a base electrode connected to the base region and a collector electrode connected to the collector region, wherein either the base electrode or the collector electrode is provided. 2. A silicide layer is formed at least in the vicinity of the upper surface.
The semiconductor device described. 4. An impurity is introduced into a predetermined region defined on the surface of a semiconductor layer of one conductivity type formed on a supporting substrate via an insulating layer and distributed over a depth reaching from the surface to the insulating layer. Forming a region of opposite conductivity type; forming a region of one conductivity type surrounded by the region of opposite conductivity type by introducing an impurity of a predetermined concentration into the region of opposite conductivity type; A step of forming an interlayer insulating layer on the semiconductor layer having a region of conductivity type; a region of the opposite conductivity type, a region around the region of opposite conductivity type, and a region formed in the region of opposite conductivity type. Forming an opening in the interlayer insulating layer that exposes at least a part of the surface of the semiconductor layer in each of the regions of one conductivity type; and through the opening on the interlayer insulating layer in which the opening is formed. An electrode connected to the surface of the semiconductor layer in the region of The method of manufacturing a semiconductor device which comprises the step of. 5. A step of forming a second insulating layer on the surface of a semiconductor layer of one conductivity type formed on a supporting substrate via a first insulating layer, and a predetermined region defined on the surface of the semiconductor layer. Forming a first opening in the second insulating layer that exposes the second insulating layer, and forming a conductive layer in contact with the semiconductor layer through the first opening and containing an impurity of the opposite conductivity type with the second insulating layer. Forming on the layer, forming a second opening in the conductive layer, the second opening being included in the first opening and exposing the semiconductor layer in the first opening; and the second opening. A step of selectively introducing an impurity of an opposite conductivity type with respect to the semiconductor layer exposed inside so as to be distributed over a depth reaching the first insulating layer from the surface of the semiconductor layer; After the introduction of at least the second
A step of forming an insulating side wall layer on the side surface of the conductive layer exposed in the opening, and the semiconductor layer exposed in the second opening after forming the side wall layer on the side surface of the conductive layer A step of introducing one conductivity type impurity having a concentration higher than that for compensating for the opposite conductivity type impurity, and a heat treatment step for activating the opposite conductivity type impurity and the one conductivity type impurity introduced into the semiconductor layer. And a step of forming an interlayer insulating layer on the semiconductor layer into which the impurity of one conductivity type has been introduced, and the step of forming an interlayer insulating layer on each of the conductive layer, the region of the one conductivity type and the region of the opposite conductivity type. And a step of forming electrodes, which are respectively connected to the surface of the semiconductor layer, on the interlayer insulating layer.