JPH0575033A - Semiconductor integrated circuit device and manufacture thereof - Google Patents

Abstract

PURPOSE:To realize both improvement in the degree of integration and increase in working speed of a semiconductor integrated circuit device. CONSTITUTION:The concentration gradient of impurity concentration distribution in the rectangular direction to a junction section in an n<+> buried layer is constituted at the two stages of distribution 2a having high concentration and distribution 2b having low concentration in the junction section of the n<+> buried layer organizing the collector of a bipolar-transistor and a p<+> buried layer surrounding the n<+> buried layer, and the region of distribution 2b having low concentration is p-n joined with the p<+> buried layer. The concentration gradient of impurity concentration distribution in the rectangular direction to the junction section in the p<+> buried layer is constructed at the two stages of distribution having high concentration and distribution having low concentration, and the region of distribution having low concentration may be p-n joined with the n<+> buried layer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device having a high-concentration buried layer in the collector of a bipolar transistor and a method for manufacturing the same.

[0002]

2. Description of the Related Art A technique relating to a semiconductor integrated circuit device having a bipolar transistor is disclosed in, for example, "Nikkei Microdevice", February 1990, p.
3 to p54. According to this, an integrated circuit device having a bipolar transistor is generally
In the PN transistor, n + forming a part of the collector is buried inside the substrate, and p + is buried so as to surround n + in order to electrically separate this n + from other elements.

The structure of the buried layer shown in the prior art can be roughly divided into two. That is, one has a structure in which n + and p + are produced by self-alignment and n + and p + form a direct PN junction, and the other is p + produced in a desired region using a photoresist as a mask. + And p + are directly PN
It is a structure that does not form a bond.

[0004]

However, the former one of the above-mentioned prior arts is suitable for high integration because the PN junction is formed by self-alignment.
Since + and p + form a PN junction, the junction capacitance is increased, the parasitic capacitance between the collector of the bipolar transistor and the substrate is increased, and no consideration is given to the speedup of the integrated circuit device.

In the latter case, high concentrations of n + and p + do not form a PN junction and the parasitic capacitance can be reduced, which is suitable for speeding up, but p + is produced using a photoresist as a mask. Considering the alignment margin, n + and p + must be separated, and no consideration has been given to the high integration.

An object of the present invention is to provide a semiconductor integrated circuit device capable of realizing both high integration and high speed and a manufacturing method thereof.

[0007]

In order to achieve the above object, the present invention comprises a bipolar transistor,
The bipolar transistor is a semiconductor integrated circuit device in which an n + buried layer is further stacked on a substrate, an n-type region is further stacked thereon, and a field oxide film for separating adjacent bipolar transistors is formed. At the junction of the n + buried layer forming the collector of the transistor and the p + buried layer surrounding the n + buried layer, one of the n + buried layer and the p + buried layer is buried. The concentration gradient of the impurity concentration distribution in the direction perpendicular to the junction in the buried layer was formed in two steps, a high-concentration distribution and a low-concentration distribution, and the region of the low-concentration distribution was PN-junctioned with the other buried layer. It is a thing.

The present invention also provides a bipolar transistor, an n-channel MOS transistor and a p-channel M.
The bipolar transistor has an n + buried layer on the substrate and an n-type region further stacked thereon, and the n-channel MOS transistor has a p + buried layer on the substrate and further thereon. p-type regions are stacked, the p-channel MOS transistor has an n + buried layer on a substrate, and an n-type region is further stacked thereon, and the bipolar transistor, the n-channel MOS transistor, and the p-channel MOS transistor are respectively formed. In a semiconductor integrated circuit device having a field oxide film to be separated, n forming a collector of the bipolar transistor is formed.
At the junction between the + buried layer and the p + buried layer surrounding the n + buried layer, a direction perpendicular to the joint in either one of the n + buried layer and the p + buried layer The concentration gradient of the impurity concentration distribution is formed in two stages of a high concentration distribution and a low concentration distribution, and the region of the low concentration distribution is PN-junctioned with the other buried layer.

Further, the present invention has the same configuration as that of each of the above configurations also in the isoplanar type semiconductor integrated circuit device.

Further, the present invention is to mount any one of the above semiconductor integrated circuit devices on a 2-input NAND gate circuit.

Further, in the manufacturing method of the present invention, the first step of forming a thermal oxide film and a nitride film on the thermal oxide film on the silicon substrate, and the n + buried layer should be formed after applying the photoresist. The second step of removing the resist at the location, the third step of ion-implanting an impurity for making the removed region into either the n + buried layer or the p + buried layer, and the same as the above-mentioned impurity And a fourth step of implanting impurities with a concentration lower than the amount of ions implanted in the third step and inclined with respect to the silicon substrate.

Further, in the manufacturing method of the present invention, a first step of forming a thermal oxide film and a nitride film thereon further on a silicon substrate, and an n + buried layer should be formed after applying a photoresist. The second step of removing the resist at the location, the third step of ion-implanting an impurity for making the removed region into either the n + buried layer or the p + buried layer, and the same as the above-mentioned impurity A fourth step of implanting impurities with a concentration lower than the amount of ions implanted in the third step and tilting with respect to the silicon substrate, the remaining resist is removed, and the remaining nitride film is removed. A fifth step of selectively oxidizing the mask to remove the nitride film and implanting boron to form a p + buried layer using the oxide film produced by the selective oxidation as a mask, and the oxide film by wet etching Removed, and then single crystal A sixth step of epitaxially growing a capacitor and a seventh step of forming an n-type area in a region where a bipolar transistor and a p-channel MOS transistor are formed and a p-type area in a region where an n-channel MOS transistor is formed. And forming a field oxide film for separating each of the bipolar transistor, the p-channel MOS transistor and the n-channel MOS transistor, and then forming an n + type region for taking a collector electrode of the bipolar transistor. And the steps of.

[0013]

According to the above structure, the distribution having the lower concentration gradient of the two-stage structure forms the PN junction with the other buried layer, so that the depletion layer of the PN junction extends and the junction is formed. The capacity decreases. This can reduce the parasitic capacitance between the collector of the bipolar transistor and the substrate,
It is possible to achieve high speed and high integration of the semiconductor integrated circuit device.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a sectional structure of an integrated circuit device in which a bipolar transistor, an n-channel MOS transistor and a p-channel MOS transistor are formed on one silicon substrate 1. In the figure, a part of the bipolar transistor is formed in A, a bipolar transistor is formed in B, an n-channel MOS transistor is formed in C, and a p-channel MOS transistor is formed in D.

Then, as shown in FIG.
The concentration gradient of the impurity concentration distribution in the lateral direction of the n + buried layer forming the collectors of the transistors A and B (direction perpendicular to the junction surface between the n + buried layer and the p + buried layer) is high. 2a and a low distribution 2b. By doing so, the low concentration distribution 2b of the two-stage concentration gradient is obtained.
Forms a PN junction with the p + buried layer, the depletion layer of the PN junction extends and the junction capacitance can be reduced. As a result, the parasitic capacitance between the bipolar transistor and the substrate can be reduced, and high-speed operation of the semiconductor integrated circuit device can be realized.

FIG. 3 shows the impurity concentration distributions of the n + buried layer and the p + buried layer formed by the conventional technique by self-aligning the n + buried layer, where n + and p + of high concentration are PN. Since the junction is formed, the depletion layer is short and the junction capacitance is high.

Next, a method of manufacturing the semiconductor integrated circuit device shown in FIGS. 1 and 2 will be described. 4 to 9
Shows cross-sectional views in each typical manufacturing process. In FIG. 4, a thermally oxidized silicon film 18 having a thickness of 10 to 500 nm is formed on a p-type silicon substrate 1 having a specific resistance of about 10 Ω · cm.
And a silicon nitride film 19 having a thickness of 10 to 500 nm is formed.
Next, in FIG. 5, in order to form the n + buried layer, the silicon nitride film in the area where the bipolar transistor and the pMOS transistor are formed is etched by the photoresist technique and the existing dry etching technique, and the remaining photo Using the resist 20 and the silicon nitride film 19 as a mask, n-type impurities such as antimony (Sb) are introduced into the silicon substrate 1 by about 1 to 5 × 10 ¹⁵ cm ² by the ion implantation technique. Then, in FIG. 6, in order to form the impurity concentration distribution of the n + buried layer into a high distribution 2a and a low distribution 2b having a two-stage structure, antimony 10 ¹³ to 10 ¹⁵ are formed by using, for example, a diagonal ion implantation technique. About cm to ² is introduced into the silicon substrate 1 at an angle of 30 to 60 degrees with respect to the substrate 1.

Even if oblique ion implantation cannot be used, the above impurity concentration distribution can be obtained as follows. For example, the resist is removed after the ion implantation shown in FIG. 5, a side spacer of a silicon nitride or silicon oxide film is formed on the edge of the silicon nitride film 19, and the ion implantation is performed. At this time, the former ion implantation is introduced at a low concentration. Subsequently, the photoresist is removed to form the p + buried layer, and selective oxidation is performed using the remaining nitride film as a mask to form a thermal oxide film of 300 to 500 nm. After that, the nitride film is removed and the oxide film selectively oxidized is used as a mask for p
Boron (B), which is a shape impurity, is introduced into the substrate at about 1 to 5 × 10 ¹³ cm ² by an ion implantation technique.

According to the above-mentioned embodiments, since the photoresist of the p + buried layer is not doped with the impurity as a mask, it is suitable for high integration.

Next, in FIG. 7, the oxide film used as the mask for pre-ion implantation is removed by the existing wet etching technique to epitaxially grow a single crystal silicon film having a thickness of 0.5 to 1.5 μm. At this time, bipolar
An n + buried layer 2 is formed in a region where a transistor and a p-channel MOS transistor are formed, and a p + buried layer 3 is formed in other regions.

Then, 10 to 500 is formed on the single crystal silicon.
nm silicon oxide film and silicon nitride film are provided, and the silicon nitride film in the area where the bipolar transistor and the p-channel MOS transistor are formed is etched using the photoresist technology and the dry etching technology to form a photoresist. Using the silicon nitride film as a mask, phosphorus (p) which is an n-type impurity is added in an amount of 1 to 10 × 10.
Ion-implant about ¹² cm ~ ² . Then, after removing the photoresist used for the mask, the remaining silicon nitride film is used as a mask to perform selective oxidation to form a silicon oxide film of 50 to 500 nm. Then, the silicon nitride film is removed,
Boron (B), which is a p-type impurity, is ion-implanted to about 1 to 10 × 10 ¹³ cm ² with the selectively oxidized silicon oxide film as a mask. Here, heat treatment is performed at 1000 ° C. for 1 hour to form an n-type region 4 and a p-type region 5 having an impurity concentration of 10 ¹⁵ to 10 ¹⁷ cm ³ up to a depth of 1 to 2 μm from the surface, The remaining silicon oxide film is removed.

Further, in FIG. 8, in order to electrically isolate the respective elements formed on the single crystal silicon, the silicon oxide film 7 of 100 to 1000 nm is formed between the respective elements by the above-mentioned selective oxidation method. At this time, in order to ensure the electrical isolation of the elements formed in the p-type region 5, a p-type region having a impurity concentration of about 10 ¹⁶ to 10 ¹⁷ cm ³ is formed immediately below the silicon oxide film 7. The shaped region 6 is formed. Next, in order to take out the electrode from the surface of the collector portion of the bipolar transistor, the n + type region 8 is doped with an impurity phosphorus (p) of about 10 ¹⁵ cm to ² by using a photoresist technique and an ion implantation technique. Implantation and heat treatment at 1000 ° C. for 30 minutes are performed so as to be in contact with the n + buried layer.

Next, in FIG. 9, first, a silicon oxide film of 5 to 50 nm is provided by thermal oxidation in order to form the gate oxide film 9 of the MOS transistor. Then, using a chemical vapor deposition technique, polycrystalline silicon is deposited, and an n-type impurity for reducing resistance is introduced. After that, a photoresist is left in a portion to be the gate electrode 10 of the MOS transistor by using the photoresist technique, and the polysilicon is etched by the existing dry etching technique using the photoresist as a mask to obtain the gate electrode 10.

Next, in order to form the source and drain regions of the n-channel MOS transistor, the photoresist on the p-type area 5 where the n-channel MOS transistor is formed is removed by a photoresist technique, and phosphorus (an n-type impurity) is formed. In the p) region, arsenic (As) is ion-implanted to form the n + region 11 by 10 ¹⁴ to 10 ¹⁶ cm ² implantation.

Subsequently, in order to form a bipolar base, the resist in the portion where the base is to be formed is removed by the same method as described above, and boron of 5 to 1 serving as p-type impurities is added.
0 × 10 ¹³ cm- ² Implantation base region 12 is formed. Here, heat treatment is performed at 800 to 1000 ° C. so that the junction depth of the base region is 100 to 500 nm. After that,
The region where the base region contacts the wiring metal film and the p channel M
OS transistor removing the resist on the n-type region 4 formed, boron is a p-type impurity (B) 10 ¹⁵ ~
10 ¹⁶ cm ~ ² implanted p + region 15 forms a.

Further, in order to form a bipolar emitter, 100 to 1000 nm of silicon oxide is deposited by a chemical vapor deposition technique, and a silicon oxide film in a portion where the emitter is formed is opened by a photoresist technique and a dry etching technique. After that, polycrystalline silicon is deposited by the above method to form the emitter region 13. Therefore, phosphorus (p) or arsenic (As), which is an n-type impurity, is ion-implanted into the polycrystalline silicon at 10 ¹⁵ -5. × 10
¹⁶⁶ cm ~ ² implant, junction depth of emitter area is 50 ~ 20
The emitter region 13 is formed by heat treatment at 800 to 1000 ° C. so that the thickness becomes 0 nm. Then, the polycrystalline silicon used for forming the emitter region is processed into a predetermined shape to obtain the emitter polycrystalline silicon electrode 14.

Finally, an interlayer insulating film 16 made of a silicon oxide is formed to provide a wiring metal film, and a connection hole is opened in a portion of each element to be connected to the metal film. Then, a metal film such as aluminum is deposited and processed into a predetermined shape to obtain the metal film 17. Through the manufacturing process as described above, FIG.
Also, the semiconductor integrated circuit device shown in FIG. 2 can be obtained.

FIG. 10 shows another embodiment of the present invention, which is a sectional structure when applied to a p + buried layer. Further, FIG. 11 shows the impurity concentration distribution along the line X′-Y ′ in FIG. 10. As shown in FIG. 11, the impurity concentration distribution in the lateral direction of the p + buried layer forming the collectors of the bipolar transistors A and B (the direction perpendicular to the junction surface between the p + buried layer and the n + buried layer). The concentration gradient of is formed in two steps, that is, the distribution 3a with high concentration and the distribution 3b with low concentration. Even with this configuration, the same effect as that of the above-described embodiment can be obtained.

FIG. 12 shows still another embodiment of the present invention, which is an example applied to an isoplanar type bipolar transistor. Since the field oxide film 7 does not project upward in the isoplanar bipolar transistor, the surface of the semiconductor integrated circuit device can be flattened. In the line segment XY shown in the figure, the impurity concentration distribution is the same as in FIG. 2, and the same effect is obtained.

FIG. 13 shows a typical circuit diagram in which the semiconductor integrated circuit device of the present invention is actually applied.
It is an AND gate circuit. In the figure, M1 and M2 are p
Channel MOS transistors, M3 to M7 are n-channel MOS transistors, and Q1 and Q2 are npn bipolar transistors. The resistance value between the bases of the bipolar transistors Q1 and Q2 and the ground can be changed by a control signal. Thus, the n-channel MOS transistors M5, M6 and M7 are connected. According to this embodiment, the parasitic capacitance Ccs between the collector and the substrate of the bipolar transistor shown in the figure can be reduced. 14
Shows a typical circuit diagram when this embodiment is actually applied and is a differential amplifier circuit.

[0031]

As described above, according to the present invention,
Since the junction capacitance can be reduced in the PN junction formed between n + that constitutes the collector of the bipolar transistor and the p + that surrounds it, the parasitic capacitance between the bipolar collector and the substrate can be reduced. It is possible to achieve high integration as well as high integration of the circuit device.

[Brief description of drawings]

FIG. 1 is a sectional structural view of a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of an impurity concentration distribution along line XY shown in FIG.

FIG. 3 is a schematic view of an impurity concentration distribution according to a conventional technique corresponding to FIG.

FIG. 4 is a sectional structural view of the semiconductor integrated circuit device of the present invention in a manufacturing process.

5 is a sectional structural view of a semiconductor integrated circuit device in a step subsequent to FIG.

6 is a sectional structural view of a semiconductor integrated circuit device in a step subsequent to FIG.

7 is a sectional structural view of a semiconductor integrated circuit device in a step subsequent to FIG.

8 is a sectional structural view of a semiconductor integrated circuit device in the next step of FIG.

9 is a sectional structural view of a semiconductor integrated circuit device in a step subsequent to FIG.

FIG. 10 is a sectional structural view of a semiconductor integrated circuit device according to another embodiment of the present invention.

FIG. 11 is a schematic diagram of an impurity concentration distribution along line X′-Y ′ shown in FIG.

FIG. 12 is a sectional structural view of a semiconductor integrated circuit device according to still another embodiment of the present invention.

FIG. 13 is a 2-input NAND gate circuit diagram to which the semiconductor integrated circuit device of the present invention is applied.

FIG. 14 is a differential amplifier circuit diagram as an application example of FIG. 13.

[Explanation of symbols]

 1 p-type silicon substrate 2 n + buried layer 3 p + buried layer 4 n-type area 5 p-type area 7 silicon oxide film 10 gate electrode 13 emitter polycrystalline silicon electrode 17 metal film

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Atsushi Watanabe 4026 Kuji Town, Hitachi City, Ibaraki Prefecture Hitachi Research Laboratory, Hitachi, Ltd.

Claims (7)

[Claims] 1. A bipolar transistor,
The bipolar transistor is a semiconductor integrated circuit device in which an n + buried layer and an n-type region are further stacked on the substrate and a field oxide film for separating adjacent bipolar transistors is formed. The junction of the n + buried layer forming the collector of the transistor and the p + buried layer surrounding the n + buried layer, said n
The concentration gradient of the impurity concentration distribution in one of the + buried layer and the p + buried layer in the direction orthogonal to the junction in the buried layer is configured in two stages of a high concentration distribution and a low concentration distribution, Further, a semiconductor integrated circuit device characterized in that the region having a low concentration distribution is formed into a PN junction with the other buried layer. 2. A bipolar transistor, an n-channel MOS transistor, and a p-channel MOS transistor, wherein the bipolar transistor has an n + buried layer on a substrate and an n-type region further on the buried layer. The MOS transistor has a p + buried layer on the substrate and a p-type region further stacked thereon, and the p-channel MOS transistor has an n + buried layer on the substrate and an n-type region further stacked thereon. A semiconductor integrated circuit device having a field oxide film for separating a bipolar transistor, an n-channel MOS transistor and a p-channel MOS transistor, respectively, wherein an n + buried layer and a n + buried layer forming a collector of the bipolar transistor are provided. At the junction of the p + buried layer surrounding the layer, said n
The concentration gradient of the impurity concentration distribution in one of the + buried layer and the p + buried layer in the direction orthogonal to the junction in the buried layer is configured in two stages of a high concentration distribution and a low concentration distribution, Further, a semiconductor integrated circuit device characterized in that the region having a low concentration distribution is formed into a PN junction with the other buried layer. 3. A bipolar transistor,
The bipolar transistor is a semiconductor integrated circuit device in which an n + buried layer and an n-type region are further stacked on the substrate, and a field oxide film for separating adjacent bipolar transistors is formed by an isoplanar method. At the junction of the n + buried layer forming the collector of the bipolar transistor and the p + buried layer surrounding the n + buried layer,
The concentration gradient of the impurity concentration distribution in one of the n + buried layer and the p + buried layer in the direction perpendicular to the junction is configured in two steps, a high concentration distribution and a low concentration distribution. Then
Further, a semiconductor integrated circuit device characterized in that the region having a low concentration distribution is formed into a PN junction with the other buried layer. 4. A bipolar transistor, an n-channel MOS transistor, and a p-channel MOS transistor, wherein the bipolar transistor has an n + buried layer on a substrate and an n-type region further stacked on the n + buried layer. The MOS transistor has a p + buried layer on the substrate and a p-type region further stacked thereon, and the p-channel MOS transistor has an n + buried layer on the substrate and an n-type region further stacked thereon. In a semiconductor integrated circuit device having a field oxide film for isolating the bipolar transistor, the n-channel MOS transistor and the p-channel MOS transistor formed by an isoplanar method, an n + buried layer forming a collector of the bipolar transistor and At the junction of the p + buried layer surrounding the n + buried layer, said n
The concentration gradient of the impurity concentration distribution in the direction perpendicular to the junction in either one of the + buried layer and the p + buried layer,
A semiconductor integrated circuit device comprising a two-stage structure of a high-concentration distribution and a low-concentration distribution, and a region of the low-concentration distribution is PN-junctioned with the other buried layer. 5. A two-input NAND gate circuit equipped with the semiconductor integrated circuit device according to claim 1. 6. A first step of forming a thermal oxide film on a silicon substrate and a nitride film thereon, and a step of removing a resist at a portion where an n + buried layer is to be formed after applying a photoresist. 2 step, a third step of ion-implanting an impurity for making the removed region into either an n + buried layer or a p + buried layer, and the same impurity as the third step 4. A method for manufacturing a semiconductor integrated circuit device, which comprises a fourth step of implanting ions at a concentration lower than the amount of implanted ions in step 4 and tilting with respect to the silicon substrate. 7. A first step of forming a thermal oxide film on a silicon substrate and a nitride film thereon, and a step of removing a resist at a portion where an n + buried layer is to be formed after applying a photoresist. 2 step, a third step of ion-implanting an impurity for making the removed region into either an n + buried layer or a p + buried layer, and the same impurity as the third step The fourth step of implanting ions at a concentration lower than the amount of ion implantation in step S10 and tilting with respect to the silicon substrate, removing the remaining resist, and further nitriding by selectively oxidizing the remaining nitride film with a mask. The fifth step is to remove the film and to implant boron to form the p + buried layer using the oxide film produced by selective oxidation as a mask, and the oxide film is removed by wet etching, and then the single crystal silicon is used. Epitaxially grown A sixth step of forming a bipolar transistor and a p-channel MOS transistor in a region where an n-channel MOS transistor is formed, and a seventh step of forming a p-type region in a region in which an n-channel MOS transistor is formed. Bipolar transistor, p
Channel MOS transistor and n-channel MO
8. A method of manufacturing a semiconductor integrated circuit device, comprising: an eighth step of forming a field oxide film for separating each S transistor, and then forming an n + type region for taking a collector electrode of the bipolar transistor.