JPH0766213A - Semiconductor device - Google Patents

Abstract

PURPOSE:To improve the performance, in particular the operation speed, of a lateral bipolar transistor formed on a SOI substrate by forming an intrinsic base region and an emitter region in self-alignment by an impurity introduced from an emitter opening. CONSTITUTION:A bottom and a side are formed in an insular semiconductor region 302 surrounded by insulation films 301, 303, and at last one end of the junction plane between first conductive regions 306, 308 and a second conductive region 307 is terminated by the bottom insulation film 301. In such a lateral bipolar transistor, an intrinsic base region 307 and an emitter region 306 are formed in self-alignment by an impurity introduced from an emitter opening 304. For example, single crystal silicon region immediately under the emitter opening 304 is etched, and an arsenic-containing polycrystalline silicon 305 is deposited, and then heat-treated to diffuse arsenic laterally from the polycrystalline silicon 305, resulting in an n<+> diffused region 306.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to the structure of a bipolar transistor formed on an insulating substrate.

[0002]

2. Description of the Related Art In recent years, a substrate (SOI Silicon On Insul) in which a thin film silicon region is provided on an insulating substrate.
Active research and development is being carried out on a technology (SOI technology) for forming a semiconductor element in a thin film silicon region of an (ator substrate). In particular, when a MOS transistor is formed on an SOI substrate, when it is formed on a silicon substrate, it has better radiation resistance than when it is formed on a silicon substrate, it has a small parasitic capacitance, and it is easy to separate elements that prevent latch-up. There are many known advantages.
Above all, the thickness of the thin film silicon region of the SOI substrate is 0.1 μm.
In addition to the above advantages, the fully depleted MOS transistor made to have a thickness of about m to completely deplete the thin film silicon region has a large carrier mobility and a large mutual conductance, which can reduce the substrate floating effect and the short channel effect. It is known that there are many advantages such as the difficulty of occurrence (for example, the Institute of Electronics, Information and Communication Engineers research report SDM
90-136 pp. 29-36) It is indispensable to completely deplete MOS transistors when using SOI technology. On the other hand, in a current semiconductor device formed on a silicon substrate, a BiCMOS circuit in which a bipolar transistor and a MOS transistor are mounted together has been widely used in order to improve load driving capability of a CMOS circuit, speed up, and airtightness. , MO even when using SOI substrate
It is necessary to develop a bipolar transistor that can be mounted together with an S transistor. However, 0.1
Since it is very difficult to make a vertical bipolar transistor widely used today in a thin film silicon region of about μm, making a lateral bipolar transistor has been studied and some reports have been made. (For example, IEE Electron Device Letters IEEE ELECTRON DEVICE
LETTERS VOL. EDL-8 No. 3 M
ARCH 1987 p. p. 104-106) This lateral bipolar transistor and MOS transistor are
By mounting it on the I substrate, B on the conventional silicon substrate
Although it has an advantage that the manufacturing process can be greatly simplified as compared with the case of forming an iCMOS circuit, it is much inferior to the vertical bipolar transistor in the performance of the bipolar transistor itself, especially in the operating speed. There is a problem in performance as a semiconductor device, particularly in operating speed.

A cross section of an example of a conventional lateral bipolar transistor formed in a silicon region on this insulating substrate is shown in FIG.
Shown in. An island-shaped single crystal silicon region is formed over an insulating substrate 401. The single crystal silicon region 402 is composed of a P ⁺ diffusion region 403, a P diffusion region 404, and n ⁺ diffusion regions 405 and 406 due to the introduced impurities. The P ⁺ diffusion region 403 is connected to the base electrode 407, and the n ⁺ diffusion region 405 is the emitter electrode 408.
And the n ⁺ diffusion region 406 is connected to the collector electrode 40.
9 is connected.

Next, process cross-sectional views showing a method of manufacturing this conventional bipolar transistor are shown in FIGS.
It shows in (c).

As shown in FIG. 5A, first, a P-type impurity such as boron is further ion-implanted in a single crystal silicon region on an insulating substrate into which a P-type impurity such as boron is introduced at about 1 × 10 ¹⁶ cm ^-3. About 1 × 10 ²⁰ cm ^{−3 is} introduced by the injection method. Next, using a photolithography technique and an etching technique, a single crystal silicon region 502 having a desired pattern is formed.
To form. Further, a silicon oxide film 503 is deposited by using a technique such as a chemical vapor deposition method (hereinafter abbreviated as a CVD method), and then a photoresist 504 having a desired pattern is formed by using a photolithography technique.

Subsequently, as shown in FIG. 5B, etching is performed using the photoresist 504 as a mask to pattern the silicon oxide film 503 and at the same time etch a part of the single crystal silicon region. Then, n such as phosphorus or arsenic is etched. A type impurity is introduced by an ion implantation method at about 1 × 10 ²⁰ cm ⁻³ .

After that, as shown in FIG. 5C, after removing the photoresist, a silicon oxide film 505 is deposited by the CVD method and the base opening 506 and the emitter opening are formed by the photolithography technique. 507 and a collector opening 508 are formed, and then polycrystalline silicon is deposited by using the CVD method, and the base electrode 509, the emitter electrode 510 and the collector electrode 511 are formed by the photolithography technique.

[0008]

In this conventional semiconductor device, the width of the P diffusion region serving as the intrinsic base region depends on the photolithography technique. Therefore, there is a problem in that the width of the intrinsic base region cannot be made narrower than the minimum width of the photoresist that can be patterned by the photolithography technique. As is well known, in order to speed up the transistor operation, it is necessary to narrow the width of the intrinsic base region, so the above problem has been a major obstacle to speeding up the semiconductor device.

[0009]

The semiconductor device of the present invention comprises:
A lateral type in which a bottom surface and a side surface are formed in an island-shaped semiconductor region surrounded by an insulating film, and at least one end of a bonding surface between the first conductivity type region and the second conductivity type region is terminated by the bottom surface insulating film. The bipolar transistor is characterized in that the intrinsic base region and the emitter region are formed in a self-aligned manner by the impurities introduced from the emitter opening.

[0010]

The present invention will be described below with reference to the drawings. FIG. 1 is a sectional view of an essential part of a semiconductor device according to an embodiment of the present invention. An island-shaped single crystal silicon region 102 is formed on an insulating substrate 101, and the single crystal silicon region 102 includes an n diffusion region 103, a P ⁺ diffusion region 104, an n ⁺ diffusion region 105, and a P diffusion region 106. The P ⁺ diffusion region 104 and the n ⁺ diffusion region 105 serve as the emitter opening 10.
It is characterized in that it is formed in a self-aligned manner by introducing impurities from 7. 2A to 2F are process cross-sectional views showing the method for manufacturing the semiconductor device of this embodiment.
First, as shown in FIG. 2A, a portion of the single crystal silicon region 202 is covered with a photoresist 203 using a photolithography technique, and phosphorus is ion-implanted to 1 × 1.
0 is introduced approximately ¹⁷ cm ^-3 to form an n-diffusion region 204, the photoresist is removed 203. Next, as shown in FIG. 2B, the n diffusion region 204 of the single crystal silicon region 202 is covered with a photoresist 206, and boron is introduced at about 1 × 10 ¹⁹ cm ⁻³ by an ion implantation method to perform P diffusion. Area 20
5 is formed, and the photoresist 206 is peeled off. The regions covered with the photoresist 203 and the photoresist 206 are overlapped with each other by about 0.5 to 1.5 μm so that the n diffusion region 204 and the P diffusion region 205 formed by the ion implantation method are not in contact with each other. , Prevents the breakdown voltage from decreasing. Further, as shown in FIG. 2C, a silicon oxide film 207 is deposited by using the CVD method, and an emitter opening 209 is formed by using the photolithography and etching technique, and then boron is added by ion implantation. × 10 ¹⁸ c
Introduce about m ⁻³ and peel off the photoresist 208 to 900
A heat treatment is performed at 20 ° C. for about 20 to 30 minutes to diffuse boron and form a P ⁺ diffusion region 210. Next, FIG. 2 (d)
As shown in Fig. 1, arsenic was added to 1 × 10 ²¹ c by the ion implantation method.
About n ^{−3 is} introduced to form the n ⁺ diffusion region 211. Further, a collector opening 212 and a base opening 213 are provided by using photolithography and etching techniques to remove the photoresist 214. Finally, polycrystal silicon is deposited by using the CVD method, and the polycrystal silicon is patterned by photolithography and etching techniques to form a collector electrode 215 and an emitter electrode 217. By using the above method, the width of the intrinsic base region can be set to about 500 to 1000 angstrom without depending on the lithography technique.

Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 3 is a sectional view of the essential parts of the second embodiment of the present invention. P in the same manner as in FIGS.
After forming the ⁺ diffusion region, the single crystal silicon region immediately below the emitter opening 304 is etched to remove arsenic at 1 × 10.
It is made by depositing polycrystalline silicon 305 containing about ²¹ cm ^−3, and the n ⁺ diffusion region 306 is formed by arsenic diffused from the polycrystalline silicon 305 by heat treatment at 900 ° C. for about 10 to 20 minutes. . In the second embodiment, arsenic is laterally diffused from the polycrystalline silicon 305 to form the n ⁺ diffusion region 306.
^The P diffusion region (intrinsic base region) 30 having excellent uniformity in the ⁺ diffusion region 306 and having a narrow width and excellent withstand voltage
It also has the advantage that 7 can be formed.

[0012]

As described above, according to the present invention, the bottom surface and the side surface are formed in the island-shaped semiconductor region surrounded by the insulating film, and the junction surface between the first conductivity type region and the second conductivity type region is formed. In the lateral bipolar transistor whose at least one end is terminated by the bottom surface insulating film, the intrinsic base region and the emitter region are formed in a self-aligned manner by the impurities introduced from the emitter opening. 500-100 without depending
The width can be narrowed to about 0 angstrom, and the transistor operation can be speeded up.

Further, as a method of introducing impurities from the emitter opening, a method of diffusing from polycrystalline silicon deposited in the emitter opening is adopted, whereby an intrinsic base region having a narrow width and excellent withstand voltage can be formed. did it.

[Brief description of drawings]

FIG. 1 is a sectional view of an essential part of an embodiment of the present invention.

2A to 2F are process sectional views showing a manufacturing method of the embodiment shown in FIG.

FIG. 3 is a sectional view of a main portion of a second embodiment of the present invention.

FIG. 4 is a sectional view of a conventional main part.

5A to 5C are process cross-sectional views showing a manufacturing method of the conventional example shown in FIG.

[Explanation of symbols]

101, 201, 301, 401, 501 Insulating substrate 102, 202, 302, 402, 502 Single crystal silicon region 103, 204, 308 n Diffusion region 104, 210, 307, 403 P ⁺ diffusion region 105, 211, 306, 405 , 406 n ⁺ diffusion region 106, 205, 309, 404 P diffusion region 107, 209, 304, 507 Emitter opening 108, 207, 303, 503, 505 Silicon oxide film 109, 215, 409, 511 Collector electrode 110, 216 , 408, 510 emitter electrode 111, 217, 407, 509 base electrode 203, 206, 208, 214, 504 photoresist 212, 508 collector opening 213, 506 base opening 305 polycrystalline silicon

Claims (1)

[Claims] 1. A bottom surface and a side surface are formed in an island-shaped semiconductor region surrounded by an insulating film, and at least one end of a bonding surface between a first conductivity type region and a second conductivity type region is a bottom insulating film. In the terminated lateral bipolar transistor,
A semiconductor device, wherein an intrinsic base region and an emitter region are formed in a self-aligned manner by impurities introduced from an emitter opening.