KR910009740B1 - Manufacturing method of self-aligned bipolar transistor using oxide film - Google Patents

Abstract

The method for making the self-aligned bipolar transistor, including a first conductive type semiconductor substrate (31) and a second conductive type collector region (34) formed on substrate and an active region (30a,30b) isolated by field oxide (35), comprises the steps of; (a) forming an implanted region of first conductive type in active region (30a); (b) depositing the nitride film (39) all over the substrate, followed by patterning the nitride film (39) to open a part of active region; (c) forming a thick oxide film (41) on substrate and etching the entire substrate surface to remain a part of oxide film (41a).

Description

Method of manufacturing self-matched bipolar transistor using oxide film

1 is a cross-sectional view of a conventional self-matched bipolar transistor.

Figure 2a-j is a process chart of the self-aligned NPN transistor according to the present invention.

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a self-aligned bipolar transistor. To improve the operation speed and noise immunity of the general bipolar transistor, the resistance of the base region Rb should be reduced. In a conventional bipolar transistor, the base resistance Rb is the resistance R1 of the active base region (Active Base or Intrinsic Base Region) below the emitter region, the edge portion of the emitter region and the bulk base region (Bulk Base Region or Extrinsic Base). Resistance R2 of the bulk base region from the contact region outside the region).

Since the area of the resistor R1 or the active base region is closely related to the characteristics of the transistor such as a cutoff frequency or a gain, the resistor R1 is difficult to change.

Conventionally, when a high concentration of impurities are diffused into the bulk base region to reduce the resistance of the base region, the base region is divided into a low concentration region a, an active base region under the emitter region, and a bulk base region b, a high concentration impurity diffusion layer, and a region a. The resistance of the resistor R1 is a high resistance resistor, and the resistance of the region b is a low resistance resistor R2.

This reduces the resistance R2, which reduces the total base resistance Rb, which is the sum of the resistors R1 and R2 connected in series.

As described above, when the regions a and b are formed, a second ion implantation process is mainly used. In this case, the region b is preferably as close to the emitter region as possible without emitter degeneration. If the region b moves away from the emitter region, the region a of high resistance expands to increase the resistance R1, and if the region b of high concentration approaches and overlaps the high concentration emitter region of the opposite conductivity type, it degenerates and leaks. It becomes larger and worsens.

In order to make the bulk base region as close to the emitter region as possible, degeneracy does not occur and the base resistance Rb is reduced. FIG. 1 shows a cross-sectional view of an NPN transistor using a conventional self-matching scheme.

Referring to FIG. 1, an n-type silicon epitaxial layer 11 is formed on a p-type silicon substrate 10 to form a high concentration N + buried layer 12 between the epitaxial layer 11 and the substrate 10. ) Is formed.

The other element region and the field oxide film 14 are spaced apart, and the emitter and base region are spaced apart from the collector region and the field oxide film 14.

There is also a P-active base region 18 surrounded by a P + bulk base 16 region and a high concentration N + emitter region 20 in the active base. This N + emitter region 20 is formed by diffusion by the doped polycrystalline silicon 22a used for internal connection.

In addition, the polycrystalline silicon 22b is formed on the N + sink region 13 connected to the N + buried layer 12, and the emitter electrode 26 is connected to the polycrystalline silicon 22a region on the substrate covered with the insulating film 24. The collector electrode 28 is formed such that the base electrode 27 is connected to the P + bulk base region and the polycrystalline silicon 22b region is connected.

As shown in the figure, the junction is formed by contacting the shallow junction emitter 20 and the P + bulk base region 16 formed by using the polycrystalline silicon 22a as an interconnection. This results in a decrease in junction breakdown voltage and a junction leakage current between the emitter and the base caused by the contact of the high concentration layer.

In addition, since the emitter is formed by the internal connection of polycrystalline silicon, the thin oxide film that may exist between the polycrystalline silicon and the silicon makes it difficult to control the DC current amplification factor hFE, and the use of polycrystalline silicon makes the process complicated and unstable.

Accordingly, it is an object of the present invention to provide a bipolar transistor manufacturing method which prevents the breakdown voltage between the emitter and the base, reduces the leakage current, and simultaneously self-matches the emitter and the base in a simple process.

Hereinafter, with reference to the accompanying drawings of the present invention will be described in detail.

2A-J show cross-sectional views of the manufacturing process of the NPN transistor according to the present invention in order.

The starting material is a p-type silicon wafer having a specific resistance of 15-20 Ω · cm and having a crystal structure of <100>.

First, referring to FIG. 2A, a pattern for forming an investment layer is formed on the substrate 31 by a normal oxidation process and a photolithographic process, and a high concentration of arsenic ions is diffused to form an N + investment layer 32. Form an N-type epitaxial layer 33 by a conventional liquid phase epitaxy method or a vapor phase epitaxy method, Phosphorus is diffused to form an N + collector 34, and then a nitride film is deposited on the entire upper surface of the substrate, and the nitride film in the region except for the active regions 30a and 30b is removed to perform an oxidation process. ) And the nitride film on the active regions 30a and 30b is removed.

Then, a photoresist pattern 37 is formed by a conventional photolithography to form a thin oxide layer 36 on the substrate and form a first interinsic base region. As the ion implantation mask, boron ions are implanted with a 3 × 10 ¹³ ions / cm 2 -7 × 10 ¹³ ions / cm 2 dose to form the first p-type ion implantation region 38, as shown in FIG. 2b.

Then, the photoresist pattern 37 on the substrate is removed, and the nitride film 39 of Si ₃ N ₄ is deposited on the front surface of the substrate to a thickness of 1500 to 2000 microseconds, as shown in FIG. 2C. Then, in order to form the emitter region on the nitride film 39, the photoresist pattern 40 is formed by a general photolithography process, except for the portion where the emitter region is to be formed using the photoresist pattern 40 as an etching mask. The nitride film 39 and the oxide film 36 of the active region 30a are etched as shown in FIG. 2D. Then, the photoresist pattern 40 on the substrate is removed, and the SiO ₂ oxide film 41 is deposited on the entire surface of the substrate to a thickness of 5000 to 8000 Pa.

Then, by etching a 500-1000 공정 oxide layer on the nitride film 39 by a conventional etch back process, and then to form a second base (Extrinsic base) 1 × 10 ¹⁵ -3 × 10 ¹⁵ ions / The second p-type ion implantation region 42 is formed by implanting boron ions into a cm 2 dose, as shown in FIG. 2f.

At this time, when the oxide film of about 500-1000Å is left on the nitride film 39 on the emitter region, an oxide spacer 41a is formed on the sidewall of the nitride film 39, which masks the ion implantation of the second base. Self-align with emitter

Then, the oxide film is etched at 3000-4000Å to remove all the oxide film remaining on the substrate, and then heat-treated to activate the first and second p-type ion implantation regions 38 and 45 to activate the first and second base regions 43. A 44 is formed, and an oxide film 45 of about 2000-2500 kV is formed on the exposed second base region 44 as shown in FIG. 2G.

Then, the nitride film 39 on the substrate is removed to form an emitter region, and arsenic ions are implanted with a dose of 4 × 10 ¹⁵ -9 × 10 ¹⁵ ions / cm 2 to form n-type ions on the surface of the first base 43. The injection region 46 is formed as shown in FIG. 2H. Subsequently, when the oxide film 47 of SiO ₂ is deposited on the substrate to a thickness of 2000-3000 Å, the n-type ion implantation region 46 is activated to form an N + emitter region 49 as shown in FIG. 2i.

Then, a contact is formed to form an emitter, a base, and a collector electrode by a conventional photolithography process, and a TiN film 49 and a metal layer 50 are simultaneously deposited on the substrate, and the emitter is fabricated by a conventional photolithography process. After the electrode 51, the base electrode 52, and the collector electrode 53 are formed and an alloy process is performed, an NPN transistor is formed as shown in FIG. 2j.

The region 60 in FIG. 9j is an oxide region in which the oxide films 35, 45 and 47 of FIG. 2i are combined.

In this step, the TiN film is formed to prevent the diffusion of the metal layer into the emitter and the base region forming the shallow junction to lower the spike phenomenon or the breakdown voltage. The TiN film may be formed using a conventional silicide film.

In the above description of the NPN transistor as an embodiment, it can be easily understood by those of ordinary skill in the art that the present invention can be formed differently without departing from the spirit of the present invention.

As described above, the present invention simultaneously self-aligns the emitter and the base of the transistor using an oxide spacer to prevent a short circuit between the two areas when a high emitter region and a high concentration second base region are formed. It can reduce leakage current, prevent breakdown, and reduce device size. In addition, the present invention reduces the contact resistance, prevents metal spikes, and reduces the second base-mask layer by using the TiN film at the interface between the silicon substrate and the metal.

Claims (3)

A semiconductor substrate 31 of a first conductivity type, a collector region of a high concentration second conductivity type formed on the substrate 31, and an active spaced apart from the collector region 34 and the field oxide film 35 on the substrate; A method of manufacturing a bipolar transistor, characterized in that the semiconductor device having the regions (30a) (30b) and the manufacturing method comprise the following steps and are successive of the following steps. (a) forming a first ion implantation region (38) of a first conductivity type in an active region (30a) on the substrate (31). (b) depositing a nitride film (39) on the entire upper surface of the substrate and patterning the nitride film (39) such that a predetermined portion of the active step (30a) is exposed. (c) forming a thick oxide film 41 on the substrate and etching a portion of the oxide film 41 to etch the entire surface of the substrate so that the oxide film 41a having a predetermined thickness remains on the top and side surfaces of the nitride film 39. fair. (d) Ion implantation of the second conductivity type using the oxide film 41a and the nitride film 39 on the substrate as an ion implantation mask to form the second ion implantation region 42 of the first conductivity type in the active region 30a. Forming process. (e) heat treatment to remove the oxide film (41a) remaining on the top and side surfaces of the nitride film (39) and to activate the first and second ion implantation regions. (f) removing the nitride film (39) and implanting a second conductive ion into the entire surface of the substrate to form a second conductive ion implanted region (46). (g) forming a thick oxide film (47) on the substrate and simultaneously activating an ion implantation region (46) in the first conductivity type. (h) forming a connection window on the emitter, base and collector regions on the substrate. (i) forming emitter, base and collector electrodes (51, 52, 53) on the substrate; A method of manufacturing a bipolar transistor according to claim 1, wherein the step (c) leaves 2000-4000 kV oxide film on the top and side surfaces of the nitride film (39). A method of manufacturing a bipolar transistor according to claim 1, wherein a TiN film is deposited on the substrate after step (h).

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