KR0172509B1 - Method of fabricating lateral bipolar transistor - Google Patents
Method of fabricating lateral bipolar transistor Download PDFInfo
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- KR0172509B1 KR0172509B1 KR1019950018278A KR19950018278A KR0172509B1 KR 0172509 B1 KR0172509 B1 KR 0172509B1 KR 1019950018278 A KR1019950018278 A KR 1019950018278A KR 19950018278 A KR19950018278 A KR 19950018278A KR 0172509 B1 KR0172509 B1 KR 0172509B1
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- 238000004519 manufacturing process Methods 0.000 title claims description 16
- 239000012535 impurity Substances 0.000 claims abstract description 30
- 125000006850 spacer group Chemical group 0.000 claims abstract description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 13
- 229920005591 polysilicon Polymers 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 238000005530 etching Methods 0.000 claims abstract description 6
- 238000000137 annealing Methods 0.000 claims abstract description 3
- 150000004767 nitrides Chemical group 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/6625—Lateral transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/735—Lateral transistors
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Bipolar Transistors (AREA)
Abstract
본 발명은 기판(1)상 예정된 부위에 저농도 도핑영역(3)을 형성하는 제1단계; 상기 저농도 도핑영역에 도핑된 불순물과 동일한 형태의 불순물을 고농도로 도핑한 제1폴리실리콘층(4)을 전체구조 상에 형성하는 제2단계; 상기 제1폴리실리콘층 상에 제1절연층(5)을 형성한 후, 에미터 및 컬렉터로 예정된 영역의 상기 제1절연층 및 제1폴리실리콘층을 제거하는 제3단계; 전체구조 표면에 제2절연층(6)을 형성한 후, 식각공정을 수행하여 베이스가 형성될 부위의 상기 제1절연층 및 제1폴리실리콘층의 측벽에 상기 제2절연층을 남기는 제4단계; 어닐링 공정을 수행하여 상기 제1폴리실리콘층에 도핑된 불순물을 상기 저농도 도핑영역으로 확산시킨 후, 컬렉터로 동작할 영역에 잔류한 상기 제2절연층의 측벽에 제3절연층 스페이서(7)를 형성하는 제5단계; 및 상기 기판의 노출된 부위에 상기 저농도 도핑영역에 도핑된 불순물과 다른 형태의 불순물을 이온주입하여 베이스 영역을 형성하는 제6단계를 포함하는 것을 특징으로 하는 수평 구조의 바이폴라 트랜지스터 제조 방법에 관한 것으로, 수평 구조를 가지는 바이폴라 트랜지스터를 제조할 수 있게 되며, 스페이서를 이용하여 베이스의 폭을 정밀하게 조절할 수 있도록 한 것이다.The present invention comprises a first step of forming a lightly doped region (3) in a predetermined region on the substrate (1); A second step of forming a first polysilicon layer (4) having a high concentration of impurities of the same type as the impurities doped in the lightly doped region on the entire structure; A third step of forming a first insulating layer (5) on the first polysilicon layer and then removing the first insulating layer and the first polysilicon layer in regions designated as emitters and collectors; After forming the second insulating layer 6 on the surface of the entire structure, and performing a etching process to leave the second insulating layer on the sidewalls of the first insulating layer and the first polysilicon layer of the portion where the base is to be formed step; After performing an annealing process to diffuse the doped impurities in the first polysilicon layer into the low concentration doped region, and then to the third insulating layer spacer 7 on the sidewalls of the second insulating layer remaining in the region to act as a collector Forming a fifth step; And a sixth step of forming a base region by ion implanting impurities of a different type from impurities doped in the lightly doped region into the exposed portion of the substrate. In addition, the bipolar transistor having a horizontal structure can be manufactured, and the width of the base can be precisely adjusted by using a spacer.
Description
제1a도 내지 제1f도는 본 발명의 일 실시예에 따른 수평 구조의 바이폴라 트랜지스터 제조 공정도.1A to 1F are a bipolar transistor manufacturing process diagram of a horizontal structure according to an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 기판 2 : 필드산화층1 substrate 2 field oxide layer
3 : n-도핑영역 4 : 폴리실리콘층3: n - doped region 4: polysilicon layer
5 : 질화층 6 : 산화층5: nitride layer 6: oxide layer
7 : 산화층 스페이서7: oxide layer spacer
본 발명은 반도체 제조 분야에 관한 것으로, 특히 바이씨모스(BiCMOS) 회로 등에 적용되는 수평 구조의 바이폴라 트랜지스터(lateral bipolar transistor) 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of semiconductor manufacturing, and more particularly, to a method of manufacturing a lateral bipolar transistor having a horizontal structure applied to a BiCMOS circuit and the like.
일반적으로, 바이폴라 트랜지스터는 수직 구조로 제조되었다. 이러한 구조, 즉, 바이폴라 트랜지스터를 이루는 에미터, 베이스, 콜렉터를 수직 구조로 형성하는 것은 제조 공정이 복잡함에도 불구하고 바이폴라 트랜지스터의 특성을 결정하는 중요한 요소 중에 하나인 베이스의 폭을 조절하기가 쉬운 장점이 있다.In general, bipolar transistors are manufactured in a vertical structure. This structure, that is, the vertical structure of the emitter, base and collector constituting the bipolar transistor, is easy to adjust the width of the base, which is one of the important factors that determine the characteristics of the bipolar transistor despite the complicated manufacturing process There is this.
한편, SOI(Semiconductor On Insulator) 구조에 대한 연구가 진행됨에 따라 SOI 구조의 장점 때문에 SOI를 이용한 바이씨모스(BiCMOS) 회로 구성에 관심이 높아지고 있다. 그런데 SOI 구조에서는 그 구조의 특성상 수직형의 바이폴라 트랜지스터를 형성하기가 매우 어렵기 때문에 수평 형태로 제조되어야 하며, 이를 구현하기 위한 방법이 요구되기에 이르렀다. 바이폴라 트랜지스터의 특성 향상을 위해서 베이스의 폭은 적어도 0.1㎛ 이하로 조절되어야 하기 때문에 베이스의 폭을 정밀하게 조절할 수 있는 제조 방법이 요구된다.On the other hand, as research on the structure of the SOI (Semiconductor On Insulator) is in progress, the interest in the configuration of the BiCMOS (BiCMOS) circuit using the SOI is increasing because of the advantages of the SOI structure. However, in the SOI structure, since it is very difficult to form a vertical bipolar transistor due to the characteristics of the structure, it has to be manufactured in a horizontal form, and a method for realizing it has been required. In order to improve the characteristics of the bipolar transistor, the width of the base should be adjusted to at least 0.1 μm or less, so a manufacturing method capable of precisely adjusting the width of the base is required.
따라서, 본 발명은 수평 구조를 가지더라도 베이스의 폭을 정밀하게 조절할 수 있는 수평 구조의 바이폴라 트랜지스터 제조 방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method of manufacturing a bipolar transistor having a horizontal structure that can precisely adjust the width of a base even if it has a horizontal structure.
상기 목적을 달성하기 위하여 본 발명은, 바이폴라 트랜지스터 제조 방법에 있어서 반도체 기판의 예정된 부위에 저농도의 제1도전형 불순물 영역을 형성하는 제1단계; 제1단계 수행후, 전체구조 상부에 상기 저농도의 제1도전형 불순물 영역에 고농도의 제1도전형 불순물이 도핑된 전도층을 형성하는 제2단계; 상기 전도층 상에 절연층을 형성하는 제3단계; 상기 절연층 및 상기 전도층을 선택식각하여 적어도 예정된 베이스 영역을 노출시키는 제4단계;In order to achieve the above object, the present invention provides a bipolar transistor manufacturing method comprising: a first step of forming a low concentration of a first conductivity type impurity region in a predetermined portion of a semiconductor substrate; A second step of forming a conductive layer doped with a high concentration of the first conductivity type impurity in the low concentration first conductivity type impurity region after performing the first step; A third step of forming an insulating layer on the conductive layer; Selectively etching the insulating layer and the conductive layer to expose at least a predetermined base region;
적어도 노출된 상기 전도층의 측벽 부분을 덮는 제1스페이서 절연층을 형성하는 제5단계; 예정된 콜렉터 영역의 상기 제1스페이서 절연층의 측벽에 제2스페이서 절연층을 형성하는 제6단계; 및 노출된 상기 저농도의 제1도전형 불순물 영역에 제2도전형 불순물을 이온주입하여 베이스를 형성하는 제7단계를 포함한다.A fifth step of forming a first spacer insulating layer covering at least a portion of the sidewall of the exposed conductive layer; Forming a second spacer insulating layer on a sidewall of the first spacer insulating layer in a predetermined collector region; And a seventh step of forming a base by ion implanting a second conductive impurity into the exposed first conductive impurity region having a low concentration.
이하, 첨부된 도면 제1a도 내지 제1f도를 참조하여 본 발명의 바람직한 실시예를 설명한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings 1A to 1F.
먼저, 제1a도에 도시된 바와 같이 기판(1) 상에 LOCOS(LOCal Oxidation of Silicon) 공정으로 소자 분리층인 필드산화층(2)을 형성한 후, 기판(1)의 활성 영역 부위에 이온주입법으로 n-도핑영역(3)을 형성한다.First, as shown in FIG. 1A, a field oxide layer 2, a device isolation layer, is formed on a substrate 1 by a LOCOS (LOCal Oxidation of Silicon) process, and then ion implantation is performed on an active region of the substrate 1. N - doped region 3 is formed.
이어서, 제1b도에 도시된 바와 같이 전체구조 상에 N형 불순물이 고농도로 도핑된 폴리실리콘층(4), 절연층인 질화층(SiN, 5)을 증착한 후, 질화층(5) 및 폴리실리콘층(4)을 선택식각하여 베이스가 형성될 영역의 n-도핑영역(3)을 노출시킨다. 이때, 선택식각시 노출되는 영역의 폭은 이후의 공정을 위해 일정 마진(margin)을 갖도록 한다.Subsequently, as shown in FIG. 1B, a polysilicon layer 4 doped with N-type impurities at high concentration and a nitride layer (SiN, 5) as an insulating layer are deposited on the entire structure, and then the nitride layer 5 and The polysilicon layer 4 is selectively etched to expose the n − doped region 3 of the region where the base is to be formed. In this case, the width of the region exposed during the selective etching may have a certain margin for the subsequent process.
계속해서, 제1c도에 도시된 바와 같이 전체구조 표면에 얇은 산화층을 증착한후, 식각공정을 수행하여 베이스가 형성될 부위의 질화층(5) 및 폴리실리콘층(4)의 측벽에 산화층(6)을 남기고, 어닐링(annealing) 공정을 수행하여 폴리실리콘층(4)에 고농도로 도핑된 불순물이 n-도핑영역(3) 내로 확산되도록 한다. 이에 따라, n-도핑영역(3)에 이후 에미터 및 콜렉터로 동작하게 될 n+도핑영역이 형성된다.Subsequently, as shown in FIG. 1C, a thin oxide layer is deposited on the surface of the entire structure, followed by etching to form sidewalls of the nitride layer 5 and the polysilicon layer 4 at the portion where the base is to be formed. 6) is left, and an annealing process is performed so that impurities heavily doped in the polysilicon layer 4 are diffused into the n − doped region 3. Thus, n - a n + doped regions will operate as an emitter and a collector since the doped region 3 is formed.
다음으로, 제1d도는 잔류한 산화층(6)의 측벽에 산화층 스페이서(7)를 형성한후, 사진 및 식각공정을 실시하여 에미터측의 산화층 스페이서(7)를 선택적으로 제거한 상태를 나타낸 것이다. 즉, 콜렉터 영역의 산화층 스페이서(7)만을 잔류시킨다.Next, FIG. 1D illustrates a state in which the oxide layer spacer 7 is formed on the sidewall of the remaining oxide layer 6, and then the oxide layer spacer 7 on the emitter side is selectively removed by performing photographic and etching processes. That is, only the oxide layer spacer 7 in the collector region is left.
이어서, 제1e도에 도시된 바와 같이 노출된 n-도핑영역(3)에 p형 불순물(예를 들어, 보론)을 이온주입하여 p+도핑영역(이후 베이스로 동작)을 형성한다.Subsequently, p-type impurities (eg, boron) are ion-implanted into the exposed n − doped region 3 as shown in FIG. 1e to form a p + doped region (hereafter acting as a base).
계속해서, 제1f도에 도시된 바와 같이 전체구조 상에 p형 불순물이 고농도로 도핑된 폴리실리콘층(8)을 형성한 후, 폴리실리콘층(8)을 패터닝하여 베이스 콘택을 형성한다.Subsequently, as shown in FIG. 1f, after forming the polysilicon layer 8 doped with a high concentration of p-type impurities on the entire structure, the polysilicon layer 8 is patterned to form a base contact.
이후, 금속화(metallization) 공정을 수행하기 위하여 전체구조 상부에 절연층을 형성한다.Thereafter, an insulating layer is formed on the entire structure in order to perform a metallization process.
참고적으로, 이러한 공정은 SOI 구조의 소자를 제조하는데 이용할 수 있으며, 한편 질화층(5) 및 산화층(6, 7)을 다른 절연층으로 대체하는 것이 가능함은 당연하다.For reference, such a process can be used to fabricate a device having an SOI structure, while it is natural that the nitride layer 5 and the oxide layers 6 and 7 can be replaced with other insulating layers.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.
상기와 같이 이루어지는 본 발명은 수평 구조를 가지는 바이폴라 트랜지스터를 제조할 수가 있게 되며, 스페이서를 이용하여 베이스의 폭을 정밀하게 조절할 수 있게 된다. 또한, 본 발명은 스페이서를 이용하여 자기정렬법으로 베이스를 형성할 수 있어 소자를 보다 쉽게 제조할 수 있다.According to the present invention made as described above it is possible to manufacture a bipolar transistor having a horizontal structure, it is possible to precisely adjust the width of the base using a spacer. In addition, the present invention can form a base by a self-aligning method using a spacer, it is possible to manufacture the device more easily.
Claims (8)
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| KR1019950018278A KR0172509B1 (en) | 1995-06-29 | 1995-06-29 | Method of fabricating lateral bipolar transistor |
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| KR20010020646A (en) * | 1999-08-16 | 2001-03-15 | 양용진 | method for manufacturing ornamental workpiece made from thin mother-of-pearl sheet at least one of whose surfaces is coated or laminated with transparent synthetic resin and stringed instrument using the workpiece |
| KR100384687B1 (en) * | 2000-08-01 | 2003-05-22 | 김정열 | mother-of-pearl ornament by screen printing and method for producing the same |
| KR101008409B1 (en) * | 2008-06-05 | 2011-01-14 | 김윤미 | Article Having Colored Mother-of-pearl Sheet and Fabricating Method Thereof |
| KR101008469B1 (en) * | 2008-06-05 | 2011-01-14 | 김윤미 | Colored Mother-of-pearl Sheet and Fabricating Method Thereof |
-
1995
- 1995-06-29 KR KR1019950018278A patent/KR0172509B1/en not_active IP Right Cessation
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| Publication number | Publication date |
|---|---|
| KR970003939A (en) | 1997-01-29 |
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