KR0128023B1 - Fabrication method of lateral bipolar transistor device complete element isolation structure - Google Patents
Fabrication method of lateral bipolar transistor device complete element isolation structureInfo
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- KR0128023B1 KR0128023B1 KR1019940010555A KR19940010555A KR0128023B1 KR 0128023 B1 KR0128023 B1 KR 0128023B1 KR 1019940010555 A KR1019940010555 A KR 1019940010555A KR 19940010555 A KR19940010555 A KR 19940010555A KR 0128023 B1 KR0128023 B1 KR 0128023B1
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- 238000000034 method Methods 0.000 title claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 238000002955 isolation Methods 0.000 title claims description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 35
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 35
- 239000010703 silicon Substances 0.000 claims abstract description 35
- 238000005530 etching Methods 0.000 claims abstract description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 11
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 11
- 238000001020 plasma etching Methods 0.000 claims abstract description 9
- 230000003647 oxidation Effects 0.000 claims abstract description 6
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 5
- 238000005468 ion implantation Methods 0.000 claims abstract description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 5
- 229920002120 photoresistant polymer Polymers 0.000 claims description 24
- 239000012535 impurity Substances 0.000 claims description 18
- 238000001459 lithography Methods 0.000 claims description 14
- 229910052751 metal Inorganic materials 0.000 claims description 13
- 239000002184 metal Substances 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 10
- 238000005229 chemical vapour deposition Methods 0.000 claims description 9
- 238000010438 heat treatment Methods 0.000 claims description 9
- 150000002500 ions Chemical class 0.000 claims description 8
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 7
- 239000010936 titanium Substances 0.000 claims description 7
- 229910052719 titanium Inorganic materials 0.000 claims description 7
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 229910021341 titanium silicide Inorganic materials 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 2
- 239000002019 doping agent Substances 0.000 abstract 2
- 230000003071 parasitic effect Effects 0.000 description 4
- 230000005669 field effect Effects 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- FAPWRFPIFSIZLT-UHFFFAOYSA-M Sodium chloride Chemical compound [Na+].[Cl-] FAPWRFPIFSIZLT-UHFFFAOYSA-M 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000011780 sodium chloride Substances 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/6625—Lateral transistors
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0804—Emitter regions of bipolar transistors
- H01L29/0808—Emitter regions of bipolar transistors of lateral transistors
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1004—Base region of bipolar transistors
- H01L29/1008—Base region of bipolar transistors of lateral transistors
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Abstract
Description
제1도의 (a)∼(1)은 본 발명의 바람직한 실시예에 따른 측면 쌍극자 트랜지스터의 제조방법을 공정순서대로 나타낸 단면도.1 (a) to (1) are cross-sectional views showing a method of manufacturing a side dipole transistor according to a preferred embodiment of the present invention in the order of a process.
제2도의 (a) 및 (b)는 제1도의 제조방법에서 사용되는 마스크들의 평면 배치도(mask layout).(A) and (b) of FIG. 2 are mask layouts of masks used in the manufacturing method of FIG.
본발명은 SOI(silicon-on-insulator)기판 위에서 에미터(emitter)와 베이스(base),콜렉터(collector)가 수평으로 배치되고 완전한 소자 격리 구조를 갖는 측면 쌍극자 트랜지스터(lateral bipolar transistor)장치의 제조방법에 관한 것이다.The present invention provides the fabrication of a lateral bipolar transistor device in which an emitter, a base, and a collector are horizontally disposed on a silicon-on-insulator (SOI) substrate and have a complete device isolation structure. It is about a method.
트랜지스터를 SOI기판위에 구현하면, 완전한 소자격리를 매우 쉽게 얻을 수 있어서, 방사선(radiation)에 대한 저항성이 큰 소자를 만들 수 있고, 기생축전용량(aprasiticcapacitance)을 줄일 수 있어 고속소자를 얻을 수 있고, 소비전력을 줄일 수 있는 등의 장점이 있다. 그래서 SOI기판 위에 여러 가지 소자를 구현하려는 연구가 활발하게 진행되고 있다.Implementing a transistor on an SOI substrate makes it possible to obtain complete device isolation very easily, to create a device that is highly resistant to radiation, and to reduce parasitic capacitance, resulting in a high-speed device. There are advantages such as reducing power consumption. As a result, researches for implementing various devices on SOI substrates are being actively conducted.
또한 전계효과 트랜지스터(meta1-oxide-semiconductor field effect transistor; MOSFET)와 쌍극자 트랜지스터를 같은 칩(chip)위에 만들어 각 소자의 장점을 함께 취하려는 노력도 계속되어 왔다.Efforts have also been made to take advantage of each device by making a field effect transistor (Meta1-oxide-semiconductor field effect transistor) and a dipole transistor on the same chip.
이와 같이 MOSEFT소자와 쌍극자 소자를 같은 칩에 함께 만들기 위해서는, SOI기판에서 실리콘산화막(silicon oxide) 위의 실리콘(silicon)층 두께가 얇은 SIO기판을 이용하는 것이 유리하다.Thus, in order to make the MOSEFT device and the dipole device together on the same chip, it is advantageous to use an SIO substrate having a thin thickness of a silicon layer on the silicon oxide film in the SOI substrate.
왜냐하면 완전한 소자격리를 위해서는 MOSFET소자는 얇은 실리콘층 위에 만드는 것이 유리하기 때문이다.Because for complete device isolation, it is advantageous to build MOSFET devices on thin silicon layers.
따라서 쌍극자 소자도 역시 얇은 실리콘층 위에 만들어져야만 한다. 하지만 종래의 쌍극자 소자는 수직방향으로 에미터와 베이스, 콜렉터가 형성되 있기 때문에 얇은 실리콘층을 갖는 SOI기판 위에 쌍극자 소자를 만드는 것은 어려웠다.Thus, dipole devices must also be made on thin silicon layers. However, in the conventional dipole device, since the emitter, the base, and the collector are formed in the vertical direction, it is difficult to make the dipole device on the SOI substrate having the thin silicon layer.
본 발명은 에미터와 베이스, 콜렉터를 활성영역(active region)에 측면으로 배열하여 기생저항 및 기생용량을 감소시킬 수 있는 측면 쌍극자 트랜지스터의 제조방법을 제공하는 데 목적이 있다.It is an object of the present invention to provide a method of manufacturing a side dipole transistor capable of reducing parasitic resistance and parasitic capacitance by arranging emitters, bases and collectors in an active region laterally.
이와 같은 목적을 달성하기 위한 본 발명의 기술적인 특징으로서, 본 발명은 열 산화에 의해 제1도전형의 실리콘층에 소자격리용 절연막을 형성하고, 상기 실리콘층의 표면 위에 제1절연막을 형성하는 공정과; 리소그라피에 의해 활성영역을 정의하역 감광막 패턴을 형성하고, 상기 감광막 패턴을 마스크로서 사용하는 반응성 이온 식각(RIE)에 의해 상기 제 1 절연막을 식각하여 상기 실리콘층을 노출시키는 공정과; 상기 실리콘층의 노출된 표면과 상기 제 1 절연막의 표면 위에 화학증착법에 의해 제 2 절연막을 형성하고, 반응성 이온 식각법으로 상기 제2절연막을 비등방적으로 식각함으로써, 측벽 절연막을 형성함과 아울러 상기 실리콘층을 노출시키는 공정과; 상기 노출된 실리콘층으로 제1도전형의 불순물 이온을 고농도로 주입하여 한쌍의 제1도전층들을 형성하는 공정과;선택적인 열산화에 의해 상기 제1도전층들 위에만 선택적으로 제3절연막을 형성하고, 리소그라피에 의해 베이스를 정의하여 감광막 패턴을 형성한 후 상기 감광막 패턴을 마스크로서 사용하는 식각에 의해 베이스가 형성된 영역에 위치한 측벽 절연막을 완전히 게거하여 상기 실리콘층의 표면을 노출시키는 공정과 ; 상기 제1및 제3 절연막을 마스크로서 사용하는 이온 주입에 의해 제2도전형의 불순물을 상기 노출된 실리콘층으로 주입하여 제2도전층을 형성하는 공정과;화학증착법으로 표면이 노출된 상기 제2도전층 주위에만 선택적으로 제2도전형의 불순물이 고농도로 도핑된 제3도전층을 형성하는 공정과;웨이퍼의 전 표면 위에 제4절연막을 형성하고, 열처리를 수행하여 주입된 불순물을 활성화시키는 공정과;리소그라피방법으로 접촉영역을 정의하여 감광막 패턴을 형성하고, 상기 감광막 패턴을 마스크로서 사용하여 상기 제4 및 제3절연막을 식각하여 상기 제1도전층들의 표면을 노출시킨 후 상기 감광막 패턴을 제거하는 공정과; 웨이퍼의 표면 위에 타이타늄층을 형성하고, 열처리를 수행하여 상기 제1도전층들 위에 타이타늄 실리사이드층을 형성한 후 상기 제4절연막 위에 형성된 상기 타이타늄층을 제거하는 공정과;웨이퍼의 표면 위에 금속층을 형성하고 감광막을 도포한 후, 리소그라피 방법으로 금속 전극 형상을 정의하여 감광막 패턴을 형성하고 상기 감광막 패턴을 마스크로서 사용하여 금속층을 식각하는 것에 의해 에미터, 베이스, 콜렉터의 금속전극(115)을 각각 형성한 후 열처리하는 공정을 포함한다.As a technical feature of the present invention for achieving the above object, the present invention is to form an insulating film for device isolation in the silicon layer of the first conductivity type by thermal oxidation, and to form a first insulating film on the surface of the silicon layer Process; Forming an unloading photoresist pattern by defining lithography and etching the first insulating film by reactive ion etching (RIE) using the photoresist pattern as a mask to expose the silicon layer; Forming a second insulating film on the exposed surface of the silicon layer and the surface of the first insulating film by chemical vapor deposition, and anisotropically etching the second insulating film by reactive ion etching to form a sidewall insulating film. Exposing the silicon layer; Forming a pair of first conductive layers by implanting impurity ions of a first conductivity type into the exposed silicon layer at a high concentration; selectively forming a third insulating layer only on the first conductive layers by selective thermal oxidation; Forming a photoresist pattern by defining a base by lithography, and then completely removing the sidewall insulating film located in a region where the base is formed by etching using the photoresist pattern as a mask to expose the surface of the silicon layer; Implanting impurities of a second conductivity type into the exposed silicon layer by ion implantation using the first and third insulating films as masks; forming a second conductive layer; Forming a third conductive layer selectively doped with impurities of a second conductivity type only around the second conductive layer; forming a fourth insulating film on the entire surface of the wafer and performing a heat treatment to activate the implanted impurities Forming a photoresist pattern by defining a contact region by a lithography method, etching the fourth and third insulating layers using the photoresist pattern as a mask to expose the surfaces of the first conductive layers, and then Removing the process; Forming a titanium layer on the surface of the wafer, performing a heat treatment to form a titanium silicide layer on the first conductive layers, and then removing the titanium layer formed on the fourth insulating layer; forming a metal layer on the surface of the wafer; After the photoresist was applied, a metal electrode shape was defined by a lithography method to form a photoresist pattern, and the metal layer 115 of the emitter, base, and collector was formed by etching the metal layer using the photoresist pattern as a mask. And then heat treatment.
제1도의 (a)∼(1)은 본 발명의 바람직한 실시예에 따라 SOI 기판 위에서 완전한 소자 격리 구조를 갖춘 측면 쌍극자 트랜지스터를 제조하는 방법을 공정 순서대로 나타낸 단면도들로서, 이하 이 도면들을 참조하면서 본 발명의 바람직한 실시예를 상세히 설명한다.1 (a) to (1) are cross-sectional views showing, in process order, a method of manufacturing a side dipole transistor with a complete device isolation structure on an SOI substrate in accordance with a preferred embodiment of the present invention. Preferred embodiments of the invention are described in detail.
먼저, 제1도의 (a)를 참조하여, 절염낙인 산화막(실리콘산화막)(11) 위에 n-형의 실리콘층(12)이 얇게 형성된 SOI기판에서, 열 산화에 의해 비활성 영역(inactive region)의 상기 실리콘층(12)에 소자격리용 산화막(실리콘산화막)(13)을 형성한다.First, referring to (a) of FIG. 1, in an SOI substrate in which an n − type silicon layer 12 is thinly formed on an oxide film (silicon oxide film) 11, which is a saline drop, a layer of an inactive region is formed by thermal oxidation. An isolation film (silicon oxide film) 13 is formed in the silicon layer 12.
소자격리를 위해서 첫번째 마스크(mask)를 사용하는데, 그 평면 배치를 살펴보면 제2도의 (a)에서 참조번호 21로 나타낸 실선과 같다.The first mask is used for device isolation, and the planar arrangement thereof is the same as the solid line indicated by reference numeral 21 in FIG.
제1도의 (a) 내지 (1)은 제2도의 (a)에서 A-A'방향으로 취해진 단면도이다.(A)-(1) of FIG. 1 is sectional drawing taken along the AA 'direction in (a) of FIG.
이어, 제1도의 (b)를 참조하여, 웨이퍼의 표면위에 2000Å 정도의 두께로 제1절연막(실리콘 산화막)(14)을 화학증착법을 이용하여 형성한다.Subsequently, referring to Fig. 1B, a first insulating film (silicon oxide film) 14 is formed on the surface of the wafer by a chemical vapor deposition method with a thickness of about 2000 GPa.
다음, 두번째 마스크를 이용하여 에미터와 서브-콜렉터(sub-co1lector)로 사용될 n++형의 영역(제1도전층)을 정의(define)한다.Next, the second mask is used to define an n ++ type region (first conductive layer) to be used as an emitter and a sub-co1lector.
이 n++영역인 제1도전층은 제2도의 (a)에서 참조번호 22로 표시된 점선으로 정의되는 영역이다.The first conductive layer, which is this n ++ region, is a region defined by the dotted line indicated by reference numeral 22 in (a) of FIG.
상기 제1도전층(n++영역)은 리소그라피에 의해 정의된다.The first conductive layer (n ++ region) is defined by lithography.
이어, 제1도의 (c)를 참조하여, 상기 리소그라피에서 형성된 감광막 패턴(photoresistpattern)을 마스크로서 사용하는 반응성 이온 식각법(reactiveionetching)에 의해 제1절연막(실리콘 산화막)(14)을 식각하여 활성영역(active region)의 실리콘층(12)을 노출시킨다.Next, referring to (c) of FIG. 1, the first insulating layer (silicon oxide layer) 14 is etched by reactive ionetching using a photoresist pattern formed from the lithography as a mask. The silicon layer 12 of the (active region) is exposed.
노출된 실리콘층(12)과 제1절연막(14) 위에 화학증착법에 의해 제2절연막(실리콘질화막)을 형성하고, 반응성 이온 식각법으로 상기 제2절연막을 비등방적으로(anisotropically) 식각함으로써, 측벽 절연막(15)을 형성함과 아울러 활성영역의 실리콘층(12)을 노출시킨다.A second insulating film (silicon nitride film) is formed on the exposed silicon layer 12 and the first insulating film 14 by chemical vapor deposition, and the second insulating film is anisotropically etched by reactive ion etching. The insulating film 15 is formed and the silicon layer 12 in the active region is exposed.
이때, 형성되는 측벽 절연막(15)에 의해 베이스 콕이 결정된다.At this time, the base cock is determined by the sidewall insulating film 15 formed.
따라서, 측벽 절연막(15)의 두께를 조절하는 것에 의해 베이스층의 폭 크기가 쉽게 조절될 수 있다.Therefore, the width size of the base layer can be easily adjusted by adjusting the thickness of the sidewall insulating film 15.
다음, 제1도의 (d)를 참조하여, 에미터와 서브-콜렉터인 제1도전층들(n++영역들)(16)을 만들기 위해서, 노출된 실리콘층(12)으로 제1도전형(n형)의 불순물 이온들(17)을 주입하여 활성영역에 한쌍의 n++영역들을 형성한다.Next, referring to FIG. 1D, in order to make the first conductive layers (n ++ regions) 16 that are emitters and sub-collectors, the first conductive type is exposed to the exposed silicon layer 12. The n-type impurity ions 17 are implanted to form a pair of n ++ regions in the active region.
이때, 제1도전형의 불순물 이온(17)으로서는 As이온이 사용된다.At this time, As ions are used as the impurity ions 17 of the first conductivity type.
다음, 제1도의 (e)를 참조하여, 선택적인 연산화에 의해 불순물 이온이 주입된 제1도전층들(16) 위에만 선택적으로 제3절연막(실리콘 산화막)(18)을 형성한다.Next, referring to FIG. 1E, a third insulating film (silicon oxide film) 18 is selectively formed only on the first conductive layers 16 into which impurity ions have been implanted by selective computation.
다음, 베이스를 형성하기 위해서 마스크를 사용하는데, 베이스 마스크에 의해 정의되는 베이스 영역은 제2도의 (a)에서 참조번호 23으로 나타낸 굵은 실선에 의해 정의되는 영역이다.Next, a mask is used to form a base, and the base area defined by the base mask is an area defined by thick solid lines indicated by reference numeral 23 in Fig. 2A.
그러나, 이 영역(23)은 정확한 베이스 영역이 아니다.However, this area 23 is not an exact base area.
베이스는 측벽 절연막 15a를 식각하여 제거한 후, 측벽 질화막(15a)이 제거된 바로 그 부분에 만들어질 것이기 때문에 제2도의 (a)에 도시된 베이스 영역(23)은 단순히 측벽 질화막 15a를 식각 제거할때, 다른 부분들을 보호하기 위한 것이다.Since the base is made by etching and removing the sidewall insulating film 15a, the base region 23 shown in (a) of FIG. 2 will simply etch away the sidewall nitride film 15a. When, to protect other parts.
따라서, 마스크 오정렬로 인한 결함은 발성되지 않는다.Thus, defects due to mask misalignment are not spoken.
다음, 제1도의 (f)를 참조하여, 리소그라피에 의해 베이스를 정의하여 감광막 패턴(19)을 형성한다.Next, referring to Fig. 1 (f), the base is defined by lithography to form the photoresist pattern 19.
감광막 패턴(19)을 마스크로서 사용하는 식각에 의해 베이스가 형성될 영역에 위치한 측벽 절연막(15a)을 완전히 제거하여 실리콘층(12)의 표면을 노출시킨다.By etching using the photoresist pattern 19 as a mask, the sidewall insulating film 15a located in the region where the base is to be formed is completely removed to expose the surface of the silicon layer 12.
다음, 제1도의 (g)를 참조하여, 산화막 14와 18을 마스크로서 사용하는 이온주입법에 의해 원하는 양의 제2도전형(p형)의 불순물(110)을 노출된 실리콘층(12)으로 주입하여 제2도전층(111)을 형성한다.Next, referring to (g) of FIG. 1, a desired amount of the second conductivity type (p-type) impurity 110 is exposed to the exposed silicon layer 12 by an ion implantation method using oxide films 14 and 18 as masks. Injecting to form a second conductive layer 111.
상기 제2도전층(111)은 베이스로서 작용하게 될 것이다.The second conductive layer 111 will act as a base.
다음, 제1도의 (h)를 참조하여, 기판세척을 수행한 후에 얇은 베이스층과 베이스전극을 연결하기 위해 SiH2Cl2-HC1-H2계통의 가스를 이용한 화학증착법으로 표면이 노출된 제2도전층(111) 위에만 선택적으로 3000Å 정도의 두께로 제3도전층(불순물이 주입된 실리콘층)(112)을 형성한다.Next, referring to (h) of FIG. 1, the surface is exposed by chemical vapor deposition using a gas of SiH 2 Cl 2 -HC1-H 2 system to connect the thin base layer and the base electrode after performing substrate cleaning. A third conductive layer (silicon layer infused with impurities) 112 is formed on the second conductive layer 111 only to a thickness of about 3000 kV.
이 화학증착공정시 실리콘층(112)의 형성과 동시에 p형의 불순물이 거기로 고농도로 도핑된다.At the same time as the formation of the silicon layer 112 in the chemical vapor deposition process, p-type impurities are heavily doped therein.
다음, 제1도의 (i)를 참조하여, 화학증착법을 이용하여 웨이퍼의 표면 위에 제4절연막(실리콘산화막)(113)을 형성한다.Next, referring to Fig. 1 (i), a fourth insulating film (silicon oxide film) 113 is formed on the surface of the wafer by chemical vapor deposition.
그후, 주입된 불순물을 활성화시킴과 아울러 에미터/베이스 접합(junction)(114)을 형성하기 위한 열처리를 수행한다.Thereafter, heat treatment is performed to activate the implanted impurities and to form the emitter / base junction 114.
다음, 제1도의 (j)를 참조하여, 네번째 마스크를 이용하여 접촉(contact) 부분을 정의한다.Next, referring to (j) of FIG. 1, a contact portion is defined using a fourth mask.
접촉부분은 제2도의 (a)에서 참조번호 24로 나타낸 실선으로 정의되는 영역이다.The contact portion is a region defined by the solid line indicated by reference numeral 24 in FIG.
리소그라피방법으로 접촉영역을 정의하여 감광막 패턴(도시되지 않음)을 형성하고, 감광막 패턴을 마스크로서 사용하여 제4산화막(113)과 제3절연막(18)을 순차로 식각한다.A contact region is defined by a lithography method to form a photosensitive film pattern (not shown), and the fourth oxide film 113 and the third insulating film 18 are sequentially etched using the photosensitive film pattern as a mask.
이로써, 불순물 이온이 주입된 제1도전층들(n++영역들)(16)의 표면이 노출된다.As a result, the surface of the first conductive layers (n ++ regions) 16 implanted with impurity ions is exposed.
그리고 마스크로 사용된 감광막 패턴을 제거한다.Then, the photoresist pattern used as the mask is removed.
다음, 제1도의 (k)를 참조하여, 자기정렬 실리사이드(self-aligned silicide)를 형성하기 위해, 웨이퍼의 표면 위에 타이타늄(titanium)층을 형성하고 열처리를 수행한다.Next, referring to (k) of FIG. 1, a titanium layer is formed on the surface of the wafer and heat treatment is performed to form a self-aligned silicide.
이로써, 실리콘과 접촉되어 있는(즉, 불순물 이온이 주입된 n++영역들(16) 위의) 타이타늄층을 실리콘과 반응하여 타이타늄 실리사이드층(titanium silicide layer)(114)을 형성한다.Thus, a titanium layer in contact with silicon (ie, over n ++ regions 16 implanted with impurity ions) is reacted with silicon to form a titanium silicide layer 114.
그 후, 제4절연막(113) 위에 형성되어 있는 타이타늄층을 완전히 제거한다.Thereafter, the titanium layer formed on the fourth insulating film 113 is completely removed.
마지막으로, 제1도의 (1)을 참조하여, 웨이퍼의 표면 위에 금속층을 형성하고 감광막을 도포한 후, 리소그라피 방법으로 금속 전극 형상을 정의하고, 리소그라피에 의해 형성된 감광막 패턴을 마스크로서 사용하여 금속층을 식각함으로써 에미터, 베이스, 콜렉터의 금속전극(115)을 각각 형성한다.Finally, referring to (1) of FIG. 1, after forming a metal layer on the surface of the wafer and applying a photoresist film, the metal electrode shape is defined by a lithography method, and the metal layer is formed using a photoresist pattern formed by lithography as a mask. By etching, the metal electrodes 115 of the emitter, the base, and the collector are formed, respectively.
이때, 금속 전극들은 제2도의 (b)에서 참조번호 25로 나타낸 실선에 의해 정의되는 영역들이다.At this time, the metal electrodes are regions defined by the solid line indicated by reference numeral 25 in (b) of FIG. 2.
그리고 열처리(alloying)을 수행하여 본 발명에 의한 완전 소자격리된 측면 쌍극자 트랜지스터를 완성한다.Then, heat treatment is performed to complete the fully isolated side dipole transistor according to the present invention.
제1도의 (1)에서 보는 바와 같이 본 실시예에 의한 완전소자격리된 측면 쌍극자 트랜지스터는 완전한 소자격리와 측면 방향의 에미터, 베이스,콜렉터 형성에 의해서 기생용량(parasitic capacitacne)을 줄였다.As shown in (1) of FIG. 1, the parasitic capacitacne is reduced by the isolation of the complete device isolation and the formation of the emitter, base, and collector in the lateral direction.
또한 베이스층(111)의 폭을 측벽 절연막(15a)을 사용하여 쉽게 줄일 수 있다.In addition, the width of the base layer 111 can be easily reduced by using the sidewall insulating film 15a.
또한 베이스층이 얇은 데도 불구하고 실리콘층(112)의 선택적인 성장과 실리사이드층(114)의 형성으로 베이스 저항을 낮게 하면서 베이스 전극을 연결할 수 있다.In addition, even though the base layer is thin, the base electrode can be connected while the base resistance is lowered by the selective growth of the silicon layer 112 and the formation of the silicide layer 114.
그리고 콜렉터의 항복(breakdown)전압을 높이기 위해 채택한 n-층(116)의 콜렉터의 두께를 쉽게 조절할 수 있다.In addition, the thickness of the collector of the n − layer 116 may be easily adjusted to increase the breakdown voltage of the collector.
상기와 같은 장점으로 본 발명에 의한 소자는 소자의 동작속도가 크게 향상될 수 있으며, MOSFET소자와 비슷한 수준의 높은 집적도를 얻을 수 있다.With the above advantages, the device according to the present invention can greatly improve the operation speed of the device, and obtain a high degree of integration similar to that of the MOSFET device.
여기서는 한 가지의 바람직한 실시예를 통하여 본 발명의 제소방법을 설명하였으나 본 발명의 사상에 벗어남이 없이 다르게 다양한 실시가 가능함을 이 분야에 통상적인 지식을 가진 자는 쉽게 알 수 있을 것이다.Herein, the method of filing the present invention has been described through one preferred embodiment, but it will be easily understood by those skilled in the art that various implementations can be made without departing from the spirit of the present invention.
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