WO1993017458A1 - Soi-type semiconductor device and method of producing the same - Google Patents

Soi-type semiconductor device and method of producing the same Download PDF

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Publication number
WO1993017458A1
WO1993017458A1 PCT/JP1990/001124 JP9001124W WO9317458A1 WO 1993017458 A1 WO1993017458 A1 WO 1993017458A1 JP 9001124 W JP9001124 W JP 9001124W WO 9317458 A1 WO9317458 A1 WO 9317458A1
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film
semiconductor device
conductor
insulating film
semiconductor
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PCT/JP1990/001124
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French (fr)
Japanese (ja)
Inventor
Tohru Yoshida
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Tohru Yoshida
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Priority to US07/684,932 priority Critical patent/US5191397A/en
Publication of WO1993017458A1 publication Critical patent/WO1993017458A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H01L21/743—Making of internal connections, substrate contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/78654—Monocrystalline silicon transistors

Definitions

  • the present invention relates to an SOI (silicon insul nat sor t) type semiconductor device and a method for manufacturing the same, and more particularly, to a device used for an ultra-high-speed, ultra-high-integration MOS integrated circuit.
  • SOI silicon insul nat sor t
  • an S0I type M0S transistor has a cross-sectional structure as shown in FIG. 1 or FIG.
  • 1 is Li co down substrate
  • the single crystal Li co down film 3 the n + realm 4
  • 5 gate insulation ⁇ , 6 polycrystalline sheet Li Congate 7 is a depletion layer.
  • FIG. 1 shows an M0S transistor in the case where the single-crystal silicon film 3 is relatively thick, that is, a region where no depletion remains immediately below the channel.
  • the gate electric field force is applied to both the gate oxide film 5 and the depletion layer 7, the electric field intensity in the channel region increases.
  • the single crystal silicon film 3 has lower field-effect mobility because of the poorer crystallinity of the silicon substrate (bulk silicon) 1.
  • the current driving capability is reduced.
  • FIG. 5 shows an M type S transistor when the single crystal silicon film 3 is relatively thin, about 500 persons, that is, when the entire area under the channel is depleted.
  • a depletion layer formed in the single-crystal silicon film 3 is formed in the underlying Si 02 film 2.
  • the capacitance between the single-crystal silicon film (usually p-type) 3 and the n + region 4 decreases, and the electron field-effect mobility becomes 900-: LOOO cm 2 / V ⁇ S. This has the advantage that it is more than 1.5 times higher than that of Luk MOS transistors.
  • the n + region 4 as a drain or a source is reached using anisotropic etching such as RIE (reactive ion etching).
  • RIE reactive ion etching
  • the thickness of the insulating film 3 is d
  • r> 2 d That is, as the thickness d of the single-crystal silicon film 3 becomes smaller, the A electrode 9 and the n + region 4 become smaller.
  • the area of the contact portion with the above becomes small, and the contact pile becomes large.
  • cut etching with NH 4 F or the like is used instead of RIE or the like, the above contact hole can be prevented from penetrating, but sufficient contact matching margin must be provided. This is a significant disadvantage for high integration.
  • the diffusion layer formed thereon must necessarily be made thinner, so that the resistance of the wiring of the diffusion layer becomes larger. For this reason, even if the single crystal silicon film 3 is thinned to increase the electron field effect mobility and increase the current driving capability, high-speed operation as an integrated circuit cannot be expected. Therefore, it becomes impossible to use the diffusion layer wiring, and the wiring of the integrated circuit must be composed only of the AQ wiring and the gate polycrystalline silicon. The disadvantage is that the size of the screen increases.
  • the present invention increases the wiring resistance of the diffusion layer wiring without increasing the contact resistance even in the S0I type MOS integrated circuit having a thin single-crystal silicon film. It is an object of the present invention to provide a high-speed, high-performance, high-quality SOI semiconductor device that can be manufactured without breaking.
  • An SOI semiconductor device has a semiconductor substrate, a concave portion, an insulating film formed on the semiconductor substrate, a conductor embedded in the concave portion, and a semiconductor formed on the insulating film. And a film formed on the semiconductor film and electrically connected to the conductor. And an impurity region to be connected.
  • the S0I type semiconductor device has a semiconductor substrate, a concave portion, an insulating film formed on the semiconductor substrate, a conductor embedded in the concave portion, and an insulating film on the insulating film.
  • An interlayer insulating film formed on the entire surface; and an electrode wiring connected to the impurity region via the contact hole.
  • an insulating film is formed on a semiconductor substrate, a recess is formed in the insulating film, a conductor is buried in the recess, and the insulating film is formed on the insulating film.
  • a semiconductor film is formed, and an impurity region electrically connected to the conductor is formed in the semiconductor film.
  • a method of manufacturing an S 0 I type semiconductor device is as follows.
  • An insulating film is formed on a semiconductor substrate, a concave portion is formed in the insulating film, and a conductor is buried in the concave portion.
  • Forming a semiconductor film forming an impurity region electrically connected to the conductor in the semiconductor film on the recess, forming an interlayer insulating film on the entire surface, and forming the interlayer film on the recess.
  • a contact hole reaching at least the impurity region is formed, and an electrode wiring is formed in a region including above the contact hole.
  • the wiring layer can be formed in the concave portion formed in the insulating film below the semiconductor film. For this reason, the semiconductor Even if the body film is formed thin, the wiring resistance of the wiring layer does not increase. Further, an impurity region is formed in the semiconductor film on the concave portion, and a conductor is buried in the concave portion. Therefore, even if the contact hole penetrates through the impurity region, the conductor does not reach the insulating film therebelow because the conductor exists in the concave portion. As a result, the area of the contact portion does not become small, and a low contact resistance can be realized.
  • FIG. 1 to 3 are cross-sectional views showing a conventional SOI type MOS semiconductor device, respectively.
  • FIG. 4 is a plane pattern diagram showing an SOI type MOS semiconductor device according to one embodiment of the present invention.
  • FIG. 5 is a cross-sectional view taken along the line I-I 'of FIG. 4, and
  • FIG. 7 is a cross-sectional view taken along the line II ′ in FIG. 6, and
  • FIG. 9 is a cross-sectional view of FIG.
  • FIG. 4 is a cross-sectional view taken along a line m ′.
  • FIG. 4 shows a plane pattern of a SOI type MOS semiconductor device according to one embodiment of the present invention.
  • FIG. 5 is a cross-sectional view taken along the line I-I 'of FIG.
  • an insulating film 12 for example, a thermal oxide film, a CVD oxide film, etc.
  • the insulating film 12 has a recess 13 a immediately below the contact hole forming region.
  • recesses 13b are respectively formed in the wiring layer formation region.
  • the recesses 13a and 13b are filled with, for example, polycrystalline silicon (conductor) Ua, b doped with impurities.
  • the polycrystalline silicon 14b buried in the recess 13b forms a wiring layer.
  • a relatively thin single-crystal silicon film 15 of about 500 persons is formed.
  • a MOSFET is formed on the single-crystal silicon film 15. Specifically, n + impurity region 16 as a source or a drain is formed in single crystal silicon film 15 including recesses 13a and 13b. Gate oxide film 17 is formed on the channel region between n + impurity regions 16. On the gate oxide film 17, a gate electrode 18 is formed. The gate electrode 18 can be made of polycrystalline silicon doped with impurities.
  • the MOSFET is composed of the n + impurity region 16, the gate oxide film 17 and the gate electrode 18. Further, an interlayer insulating film 19 is formed on the entire surface. ⁇ Contact hole 20 is formed on interlayer insulating film 19 on concave portion 13a.
  • the contact hole 20 does not reach the insulating film 12 because the recess 13 a exists. Further, in the contact hole 20, an A wiring 21 is formed, and a contact between the n + impurity region 16 and the A wiring 21 is taken.
  • FIG. 7 is a cross-sectional view taken along the line ⁇ —II ′ in FIG.
  • FIG. 9 is a sectional view taken along the line HI-m ′ in FIG.
  • an insulating film 12 having a thickness of about 1 m is deposited and formed on a silicon substrate 11. Further, the insulating film 12 existing immediately below the connection hole formation region and in the wiring layer formation region is etched by about ⁇ by photolithography to form the concave portions 13a and 13b.
  • impurities are doped. Further, by performing etch-back on the entire surface, polycrystalline silicon 14a, 14b doped with impurities is buried in the recesses 13a, 13b.
  • an amorphous silicon film is deposited on the entire surface by about 5 ⁇ 0 people. Thereafter, the amorphous silicon film is crystallized by laser annealing, electron beam annealing, or the like, and a single-crystal silicon film 15 is formed. The element active region is formed by etching the single-crystal silicon film 15 into an island shape using a photolithography process. Further, after the gate oxide film 17 is formed by using the thermal oxidation method, a polycrystalline silicon film is deposited and formed on the entire surface. In addition, phosphorus (P) is diffused to make this polycrystalline silicon film a conductor.
  • P phosphorus
  • a gate electrode 18 and a polycrystalline silicon wiring are formed using a photolithographic process. Further, phosphorus or arsenic (As) is ion-implanted using the gate electrode 18 as a mask to form an n + impurity region 16 as a source or a drain.
  • a contact hole 20 is formed on the interlayer insulating film 19 on the concave portion 13 a by photolithography. Further, an A wiring 21 is formed in a region including the contact hole 20, and the connection between the n + impurity region 16 and the A wiring 21 is established.
  • the wiring layer (diffusion layer wiring) is formed in the recess 13 b formed in the insulating film 12 without being formed in the thin single-crystal silicon film 15.
  • the wiring layer is composed of the polycrystalline silicon 14b embedded in the recess 13b of the insulating film 12.
  • the wiring resistance of the wiring layer can be reduced, and the degree of design freedom is increased, which is advantageous for high integration.
  • a recess 13a in which polycrystalline silicon 14a is buried is formed immediately below contact hole 20 for making contact between A j? Interconnection 21 and n + impurity region 16. . Therefore, even if the contact hole formed by RIE or the like penetrates through the n + impurity region 16 as a source or a drain, the polycrystalline silicon in which the impurity is doped in the recess 13a is formed. Since the conductive material 14a is present, it does not reach the insulating film 12 thereunder. Therefore, the area of the contact portion between the A J2 wiring 21 and the n + impurity region 16 is not reduced, and the contact resistance between the A wiring 21 and the n + impurity region 16 is prevented from increasing.
  • the n-channel S0I type M0S semiconductor device has been described.
  • the present invention can be applied to a p-channel or complementary MOS semiconductor device.
  • the crystalline silicon a and b are formed by doping impurities independently, they may be formed simultaneously with the formation of the n + impurity region 16 by ion implantation.
  • the conductors embedded in the recesses 13a and 13b are not limited to polycrystalline silicon, but may be single-crystal silicon, amorphous silicon, silicon, and polysilicon. Or high melting point metal.
  • the SOI semiconductor device and the method of manufacturing the same of the present invention can reduce the contact resistance even if the thickness of the single crystal silicon film formed on the insulating film is particularly small. This is useful when manufacturing without increasing the wiring resistance of the diffusion layer wiring without increasing the wiring resistance.

Abstract

An SOI-type semiconductor device having a semiconductor film (15) of a reduced thickness formed on an insulating film (12). The SOI-type semiconductor device has a semiconductor substrate (11), the insulating film (12) that has recessed portions (13a, 13b) and that is formed on the semiconductor substrate (11), and electrically conductive members (14a, 14b) buried in the recessed portions (13a, 13b). The device further has the semiconductor film (15) formed on the insulating film (12) and impurity regions (16) that are formed in the semiconductor film (15) and that are electrically connected to the electrically conductive members (14a, 14b).

Description

明 細 書  Specification
S 0 I 型半導体装置及びその製造方法  S 0 I-type semiconductor device and manufacturing method thereof
技術分野  Technical field
本発明は、 S O I ( s i l i c o n o n i n s u l a t o r ) 型半導体装置及びその製造方法に関する もので、 ' 特に超高速、 超高集積の MO S集積回路に使用される もので める。  The present invention relates to an SOI (silicon insul nat sor t) type semiconductor device and a method for manufacturing the same, and more particularly, to a device used for an ultra-high-speed, ultra-high-integration MOS integrated circuit.
背景技術  Background art
従来、 S 0 I型 M 0 S ト ラ ン ジス タは、 第 1図又は第 2 図に示すような断面構造をしている。 こ こで、 1はシ リ コ ン 基板、 2は S i 02 膜、 3は単結晶シ リ コ ン膜、 4は n + 領 域、 5はゲー ト絶緣膜、 6は多結晶シ リ コ ンゲー ト、 7は空 乏層である。 Conventionally, an S0I type M0S transistor has a cross-sectional structure as shown in FIG. 1 or FIG. In here, 1 is Li co down substrate, 2 S i 0 2 film, the single crystal Li co down film 3, the n + realm 4, 5 gate insulation緣膜, 6 polycrystalline sheet Li Congate 7 is a depletion layer.
第 1図は、 単結晶シ リ コ ン膜 3が比較的に厚い場合、 即 ちチャ ネル下に空乏化しない領域が残るような場合の M 0 S トラ ンジスタを示している。 かかる場合には、 ゲー ト電界力《、 ゲー 卜酸化膜 5と空乏層 7の両方に加わるため、 チャネル領 域の電界強度が大き く なる。 このため、 この M 0 S トラ ンジ ス夕 は、 単結晶シ リ コ ン膜 3がシ リ コ ン基板 （バルク シ リ コ ン） 1より結晶性が悪い分だけ電子の電界効果移動度が下が り、 又電流駆動能力が低下するという欠点がある。  FIG. 1 shows an M0S transistor in the case where the single-crystal silicon film 3 is relatively thick, that is, a region where no depletion remains immediately below the channel. In such a case, since the gate electric field force is applied to both the gate oxide film 5 and the depletion layer 7, the electric field intensity in the channel region increases. For this reason, in the M0S transistor, the single crystal silicon film 3 has lower field-effect mobility because of the poorer crystallinity of the silicon substrate (bulk silicon) 1. In addition, there is a disadvantage that the current driving capability is reduced.
第 5図は、 単結晶シリ コ ン膜 3が 5 0 0 人程度と比較的 に薄い場合、 即ちチャ ネル下が全て空乏化するような場合の Mひ S トラ ンジスタを示している。 かかる場合には、 単結晶 シ リ コ ン膜 3に形成される空乏層が、 下地の S i 02 膜 2に 達する。 このため、 単結晶シリ コン膜 （通常は p型） 3及び n + 領域 4間の容量が減少し、 電子の電界効果移動度が 9 0 0〜： L O O O c m2 / V · Sとノく'ルク MO S トラ ンジスタの 1. 5倍以上に向上する利点がある。 FIG. 5 shows an M type S transistor when the single crystal silicon film 3 is relatively thin, about 500 persons, that is, when the entire area under the channel is depleted. In such a case, a depletion layer formed in the single-crystal silicon film 3 is formed in the underlying Si 02 film 2. Reach. As a result, the capacitance between the single-crystal silicon film (usually p-type) 3 and the n + region 4 decreases, and the electron field-effect mobility becomes 900-: LOOO cm 2 / V · S. This has the advantage that it is more than 1.5 times higher than that of Luk MOS transistors.
ところで、 単結晶シリ コン膜 3の比較的に薄い MO S ト ラ ンジスタでは、 この単結晶シリ コン膜 3をさ らに薄くする ことにより、 電子の電界効果移動度をシリ コン基板を走る電 子移動度 （ 1 3 5 0 c m2 ZV * S ) に近ずけるとが可能で ある。 なお、 これについては、 吉見 信等 "薄膜 S 0 I を用 いた高性能 S 0 I · M 0 S F E Tの特性解析" ， 電子情報通 信学会技術研究報告 〔シリ コ ン材料 ' デバイス） ， S D M 8 7 - 1 54 , P, 1 3〜 P. 18， 1 988年 1月に詳しく 記載されている。 By the way, in the case of a MOS transistor having a relatively thin single-crystal silicon film 3, the field-effect mobility of electrons can be reduced by making the single-crystal silicon film 3 even thinner. It is possible to approach the mobility (1350 cm 2 ZV * S). Nobuyoshi Yoshimi et al., “Characteristic analysis of high-performance S0I · M0 SFET using thin film S0I”, IEICE Technical Report [Silicon material 'device], SDM 8 7-1, 154, p. 13-p. 18, January 1998.
しかしながら、 単結晶シリ コン膜 3が薄く なればなる程、 3図に示すように、 R I E ( r e a c t i v e i o n e t c h i n g ) 等の異方性エッチングを用いて、 ドレイ ン 又はソ一スとしての n + 領域 4に達するコンタク トホ一ルを 層間絶緣膜 8に開ける場合、 n + 領域 4を突き抜けて S i 0 2 膜 2までエッチングしてしまう危険性が非常に高く なる。 こうなると、 A 電極 9と n + 領域 4とのコンタク 卜部分の 面積は、 n + 領域 4を突き抜けない場合に比べて、 円柱状の コ ンタク トホ—ルの半径を r、 単結晶シ リ コ ン膜 3の膜厚を dとすると、 7Γ Γ 2 — 2 r r d = ;r r 2 ( 1 — 2 d / r ) だ け減少する。 但し、 r > 2 d とする。 即ち、 単結晶シリ コ ン 膜 3の膜厚 dが薄く なればなる程、 A£ 電極 9と n + 領域 4 とのコ ンタク 卜部分の面積が小さ く なり、 そのコ ンタク 卜抵 杭が大き く なるという欠点がある。 なお、 R I E等に変えて N H 4 F等によるゥヱ ッ トエッチングを用いる場合は、 上記 コ ンタク トホ―ルの突き抜けは回避できるが、 コ ンタク ト整 合の余裕を十分に取らなければならず、 高集積化に著しく不 利となる。 However, as the single-crystal silicon film 3 becomes thinner, as shown in FIG. 3, the n + region 4 as a drain or a source is reached using anisotropic etching such as RIE (reactive ion etching). When the contact hole is opened in the interlayer insulating film 8, the danger of penetrating the n + region 4 and etching to the SiO 2 film 2 becomes extremely high. In this case, the area of the contact portion between the A electrode 9 and the n + region 4 is smaller than that of the case where the contact electrode does not penetrate the n + region 4 by the radius of the cylindrical contact hole r and the single-crystal silicon. Assuming that the thickness of the insulating film 3 is d, the thickness is reduced by 7Γ Γ 2 — 2 rrd =; rr 2 (1 — 2 d / r). However, r> 2 d. That is, as the thickness d of the single-crystal silicon film 3 becomes smaller, the A electrode 9 and the n + region 4 become smaller. However, there is a disadvantage in that the area of the contact portion with the above becomes small, and the contact pile becomes large. When cut etching with NH 4 F or the like is used instead of RIE or the like, the above contact hole can be prevented from penetrating, but sufficient contact matching margin must be provided. This is a significant disadvantage for high integration.
また、 単結晶シリ コ ン膜 3が薄く なると、 そこに形成さ れる拡散層も必然的に薄く しなければならないため、 拡散層 配線の抵抗も大き く なる。 このため、 単結晶シリ コ ン膜 3を 薄くすることにより電子の電界効果移動度を大き く し電流駆 動能力を上げても、 集積回路と しての高速動作は期待できな く なる。 よって、 拡散層配線を使用することが不可能になり、 A Q 配線ゃゲ— 卜多結晶シリ コ ンのみで集積回路の配線を構 成しなければならず、 設計の自由度が制限されパ夕一 ンが大 き く なるという欠点がある。  Further, when the single crystal silicon film 3 becomes thinner, the diffusion layer formed thereon must necessarily be made thinner, so that the resistance of the wiring of the diffusion layer becomes larger. For this reason, even if the single crystal silicon film 3 is thinned to increase the electron field effect mobility and increase the current driving capability, high-speed operation as an integrated circuit cannot be expected. Therefore, it becomes impossible to use the diffusion layer wiring, and the wiring of the integrated circuit must be composed only of the AQ wiring and the gate polycrystalline silicon. The disadvantage is that the size of the screen increases.
そ こで、 本発明は、 薄い単結晶シ リ コ ン膜を有する S 0 I 型 M O S集積回路であっても、 コ ンタク 卜抵抗を大き くす ることなく 、 かつ拡散層配線の配線抵抗を大き くすることな く製作できるような高速、 高性能、 高品質の S 0 I型半導体 装置を提供することを目的とする。  Therefore, the present invention increases the wiring resistance of the diffusion layer wiring without increasing the contact resistance even in the S0I type MOS integrated circuit having a thin single-crystal silicon film. It is an object of the present invention to provide a high-speed, high-performance, high-quality SOI semiconductor device that can be manufactured without breaking.
発明の開示  Disclosure of the invention
本発明に係わる S O I 型半導体装置は、 半導体基板と、 凹部を有し、 前記半導体基板上に形成される絶縁膜と、 前記 凹部に埋め込まれる導電体と、 前記絶緣膜上に形成される半 導体膜と、 前記半導体膜に形成され、 前記導電体と電気的に 接続される不純物領域とを備えている。 An SOI semiconductor device according to the present invention has a semiconductor substrate, a concave portion, an insulating film formed on the semiconductor substrate, a conductor embedded in the concave portion, and a semiconductor formed on the insulating film. And a film formed on the semiconductor film and electrically connected to the conductor. And an impurity region to be connected.
また、 本発明に係わる S 0 I型半導体装置は、 半導体基 板と、 凹部を有し、 前記半導体基板上に形成される絶緣膜と、 前記凹部に埋め込まれる導電体と、 前記絶緣膜上に形成され る半導体膜と、 前記凹部上の前記半導体膜に形成され、 前記 導電体と電気的に接続される不純物領域と、 前記凹部上に少 なく とも前記不純物領域へ達するコンタク 卜ホールを有し、 全面に形成される層間絶緣膜と、 前記コンタク トホールを介 して前記不純物領域に接続される電極配線とを備えている。 本発明に係わる S 0 I型半導体装置の製造方法は、 半導 体基板上に絶緣膜を形成し、 この絶緣膜に凹部を形成し、 こ の凹部に導電体を埋め込み、 前記絶緣膜上に半導体膜を形成 し、 この半導体膜に前記導電体と電気的に接統される不钝物 領域を形成する ものである。  Further, the S0I type semiconductor device according to the present invention has a semiconductor substrate, a concave portion, an insulating film formed on the semiconductor substrate, a conductor embedded in the concave portion, and an insulating film on the insulating film. A semiconductor film to be formed; an impurity region formed in the semiconductor film over the concave portion and electrically connected to the conductor; and a contact hole over the concave portion at least reaching the impurity region. An interlayer insulating film formed on the entire surface; and an electrode wiring connected to the impurity region via the contact hole. According to a method of manufacturing an S0I type semiconductor device according to the present invention, an insulating film is formed on a semiconductor substrate, a recess is formed in the insulating film, a conductor is buried in the recess, and the insulating film is formed on the insulating film. A semiconductor film is formed, and an impurity region electrically connected to the conductor is formed in the semiconductor film.
また、 本発明に係わる S 0 I型半導体装置の製造方法は. 半導体基板上に絶緣膜を形成し、 この铯緣膜に凹部を形成し- この凹部に導電体を埋め込み、 前記絶緣膜上に半導体膜を形 成し、 前記凹部上の前記半導体膜に前記導電体と電気的に接 続される不純物領域を形成し、 全面に層間絶緣膜を形成し、 前記凹部上の前記層間铯緣膜に少なく とも前記不純物領域へ 達するコンタク 卜ホ—ル形成し、 前記コンタク トホール上を 含む領域に電極配線を形成するものである。  Also, a method of manufacturing an S 0 I type semiconductor device according to the present invention is as follows. An insulating film is formed on a semiconductor substrate, a concave portion is formed in the insulating film, and a conductor is buried in the concave portion. Forming a semiconductor film, forming an impurity region electrically connected to the conductor in the semiconductor film on the recess, forming an interlayer insulating film on the entire surface, and forming the interlayer film on the recess. In particular, a contact hole reaching at least the impurity region is formed, and an electrode wiring is formed in a region including above the contact hole.
上記構成によれば、 半導体膜下の絶緣膜に形成された凹 部に、 配線層を形成することができる。 このため、 前記半導 体膜が薄く 形成されても、 前記配線層の配線抵抗が大き く な るという ことはない。 また、 凹部上の半導体膜には不純物領 域が形成され、 又前記凹部には導電体が埋め込まれてる。 こ のため、 コ ンタク トホールが前記不純物領域を突き抜けて形 成されても、 前記凹部には導電体が存在するので、 その下の 絶縁膜には達することがない。 この結果、 コ ンタク 卜部分の 面積は小さ く ならず、 低いコ ンタク 卜抵抗を実現できる。 According to the above configuration, the wiring layer can be formed in the concave portion formed in the insulating film below the semiconductor film. For this reason, the semiconductor Even if the body film is formed thin, the wiring resistance of the wiring layer does not increase. Further, an impurity region is formed in the semiconductor film on the concave portion, and a conductor is buried in the concave portion. Therefore, even if the contact hole penetrates through the impurity region, the conductor does not reach the insulating film therebelow because the conductor exists in the concave portion. As a result, the area of the contact portion does not become small, and a low contact resistance can be realized.
図面の簡単な説明  BRIEF DESCRIPTION OF THE FIGURES
第 1図乃至第 3図はそれぞれ従来の S O I型 M O S半導 体装置を示す断面図、 第 4図は本発明の一実施例に係わる S 0 I 型 M O S半導体装置を示す平面パター ン図、 第.5図は前 記第 4図の I 一 I ' 線に沿う断面図、 第 6図及び第 8図はそ れぞれ本発明の一実施例に係わる S 0 I 型 M 0 S半導体装置 の製造方法を説明するための平面パター ン図、 第 7図は前記 第 6図の II 一 Π ' 線に沿う断面図、 第 9図は前記第 8図の m 1 to 3 are cross-sectional views showing a conventional SOI type MOS semiconductor device, respectively. FIG. 4 is a plane pattern diagram showing an SOI type MOS semiconductor device according to one embodiment of the present invention. FIG. 5 is a cross-sectional view taken along the line I-I 'of FIG. 4, and FIGS. FIG. 7 is a cross-sectional view taken along the line II ′ in FIG. 6, and FIG. 9 is a cross-sectional view of FIG.
— m ' 線に沿う断面図である。 FIG. 4 is a cross-sectional view taken along a line m ′.
- 発明を実施するための最良の形態  -Best mode for carrying out the invention
以下、 図面を参照しながら本発明の一実施例について詳 細に説明する。  Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.
第 4図は、 本発明の一実施例に係わる S O I 型 M O S半 導体装置の平面パター ンを示している。 また、 第 5図は、 前 記第 4図の I 一 I ' 線に沿う断面図を示している。  FIG. 4 shows a plane pattern of a SOI type MOS semiconductor device according to one embodiment of the present invention. FIG. 5 is a cross-sectional view taken along the line I-I 'of FIG.
シリ コ ン基板 11上には、 膜厚約 1 mの絶緣膜 （例えば 熱酸化膜、 C V D酸化膜等） 12が形成されている。 この絶緣 膜 12には、 コ ンタク トホ―ル形成領域の直下に凹部 13 aが、 又配線層形成領域に凹部 13bがそれぞれ形成されている。 こ の凹部 13a, 13bには、 例えば不純物がドープされた多結晶 シ リ コ ン （導電体） Ua, b が埋め込まれている。 なお、 凹部 13bに埋め込まれた多結晶シ リ コ ン 14bは、 配線層を構 成している。 また、 絶緣膜 12及び多結晶シ リ コ ン ； a， 14b 上には、 5 0 0人程度の比較的に薄い単結晶シリ コン膜 15が 形成されている。 単結晶シリ コ ン膜 15には、 例えば M O S F E Tが形成されている。 具体的には、 凹部 13a, 13b上を含 む単結晶シリ コン膜 15には、 ソ―ス又は ドレイ ンとしての n + 不純物領域 16が形成されている。 n + 不純物領域 16間のチ ャネル領域上には、 ゲー ト酸化膜 17が形成されている。 ゲー ト酸化膜 17上には、 ゲー ト電極 18が形成されている。 なお、 ゲー ト電極 18は、 不純物が ド―プされた多結晶シリ コ ンから 構成することができる。 M O S F E Tは、 これら n + 不純物 領域 16、 ゲ— 卜酸化膜 17及びゲ— ト電極 18によって構成され ている。 さらに、 全面には、 層間絶緣膜 19が形成されている < 凹部 13a上の層間絶緣膜 19には、 コンタク 卜ホ―ル 20が形成 されている。 ここで、 コ ンタク トホール 20が、 n + 不純物領 域 16を貫通して形成されても、 凹部 13aが存在するため、 絶 緣膜 12に達することはない。 さ らに、 コンタク トホール 20内 には、 A £ 配線 21が形成され、 n + 不純物領域 16と A 配線 21とのコンタク 卜が取られている。 On the silicon substrate 11, an insulating film (for example, a thermal oxide film, a CVD oxide film, etc.) 12 having a thickness of about 1 m is formed. The insulating film 12 has a recess 13 a immediately below the contact hole forming region. Also, recesses 13b are respectively formed in the wiring layer formation region. The recesses 13a and 13b are filled with, for example, polycrystalline silicon (conductor) Ua, b doped with impurities. The polycrystalline silicon 14b buried in the recess 13b forms a wiring layer. On the insulating film 12 and the polycrystalline silicon; a and 14b, a relatively thin single-crystal silicon film 15 of about 500 persons is formed. For example, a MOSFET is formed on the single-crystal silicon film 15. Specifically, n + impurity region 16 as a source or a drain is formed in single crystal silicon film 15 including recesses 13a and 13b. Gate oxide film 17 is formed on the channel region between n + impurity regions 16. On the gate oxide film 17, a gate electrode 18 is formed. The gate electrode 18 can be made of polycrystalline silicon doped with impurities. The MOSFET is composed of the n + impurity region 16, the gate oxide film 17 and the gate electrode 18. Further, an interlayer insulating film 19 is formed on the entire surface. <Contact hole 20 is formed on interlayer insulating film 19 on concave portion 13a. Here, even if the contact hole 20 is formed penetrating the n + impurity region 16, the contact hole 20 does not reach the insulating film 12 because the recess 13 a exists. Further, in the contact hole 20, an A wiring 21 is formed, and a contact between the n + impurity region 16 and the A wiring 21 is taken.
次に、 第 4図乃至第 9図を参照しながら本発明に係わる S 0 I型 M O S半導体装置の製造方法について詳細に説明す る。 ここで、 第 7図は第 6図の Π— II '線に沿う断面図を、 第 9図は第 8図の HI - m ' 線に沿う断面図をそれぞれ示して いる。 Next, a method of manufacturing an S0I type MOS semiconductor device according to the present invention will be described in detail with reference to FIGS. Here, FIG. 7 is a cross-sectional view taken along the line Π—II ′ in FIG. FIG. 9 is a sectional view taken along the line HI-m ′ in FIG.
まず、 第 6図及び第 7図に示すように、 シ リ コ ン基板 1 1 上に膜厚約 1 mの絶緣膜 12を堆積形成する。 また、 コ ン夕 ク トホ -ル形成領域の直下及び配線層形成領域に存在する絶 縁膜 12をフオ ト リ ソグラフエ程により約◦ . エツチン グし、 凹部 13 a, 13 bを形成する。 さ らに、 全面に、 多結晶 シ リ コ ン膜を堆積形成した後、 不純物を ドー ピングする。 ま た、 全面にエッチバッ クを施すことにより、 凹部 13 a, 13 b には不純物が ド―プされた多結晶シ リ コ ン 14a, 14b を埋め 込 、。  First, as shown in FIGS. 6 and 7, an insulating film 12 having a thickness of about 1 m is deposited and formed on a silicon substrate 11. Further, the insulating film 12 existing immediately below the connection hole formation region and in the wiring layer formation region is etched by about ◦ by photolithography to form the concave portions 13a and 13b. In addition, after a polycrystalline silicon film is deposited on the entire surface, impurities are doped. Further, by performing etch-back on the entire surface, polycrystalline silicon 14a, 14b doped with impurities is buried in the recesses 13a, 13b.
次に、 第 8図及び第 9図に示すように、 全面に、 非結晶 シ リ コ ン膜を約 5 ◦ 0人堆積形成する。 こ の後、 レーザァニ ール、 電子ビームァニール等により前記非結晶シリ コ ン膜を 結晶化し、 単結晶シ リ コ ン膜 15を形成する。 また、 こ の単結 晶シリ コ ン膜 15をフォ ト リ ソグラフ工程を用いて島状にエツ チングすることにより、 素子能動領域を形成する。 さ らに、 熱酸化法を用いてゲ- 卜酸化膜 17を形成した後、 全面には、 多結晶シ リ コ ン膜を堆積形成する。 また、 こ の多結晶シリ コ ン膜を導電体にするためリ ン （ P ) を拡散する。 この後、 フ ォ ト リ ソグラフ工程を用いてゲ— ト電極 18及び多結晶シリ コ ン配線 （図示せず） を形成する。 さ らに、 このゲ— 卜電極 18 をマスクにしてリ ン又はヒ素 （A s ) をイオン注入し、 ソー ス又は ド レイ ンと しての n + 不純物領域 16を形成する。  Next, as shown in FIGS. 8 and 9, an amorphous silicon film is deposited on the entire surface by about 5 約 0 people. Thereafter, the amorphous silicon film is crystallized by laser annealing, electron beam annealing, or the like, and a single-crystal silicon film 15 is formed. The element active region is formed by etching the single-crystal silicon film 15 into an island shape using a photolithography process. Further, after the gate oxide film 17 is formed by using the thermal oxidation method, a polycrystalline silicon film is deposited and formed on the entire surface. In addition, phosphorus (P) is diffused to make this polycrystalline silicon film a conductor. Thereafter, a gate electrode 18 and a polycrystalline silicon wiring (not shown) are formed using a photolithographic process. Further, phosphorus or arsenic (As) is ion-implanted using the gate electrode 18 as a mask to form an n + impurity region 16 as a source or a drain.
次に、 第 4図及び第 5図に示すよ う に、 全面に、 層間絶 緣膜 19を堆積形成した後、 フ ォ ト リソグラフエ程を用いて凹 部 13a上の層間絶緣膜 19にコ ンタク 卜ホ―ル 20を形成する。 また、 コ ンタク 卜ホール 20を含む領域に A £ 配線 21を形成し、 n + 不純物領域 16と A 配線 21との接続を取る。 Next, as shown in Fig. 4 and Fig. 5, After depositing and forming the film 19, a contact hole 20 is formed on the interlayer insulating film 19 on the concave portion 13 a by photolithography. Further, an A wiring 21 is formed in a region including the contact hole 20, and the connection between the n + impurity region 16 and the A wiring 21 is established.
このような構成によれば、 配線層 （拡散層配線） は、 薄 く形成された単結晶シリ コ ン膜 15に形成されることなく、 絶 緣膜 12に形成された凹部 13 b中に形成されている。 即ち、 配 線層は、 絶緣膜 12の凹部 13 bに埋め込まれた多結晶シリ コ ン 14b により構成される。 これにより、 配線層の配線抵抗を小 さくすることが可能になると共に、 設計の自由度が上るため 高集積化にとつても有利になる。  According to such a configuration, the wiring layer (diffusion layer wiring) is formed in the recess 13 b formed in the insulating film 12 without being formed in the thin single-crystal silicon film 15. Have been. That is, the wiring layer is composed of the polycrystalline silicon 14b embedded in the recess 13b of the insulating film 12. As a result, the wiring resistance of the wiring layer can be reduced, and the degree of design freedom is increased, which is advantageous for high integration.
また、 A j? 配線 21と n + 不純物領域 16との接铳を取るた めのコンタク トホ—ル 20直下には、 多結晶シリ コ ン 14aの埋 め込まれた凹部 13aが形成されている。 このため、 R I E等 によつて形成されるコンタク トホールは、 ソース又は ドレイ ンとしての n + 不純物領域 16を突き抜けて形成されても、 凹 部 13aに不純物がド―プされた多結晶シ リ コ ン （導電体） 1 4aが存在するため、 その下の絶緣膜 12に達することはない。 よって、 A J2 配線 21と n + 不純物領域 16とのコンタク 卜部分 の面積が小ざく なることはなく、 又 A £ 配線 21と n + 不純物 領域 16とのコンタク ト抵抗が大きく なるのを防ぐことができ なお、 上記実施例では、 nチャネルの S 0 I型 M 0 S半 導体装置について述べてきたが、 pチヤネル型又は相補型の M O S半導体装置であっても本発明を適用できる。 また、 多 結晶シ リ コ ン a， 14bは独自に不純物を ドー ピングして形 成したが、 イオ ン注入法によ り n + 不純物領域 16の形成と同 時に形成してもよい。 さ らに、 凹部 13 a, 13 bに埋め込まれ る導電体は多結晶シ リ コ ンに限らず、 単結晶シ リ コ ン、 非結 晶シ リ コ ン、 シ リ サイ ド、 ポ リ サイ ド、 高融点金属等であつ てもよい。 A recess 13a in which polycrystalline silicon 14a is buried is formed immediately below contact hole 20 for making contact between A j? Interconnection 21 and n + impurity region 16. . Therefore, even if the contact hole formed by RIE or the like penetrates through the n + impurity region 16 as a source or a drain, the polycrystalline silicon in which the impurity is doped in the recess 13a is formed. Since the conductive material 14a is present, it does not reach the insulating film 12 thereunder. Therefore, the area of the contact portion between the A J2 wiring 21 and the n + impurity region 16 is not reduced, and the contact resistance between the A wiring 21 and the n + impurity region 16 is prevented from increasing. In the above embodiment, the n-channel S0I type M0S semiconductor device has been described. However, the present invention can be applied to a p-channel or complementary MOS semiconductor device. Also, many Although the crystalline silicon a and b are formed by doping impurities independently, they may be formed simultaneously with the formation of the n + impurity region 16 by ion implantation. In addition, the conductors embedded in the recesses 13a and 13b are not limited to polycrystalline silicon, but may be single-crystal silicon, amorphous silicon, silicon, and polysilicon. Or high melting point metal.
産業上の利用可能性  Industrial applicability
以上、 説明 したように、 本発明の S O I 型半導体装置及 びその製造方法は、 特に絶緣膜上に形成される単結晶シ リ コ ン膜の膜厚が薄く なつても、 コ ンタ ク ト抵抗を大き く する こ とな く 、 かつ拡散層配線の配線抵抗を大き く する こ とな く製 作する場合に有用である。  As described above, the SOI semiconductor device and the method of manufacturing the same of the present invention can reduce the contact resistance even if the thickness of the single crystal silicon film formed on the insulating film is particularly small. This is useful when manufacturing without increasing the wiring resistance of the diffusion layer wiring without increasing the wiring resistance.

Claims

請求の範囲 The scope of the claims
( 1 ) 半導体基板と、 凹部を有し、 前記半導体基板上に 形成される絶緣膜と、 前記凹部に埋め込まれる導電体と、 前 記铯緣膜上に形成される半導体膜と、 前記半導体膜に形成さ れ、 前記導電体と電気的に接铳される不純物領域とを具備す ることを特徵とする S 0 I型半導体装置。  (1) a semiconductor substrate, an insulating film having a recess, formed on the semiconductor substrate, a conductor embedded in the recess, a semiconductor film formed on the film, and the semiconductor film An S0I type semiconductor device, characterized in that it has an impurity region formed therein and electrically connected to the conductor.
( 2 ) 前記導電体は、 配線層を構成していることを特徵 とする請求項 1記載の S 0 I型半導体装置。  (2) The S0I type semiconductor device according to claim 1, wherein the conductor forms a wiring layer.
( 3 ) 前記導電体は、 不純物を含んだ多結晶シ リ コ ンで あることを特徵とする請求項 1記載の S 0 I型半導体装置。  (3) The S0I type semiconductor device according to claim 1, wherein the conductor is a polycrystalline silicon containing impurities.
( 4 ) 前記半導体膜は、 5 ◦ 0人以下の膜厚を有してい ることを特徵とする請求項 1記載の S 0 I型半導体装置。 (4) The S0I type semiconductor device according to claim 1, wherein the semiconductor film has a thickness of 5 0 or less.
( 5 ) 前記半導体膜は、 単結晶シリ コン膜であることを 特徵とする請求項 1記載の S 0 I型半導体装置。  (5) The SOI semiconductor device according to claim 1, wherein the semiconductor film is a single crystal silicon film.
( 6 ) 前記不純物領域は、 M 0 S F E Tのソ ース又は ド レイ ン領域であることを特徴とする請求項 1記載の S 0 I型 半導体装置。  (6) The S0I type semiconductor device according to claim 1, wherein the impurity region is an M0SFET source or drain region.
( 7 ) 半導体基板と、 凹部を有し、 前記半導体基板上に 形成される絶緣膜と、 前記凹部に埋め込まれる導電体と、 前 記絶緣膜上に形成される半導体膜と、 前記凹部上の前記半導 体膜に形成され、 前記導電体と電気的に接铳される不純物領 域と、 前記凹部上に少なく とも前記不純物領域へ達するコン タク トホールを有し、 全面に形成される層間铯緣膜と、 前記 コンタク トホールを介して前記不純物領域に接続される電極 1 ί (7) a semiconductor substrate, an insulating film having a concave portion, formed on the semiconductor substrate, a conductor embedded in the concave portion, a semiconductor film formed on the insulating film, An impurity region formed in the semiconductor film and electrically connected to the conductor; and a contact hole on the concave portion reaching at least the impurity region. A film and an electrode connected to the impurity region via the contact hole 1 ί
配線とを具備するこ とを特徴とする S O I 型半導体装置。 An SOI type semiconductor device comprising wiring.
(8 ) 前記絶縁膜は、 熱酸化膜又は C V D酸化膜である こ とを特徴とする請求項 7記載の S 0 I 型半導体装置。  (8) The S0I type semiconductor device according to claim 7, wherein the insulating film is a thermal oxide film or a CVD oxide film.
( 9 ) 前記導電体は、 不純物を含んだ多結晶シリ コ ンで あるこ とを特徴とする請求項 7記載の S 0 I 型半導体装置。  (9) The S0I type semiconductor device according to (7), wherein the conductor is a polycrystalline silicon containing impurities.
( 1 0) 前記半導体膜は、 50 O A以下の膜厚を有して いるこ とを特徴とする請求項 7記載の S O I 型半導体装置。 (10) The SOI semiconductor device according to claim 7, wherein the semiconductor film has a thickness of 50 OA or less.
( 1 1 ) 前記半導体膜は、 単結晶シリ コン膜であるこ と を特徴とする請求項 7記載の S 0 I 型半導体装置。 (11) The S0I type semiconductor device according to claim 7, wherein the semiconductor film is a single crystal silicon film.
( 1 2 ) 前記不純物領域は、 M 0 S F E Tのソ ース又は ドレイ ン領域であるこ とを特徴とする請求項 7記載の S O I 型半導体装置。  (12) The SOI semiconductor device according to claim 7, wherein the impurity region is an M0S FET source or drain region.
( 1 3 ) 半導体基板上に絶緣膜を形成する工程と、 この 絶縁膜に凹部を形成する工程と、 この凹部に導電体を埋め込 む工程と、 前記絶緣膜上に半導体膜を形成する工程と、 この 半導体膜に前記導電体と電気的に接続される不純物領域を形 成する工程とを具備するこ とを特徵とする S O I 型半導体装 置の製造方法。  (13) A step of forming an insulating film on a semiconductor substrate, a step of forming a recess in the insulating film, a step of embedding a conductor in the recess, and a step of forming a semiconductor film on the insulating film Forming an impurity region electrically connected to the conductor in the semiconductor film. A method for manufacturing an SOI semiconductor device, comprising the steps of:
( 1 4 ) 前記導電体は、 不純物を含んだ多結晶シリ コ ン であることを特徴とする請求項 1 3記載の S 0 I 型半導体装 置の製造方法。  (14) The method for manufacturing an SOI semiconductor device according to claim 13, wherein the conductor is a polycrystalline silicon containing impurities.
( 1 5) 前記半導体膜は、 50 O A以下の膜厚となるよ うに形成するこ とを特徵とする請求項 1 3記載の S 0 I 型半 導体装置の製造方法。 (15) The S0I type half according to claim 13, wherein the semiconductor film is formed to have a thickness of 50 OA or less. A method for manufacturing a conductor device.
( 1 6 ) 前記半導体膜は、 単結晶シリ コン膜であること を特徴とする請求項 1 3記載の S 0 I型半導体装置の製造方 法 o  (16) The method of manufacturing an SOI semiconductor device according to claim 13, wherein the semiconductor film is a single crystal silicon film.
( 1 7) 前記不純物領域は、 MO S F E Tの ソ ース又は ドレイ ン領域であることを特徴とする請求項 1 3記載の S 0 I型半導体装置の製造方法。  (17) The method for manufacturing an S0I type semiconductor device according to claim 13, wherein the impurity region is a source or drain region of MOS FET.
( 1 8) 半導体基板上に絶緣膜を形成する工程と、 この 絶緣膜に凹部を形成する工程と、 この凹部に導電体を埋め込 む工程と、 前記絶緣膜上に半導体膜を形成する工程と、 前記 凹部上の前記半導体膜に前記導電体と電気的に接続される不 純物領域を形成する工程と、 全面に層間絶緣膜を形成するェ 程と、 前記凹部上の前記層間絶緣膜に少なく とも前記不純物 領域へ達するコンタク 卜ホール形成する工程と、 前記コ ン夕 ク 卜ホール上を含む領域に電極配線を形成する工程とを具俯 することを特徴とする S 0 I型半導体装置の製造方法。  (18) a step of forming an insulating film on the semiconductor substrate, a step of forming a recess in the insulating film, a step of embedding a conductor in the recess, and a step of forming a semiconductor film on the insulating film Forming an impurity region electrically connected to the conductor in the semiconductor film on the recess; forming an interlayer insulating film on the entire surface; and forming the interlayer insulating film on the recess. A step of forming a contact hole reaching at least the impurity region, and a step of forming an electrode wiring in a region including the contact hole. Manufacturing method.
( 1 9 ) 前記導電体は、 不純物を含んだ多結晶シ リ コ ン であることを特徴とする請求項 1 8記載の S 0 I型半導体装 置の製造方法。  (19) The method for manufacturing an SOI semiconductor device according to claim 18, wherein the conductor is a polycrystalline silicon containing impurities.
(2 0 ) 前記半導体膜は、 5 0 0 A以下の膜厚となるよ うに形成することを特徵とする請求項 1 8記載の S 0 I型半 導体装置の製造方法。  (20) The method for manufacturing an SOI semiconductor device according to claim 18, wherein the semiconductor film is formed so as to have a thickness of 500A or less.
(2 1 ) 前記半導体膜は、 単結晶シリ コ ン膜であること を特徴とする請求项 1 8記載の S 0 I型半導体装置の製造方 法。 ( 2 2 ) 前記不純物領域は、 M 0 S F E Tのソ ー ス又は ドレイ ン領域であることを特徴とする請求項 1 8記載の S 0 I型半導体装置の製造方法。 (21) The method for manufacturing an SOI semiconductor device according to claim 18, wherein the semiconductor film is a single crystal silicon film. (22) The method for manufacturing an S0I semiconductor device according to claim 18, wherein the impurity region is a source or drain region of an M0SFET.
PCT/JP1990/001124 1989-09-07 1990-09-04 Soi-type semiconductor device and method of producing the same WO1993017458A1 (en)

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JPS59125663A (en) * 1983-01-05 1984-07-20 Seiko Instr & Electronics Ltd Manufacture of thin film semiconductor device
JPS63265464A (en) * 1987-04-23 1988-11-01 Agency Of Ind Science & Technol Manufacture of semiconductor device

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JPS6194366A (en) * 1984-10-16 1986-05-13 Toshiba Corp Thin-film transistor

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Publication number Priority date Publication date Assignee Title
JPS59125663A (en) * 1983-01-05 1984-07-20 Seiko Instr & Electronics Ltd Manufacture of thin film semiconductor device
JPS63265464A (en) * 1987-04-23 1988-11-01 Agency Of Ind Science & Technol Manufacture of semiconductor device

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