JPH069245B2 - Field effect semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device, and more particularly to a field effect transistor formed on an insulating film, in which a gate portion surrounds a channel region. Is arranged, and the gate portion controls not only the lower surface of the gate portion but also the potential of the entire region surrounded by the gate. Accordingly, the present invention relates to a semiconductor device having significantly improved characteristics as compared with a field effect semiconductor device formed on an insulating film.

(Prior Art) In field-effect transistors, various problems have arisen with the miniaturization of elements. For example, as the channel length of the device becomes shorter, the distance between the source and drain regions becomes smaller, and the punch-through breakdown voltage lowers. In addition, the wiring length becomes longer as the integration of the device becomes higher, which causes a problem such as imbalance between the parasitic capacitance and the current driving force of the device. Usually, the decrease in punch-through breakdown voltage due to the miniaturization of elements is dealt with by increasing the concentration of impurities in the semiconductor substrate, but this has the following drawbacks. Increasing the impurity concentration of the semiconductor substrate causes a decrease in carrier mobility and a decrease in drain breakdown voltage. Therefore, in order to further miniaturize the device, it is necessary to consider another method or a combination thereof. In addition, in the field-effect transistor, a very thin inversion layer (about 100 Å) is formed directly under the gate when the channel part is activated, and it becomes a current channel. The current driving force is low. In particular, the device has become finer and the operating speed of the device itself has become extremely high.However, the wiring length within the device has become longer with higher integration, and this parasitic capacitance and the current driving force of the device have become unbalanced. The delay from balance has not been improved sufficiently, which prevents the high speed operation of the entire device.

In the future, in order to further miniaturize and highly integrate the elements, it is extremely important to increase the speed of the entire device by making it possible to prevent the punch-through breakdown voltage from decreasing and to have a large current driving force (large channel conductance). Becomes an important issue.

(Problems to be Solved by the Invention) The present invention suppresses the above-mentioned lowering of punch-through breakdown voltage, lowering of electric field driving, and lowering of current driving force, which are problems in miniaturizing a field effect transistor. The present invention provides a semiconductor device with dramatically improved element characteristics.

(Operation) Since the semiconductor device according to the present invention is formed on the insulating film substrate, the substrate potential of the device is not fixed. Further, in the semiconductor device according to the present invention, the channel region is surrounded by the gate electrode on at least three sides, and the dimension thereof is, for example, a depletion layer extending from the channel surface when a gate potential is applied so as to invert the channel surface. The gate electrode can suppress the potential of the entire channel region if it is small enough to contact each other before the inversion layer is formed. This is because, in a normal MOS field effect transistor, an insulating layer (O) is formed on the metal layer (M) (gate electrode) so as to activate the channel, as shown in FIG. 3 (a). When a voltage (gate voltage) is applied through the semiconductor layer (S), a very thin inversion layer (30) is formed on the channel surface below the inversion layer, and the electric field lines extending from the gate electrode there are formed. Since it is terminated, the potential on the substrate side cannot be controlled further by the gate electrode.

That is, the inversion layer (30) has a potential (qψ _B ) inside the semiconductor layer (S) that represents a difference between the intrinsic energy level (Ei) and the Fermi energy level (EF) and the intrinsic energy level (Ei).
Of the semiconductor layer (S) and the insulating layer (O) at the interface, that is, the relationship between the surface potential (qψ _S ) and qψ _s >
It occurs when it becomes 2qψ _B. The inversion layer (30) is formed by gradually increasing the voltage applied to the metal layer (M) (gate), and the depth XJ of the inversion layer (30) is usually about 1
It is about 00Å, and when electrons move in the inversion layer (30), a current flows between the source and the drain.

Here, Ec is the energy level of the conduction band, Ev is the energy level of the valence band, and (31) is the depletion layer.

On the other hand, in the semiconductor device according to the present invention, for example, the channel width is so small that the depletion layers are in contact with each other before the inversion layer is formed on the channel surface. Since it does not terminate in, it further penetrates deeply into the channel region, so that the controllability of the channel region polancial by the gate electrode increases accordingly.

That is, as shown in FIG. 3 (b), the channel region (32)
Has a structure in which it is sandwiched between the insulating layer (O) and the metal layer (M) on both sides. Therefore, when the voltage is gradually applied to the metal layer (M), the depletion layer becomes a channel region (32 ) From both sides towards the inside. Then, after the depletion layers extending from both sides are in contact with each other in the channel region, the inversion layer is formed on both sides of the insulating layer.
It is formed on the surface of the channel region under (O). When the gate voltage is further increased, the potential in the channel region increases (the energy level decreases), the entire channel region becomes an inversion layer, and the region that can be used as the channel becomes wider than that of a normal device. . And in the end,
The mobility of electrons inside the channel region is increased, and the current driving force is improved.

Further, in the past, when the gate voltage was cut off, the channel region was affected by the drain voltage, and the punch through phenomenon occurred. On the other hand, in the semiconductor device according to the present invention,
Since the potential of the channel region is controlled by the gate voltage and is not affected by the drain voltage, punch through does not occur. Therefore, the punch-through breakdown voltage is very high, and its current driving force is larger than that of the surface channel conduction type device.

Therefore, according to the present invention, since the punch-through breakdown voltage can be increased without increasing the impurity concentration of the substrate, it is possible to cope with punch-through without lowering the breakdown voltage of the drain. At the same time, since the area that can be used as a channel is expanded, it is possible to make an element having a large current driving force.

(Example) Hereinafter, the present invention will be described in detail with reference to the drawings, taking an N-channel MOSFET as an example.

First, FIGS. 1 (a) and 1 (b) are a perspective view of a semiconductor device according to the present invention and a sectional view taken along line AA 'of this perspective view.

FIG. 1 shows a field effect semiconductor device formed on an insulating film (not shown). Reference numeral (1) denotes a source / drain portion having a width w, and a channel region (3) having a width w (<W) is provided between the source and drain portions. A gate insulating film (4) is provided so as to cover the channel region. Further, a gate electrode (2) is covered thereover to form a gate portion.

Specifically, w is, when a voltage is applied to the gate electrode,
The dimension at which the depletion layer extending in the channel region is in contact with each other before the inversion layer is formed on the surface of the channel region is as follows.

With such a structure, as described above, the gate electrode
Since the inversion layer is effectively formed in the channel region (3) by applying the voltage to (2), the mobility of electrons in this region becomes large and the current driving force can be increased. Further, in the field effect type semiconductor device having such a structure, punch through current is prevented.

Next, a method of manufacturing a semiconductor device according to the present invention will be described.

FIG. 2 is a sectional view of the structural process.

First, as shown in FIG. 2 (a), a silicon oxide film (6) is deposited to a thickness of, for example, 1 μm on the entire surface of a semiconductor substrate (5) by a sputtering method or a CVD method. Then, a polycrystalline silicon oxide film was deposited to a thickness of 8000Å. Then, the polycrystalline silicon film is converted into a single crystallized silicon film by using a beam annealing method or an annealing method using a heater.
(7) A single crystal silicon substrate having an SOI structure was formed.

Next, as shown in FIG. 2 (b), the MOSFET formation region (8) is etched using normal lithography and anisotropic etching until it reaches the silicon oxide film (6) perpendicularly to the substrate to form an island shape. Patterned.

Next, the width of the central part (the part which becomes the gate part) of the MOSFET formation region (8) patterned in the island shape is the first
Etching is performed by the RJE method or the like so as to be smaller than the source and drain formed on both sides as shown in FIG. The width of the central portion (gate portion) at this time is, for example, 1 μm.
It was set to be 1000 Å for the source and drain of m.

Next, as shown in FIG. 2 (c), a gate oxide film (11) is formed to 200 Å by a thermal oxidation method in an oxygen atmosphere, and a polycrystalline silicon film (12) to be a gate electrode is deposited to 4000 Å and deposited. 9
Phosphorus diffusion is performed at 00 degrees to reduce the sheet resistance of the polycrystalline silicon film to 30 ohms or less, and then the normal N-channel MOS
According to the method of forming the FET, the MOSFET forming region is formed.
Patterning was performed so that the central portion of (8) became the gate electrode (12).

At this time, since the width is narrower than that of the source / drain (9) and (10) in the central portion, the MOSFET forming region (8) becomes the channel region. This channel region is formed by the gate oxide film (1
The gate portion is formed by being surrounded by at least three sides by 1) and the polycrystalline silicon film (12) which becomes the gate electrode.

Next, using the gate electrode (12) as a mask, impurity ions are implanted into the source (9) and drain (10) regions by using a normal self-alignment method. Next, a CVD silicon oxide film (13) is added to 40
After depositing 00Å, contact holes reaching the source, drain, and gate are formed in the silicon oxide film by using the ordinary lithography and etching method, and wiring is performed using the metal wiring (14).

Obviously, the present invention can be applied to a P-channel MOSFET simply by changing the conductivity type of the channel.

[Advantages of the Invention] As described above, according to the present invention, the channel width is
For example, in a field effect type semiconductor device having a small size of 1 μm or less, it is possible to obtain a good transistor which has a high current driving force and can suppress punch-through having a good switching characteristic despite the miniaturization of elements.

[Brief description of drawings]

1 (a) and 1 (b) are a perspective view and a sectional view showing an embodiment of a field effect semiconductor device according to the present invention, and FIG. 2 is a view of an embodiment of a field effect semiconductor device according to the present invention. FIG. 3 is a cross-sectional view of a manufacturing process for explaining the operation of the present invention. 1, 9, 10 Source, drain 2, 12 Gate electrode 4 Gate insulating film 3 Channel region 5 Substrate 6 Insulating film

Claims (2)

[Claims] 1. A source / drain portion having a width W is formed in an element forming region on an insulating substrate, and a channel region having a width w (<W) is formed in the element forming region between the source and drain. The opened three directions of the channel region are covered with a gate electrode through an insulating film to form a gate portion, and the width w of the channel region is changed so that an inversion layer is formed on the surface of the channel region. A field-effect-type semiconductor device, characterized in that, when a voltage is applied to the gate electrode, the depletion layer extending inside the channel region has a dimension not more than a size in contact with each other before the inversion layer is formed on the surface of the channel region. 2. The field effect semiconductor device according to claim 1, wherein the width w of the channel region has a thickness of 1000 Å or less.