JPH0685262A - Field effect transistor and its manufacture - Google Patents
Field effect transistor and its manufactureInfo
- Publication number
- JPH0685262A JPH0685262A JP23792092A JP23792092A JPH0685262A JP H0685262 A JPH0685262 A JP H0685262A JP 23792092 A JP23792092 A JP 23792092A JP 23792092 A JP23792092 A JP 23792092A JP H0685262 A JPH0685262 A JP H0685262A
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- insulating film
- semiconductor thin
- thin film
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000005669 field effect Effects 0.000 title claims description 8
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 9
- 238000002955 isolation Methods 0.000 claims abstract description 7
- 239000010408 film Substances 0.000 claims description 27
- 239000010409 thin film Substances 0.000 claims description 16
- 239000004065 semiconductor Substances 0.000 claims description 15
- 239000010410 layer Substances 0.000 claims description 13
- 229920005591 polysilicon Polymers 0.000 claims description 8
- 239000011229 interlayer Substances 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 5
- 239000012535 impurity Substances 0.000 claims description 5
- 239000012212 insulator Substances 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 3
- 230000001590 oxidative effect Effects 0.000 claims description 2
- 239000000758 substrate Substances 0.000 abstract description 23
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 10
- 229910052710 silicon Inorganic materials 0.000 abstract description 10
- 239000010703 silicon Substances 0.000 abstract description 10
- 230000000694 effects Effects 0.000 abstract description 7
- 238000000034 method Methods 0.000 abstract description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 4
- 230000003647 oxidation Effects 0.000 abstract description 2
- 238000007254 oxidation reaction Methods 0.000 abstract description 2
- 239000000969 carrier Substances 0.000 description 6
- 229910052796 boron Inorganic materials 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 230000006798 recombination Effects 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- -1 boron ions Chemical class 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 238000001953 recrystallisation Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78612—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
- H01L29/78615—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect with a body contact
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明はＳＯＩを用いたＭＯＳ電
界効果トランジスタおよびその製造方法に関するもので
ある。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS field effect transistor using SOI and a method for manufacturing the same.
【０００２】[0002]
【従来の技術】絶縁物である酸化シリコンなどの上に形
成されたシリコンなどからなる半導体薄膜の表面をチャ
ネルとするＭＯＳ電界効果トランジスタ（以下、ＳＯＩ
ＭＯＳＦＥＴという）はシリコン基板表面をチャネルと
するバルクＭＯＳＦＥＴに比べて、短チャネル効果に強
く、スイッチング速度が速くなるなどの利点がある。2. Description of the Related Art A MOS field effect transistor (hereinafter referred to as SOI) having a channel on the surface of a semiconductor thin film made of silicon or the like formed on an insulating material such as silicon oxide.
Compared with a bulk MOSFET having a silicon substrate surface as a channel, the MOSFET has a short channel effect, and has an advantage that a switching speed is increased.
【０００３】しかし、ＳＯＩＭＯＳＦＥＴではシリコン
薄膜（以下、基板という）に電極を接続して基板電位を
固定することが難しいので、通常、浮遊電位のまま動作
させている。そのため基板に少数キャリアが蓄積すると
基板電位が変動し、その結果ＭＯＳＦＥＴの特性が変化
するという欠点がある。However, since it is difficult to fix the substrate potential by connecting an electrode to a silicon thin film (hereinafter referred to as a substrate) in the SOI MOSFET, the SOI MOSFET is normally operated with a floating potential. Therefore, when minority carriers are accumulated in the substrate, the substrate potential fluctuates, and as a result, the characteristics of the MOSFET change.
【０００４】従来は、少数キャリア発生の原因となるイ
ンパクトイオン化を抑制するため、高濃度ドレインに隣
接して低濃度ドレインを形成するＬＤＤ構造を適用した
り、発生した少数キャリアをソース領域に引き込んで、
再結合によって消滅させる再結合中心となる金属をソー
ス領域に導入して、この浮遊基板効果を抑制している。Conventionally, in order to suppress impact ionization that causes generation of minority carriers, an LDD structure in which a low-concentration drain is formed adjacent to a high-concentration drain is applied, or the generated minority carriers are drawn into a source region. ,
This floating substrate effect is suppressed by introducing into the source region a metal serving as a recombination center that disappears by recombination.
【０００５】[0005]
【発明が解決しようとする課題】ＳＯＩＭＯＳＦＥＴの
浮遊基板効果を抑制するため、ＬＤＤ構造にすると低濃
度ドレインの抵抗成分のためＭＯＳＦＥＴの電流駆動能
力が低下する。そのため本来のＳＯＩＭＯＳＦＥＴの利
点である速いスイッチ速度を遅くしてしまうという問題
がある。When the LDD structure is used to suppress the floating substrate effect of the SOIMOSFET, the current driving capability of the MOSFET is lowered due to the resistance component of the lightly doped drain. Therefore, there is a problem that the fast switching speed, which is the original advantage of the SOIMOSFET, is reduced.
【０００６】また、ソース領域に再結合中心を導入して
少数キャリアをソースに引き抜こうとしても、少数キャ
リアの発生はドレイン端で生じるのでソースに到達する
までに少数キャリアの一部が基板に蓄積する。ＭＯＳＦ
ＥＴ特性の変動は小さくなっても残ってしまうという問
題がある。これらの問題はＳＯＩＭＯＳＦＥＴにおいて
は基板電極を形成することが困難であることから生じ
る。Further, even if the recombination center is introduced into the source region to extract the minority carriers to the source, the minority carriers are generated at the drain end, so that some of the minority carriers are accumulated in the substrate before reaching the source. To do. MOSF
There is a problem that the fluctuation of the ET characteristic remains even if it becomes small. These problems arise from the difficulty in forming the substrate electrode in SOI MOSFETs.
【０００７】また、基板電極を形成したとしても、その
領域を設けた分だけチップ面積が増えてしまうという問
題が生じる。Further, even if the substrate electrode is formed, there is a problem that the chip area is increased by the amount of the area provided.
【０００８】本発明の目的は、チップ面積を増やすこと
なく基板電極を形成すると同時にスイッチ速度の高速化
を実現した電界効果トランジスタおよびその製造方法を
提供することにある。It is an object of the present invention to provide a field effect transistor which can form a substrate electrode without increasing the chip area and at the same time realizes a high switching speed, and a method of manufacturing the same.
【０００９】[0009]
【課題を解決するための手段】本発明の電界効果トラン
ジスタは、絶縁物の上に半導体薄膜、ゲート絶縁膜およ
びゲート電極が順次積層され、前記ゲート電極および前
記ゲート絶縁膜に形成されたコンタクトを覆う金属配線
によって、前記ゲート電極と前記半導体薄膜とが電気的
に接続されたものである。In the field effect transistor of the present invention, a semiconductor thin film, a gate insulating film, and a gate electrode are sequentially laminated on an insulator, and a contact formed on the gate electrode and the gate insulating film is formed. The gate electrode and the semiconductor thin film are electrically connected by a covering metal wiring.
【００１０】また、本発明の電界効果トランジスタの製
造方法は、絶縁物の上に形成された一導電型半導体薄膜
を選択酸化して素子分離酸化膜を形成する工程と、前記
素子分離酸化膜に囲まれて残された前記半導体薄膜の表
面にゲート絶縁膜を形成したのち全面にポリシリコンを
堆積する工程と、前記ポリシリコンおよび前記ゲート絶
縁膜をパターニングして、前記半導体薄膜表面に達する
第１のコンタクト開口を有する前記ポリシリコンからな
るゲート電極を形成する工程と、逆導電型不純物をイオ
ン注入して前記ゲート電極両側の直下の前記半導体薄膜
にソース・ドレイン層を形成する工程と、全面に層間絶
縁膜を堆積したのち前記第１のコンタクト開口の内側に
第２のコンタクト開口を形成する工程と、一導電型不純
物をイオン注入して前記第２のコンタクト開口の前記半
導体薄膜にオーミック層を形成する工程と、前記ゲート
電極および前記オーミック層に接する前記第２のコンタ
クト開口近傍の絶縁膜をエッチングする工程とを含むも
のである。The method of manufacturing a field effect transistor according to the present invention further comprises a step of selectively oxidizing one conductivity type semiconductor thin film formed on an insulator to form an element isolation oxide film, and a step of forming the element isolation oxide film. A step of forming a gate insulating film on the surface of the semiconductor thin film left surrounded and then depositing polysilicon on the entire surface, and patterning the polysilicon and the gate insulating film to reach the surface of the semiconductor thin film. Forming a gate electrode made of the polysilicon having a contact opening, forming a source / drain layer in the semiconductor thin film immediately below both sides of the gate electrode by ion-implanting an impurity of opposite conductivity type, and A step of forming a second contact opening inside the first contact opening after depositing an interlayer insulating film, and ion-implanting one conductivity type impurity Wherein forming an ohmic layer on the semiconductor thin film of the second contact opening, the second contact opening near the insulating film in contact with the gate electrode and the ohmic layer is intended to include the step of etching.
【００１１】[0011]
【作用】ＮチャネルＭＯＳＦＥＴのドレイン電流とゲー
ト電圧との関係を図３に示す。基板にゲート電圧と同一
極性の１Ｖを印加すると、破線に示すようにＭＯＳＦＥ
Ｔのしきい値電圧が下がってドレイン電流が増大すると
同時に、ゲート電圧０Ｖのオフ時のリーク電流が増大す
る。The relationship between the drain current and the gate voltage of the N-channel MOSFET is shown in FIG. When 1V with the same polarity as the gate voltage is applied to the substrate, the MOSFE
At the same time as the threshold voltage of T decreases and the drain current increases, the leak current when the gate voltage 0V is off increases.
【００１２】一方、基板とゲート電極とをショート（短
絡）すると実線に示すように変る。ゲート電圧０Ｖにお
ける漏れ電流は十分に小さいうえ、ドレイン電流に対す
るゲート電圧特性の勾配が急峻になるのでＦＥＴのＯＮ
（オン）状態とＯＦＦ（オフ）状態との区別がより明確
になる。さらにＦＥＴがオン状態のときのドレイン電流
が増大してスイッチング特性が向上する。On the other hand, when the substrate and the gate electrode are short-circuited (short circuit), the change occurs as shown by the solid line. The leakage current at a gate voltage of 0V is sufficiently small, and the slope of the gate voltage characteristic with respect to the drain current becomes steep, so the FET is turned on.
The distinction between the (on) state and the off (off) state becomes clearer. Further, the drain current when the FET is in the ON state is increased, and the switching characteristics are improved.
【００１３】チップ面積を増やすことなく、基板に電極
を形成してゲート電極と接続することができる。その結
果、ＳＯＩＭＯＳＦＥＴの問題点である浮遊基板効果を
抑制するとともに、ＦＥＴの高速化が可能になる。An electrode can be formed on the substrate and connected to the gate electrode without increasing the chip area. As a result, the floating substrate effect, which is a problem of the SOIMOSFET, can be suppressed and the speed of the FET can be increased.
【００１４】[0014]
【実施例】本発明の一実施例について、図２（ａ）〜
（ｇ）を参照して工程順に説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention is shown in FIGS.
The process order will be described with reference to FIG.
【００１５】はじめに平面図である図２（ａ）およびそ
の断面図である図２（ｂ）に示すように、Ｐ型シリコン
からなる下地ウェーハ１に酸化シリコン膜２で絶縁分離
されたＰ型シリコン層３が形成されている、Ｐ型ＳＯＩ
基板を用いる。ＳＯＩ基板は酸素イオン注入によるＳＩ
ＭＯＸ（Ｓｅｐａｒａｔｉｏｎ ｂｙ Ｉｍｐｌａｎｔ
ｅｄ Ｏｘｙｇｅｎ）または、レーザ、電子ビームやラ
ンプアニールによって再結晶するＺＭＲ（Ｚｏｎｅ Ｍ
ｅｌｔｉｎｇ Ｒｅｃｒｙｓｔａｌｌｉｚａｔｉｏｎ）
などで形成される。つぎに選択酸化法により素子分離用
酸化膜４を形成して素子領域となるＰ型シリコン層３を
絶縁分離する。このとき図２（ａ）に示すように、ゲー
ト電極のコンタクト予定領域までＰ型シリコン層３を残
して凸型にしたことに特徴がある。First, as shown in FIG. 2 (a) which is a plan view and FIG. 2 (b) which is a cross-sectional view thereof, a P-type silicon insulatingly separated by a silicon oxide film 2 is formed on a base wafer 1 made of P-type silicon. P-type SOI with layer 3 formed
A substrate is used. SOI substrate is SI by oxygen ion implantation
MOX (Separation by Implant)
ed Oxygen) or ZMR (Zone M) recrystallized by laser, electron beam or lamp annealing.
eluting Recrystallization)
And so on. Next, an element isolation oxide film 4 is formed by a selective oxidation method to insulate and isolate the P-type silicon layer 3 to be an element region. At this time, as shown in FIG. 2A, it is characterized in that the P-type silicon layer 3 is left to reach the contact planned region of the gate electrode to form a convex shape.
【００１６】つぎに平面図である図２（ｃ）およびその
断面図である図２（ｄ）に示すように、ゲート酸化膜５
を形成したのちしきい値電圧を調整するためボロン（硼
素）をイオン注入する。つぎに燐をドープしたポリシリ
コンを形成してからパターニングしてゲート電極６を形
成する。ポリシリコンをパターニングするとき、同時に
ゲート電極６にコンタクト１１を開口する。Next, as shown in a plan view of FIG. 2C and a sectional view of FIG. 2D, the gate oxide film 5 is formed.
Then, boron (ion) is ion-implanted to adjust the threshold voltage. Next, phosphorus-doped polysilicon is formed and then patterned to form the gate electrode 6. At the same time when the polysilicon is patterned, the contact 11 is opened in the gate electrode 6.
【００１７】つぎに平面図である図２（ｅ）およびその
断面図である図２（ｆ）に示すように、砒素をイオン注
入してＮ+ 型ソース・ドレイン拡散層７を形成する。つ
ぎに全面に厚さ０．４μｍの層間絶縁膜８を堆積したの
ち、レジスト（図示せず）をマスクとしてエッチングし
てコンタクト１２を開口する。このときコンタクト１２
はゲート電極６と同時にパターニングしたコンタクト１
１よりもひとまわり小さくして、コンタクト１２の側面
に層間絶縁膜８からなる厚さ約０．１μｍの側壁が残る
ようにする。このあとボロンをイオン注入したとき、ゲ
ート電極６にボロンが侵入しないようにするためであ
る。Next, as shown in a plan view of FIG. 2E and a sectional view of FIG. 2F, arsenic is ion-implanted to form an N + type source / drain diffusion layer 7. Next, after depositing an interlayer insulating film 8 having a thickness of 0.4 μm on the entire surface, the contact 12 is opened by etching using a resist (not shown) as a mask. Contact 12 at this time
Is the contact 1 patterned at the same time as the gate electrode 6
It is made slightly smaller than 1 so that the side wall of the interlayer insulating film 8 having a thickness of about 0.1 μm remains on the side surface of the contact 12. This is to prevent boron from entering the gate electrode 6 when boron is ion-implanted thereafter.
【００１８】つぎに平面図である図２（ｇ）およびその
断面図である図２（ｈ）に示すように、ボロンをイオン
注入したのちアニールして基板電極予定領域にＰ+ 型オ
ーミック拡散層９を形成する。つぎにコンタクト１２の
側面に残っている層間絶縁膜８などからなる絶縁膜をエ
ッチングする。Next, as shown in a plan view of FIG. 2 (g) and a sectional view of FIG. 2 (h), boron ions are implanted and then annealed to form a P + -type ohmic diffusion layer in the substrate electrode planned region. 9 is formed. Next, the insulating film formed of the interlayer insulating film 8 and the like remaining on the side surface of the contact 12 is etched.
【００１９】最後に平面図である図１（ａ）およびその
断面図である図１（ｂ）に示すように、スパッタ法によ
り全面にＡｌ（アルミニウム）系合金を堆積したのち、
パターニングしてＡｌ配線１０を形成して素子部が完成
する。Finally, as shown in a plan view of FIG. 1A and a sectional view of FIG. 1B, an Al (aluminum) type alloy is deposited on the entire surface by a sputtering method,
The Al wiring 10 is formed by patterning to complete the element portion.
【００２０】本実施例ではＮチャネルのＦＥＴについて
説明したが、本発明はＮチャネルに限定されることなく
極性を変えることによりＰチャネルのＦＥＴにも適用す
ることができる。さらにＮチャネルおよびＰチャネルの
ＦＥＴが共存するＣＭＯＳ集積回路に適用しても同様の
効果を得ることができる。Although the N-channel FET has been described in this embodiment, the present invention is not limited to the N-channel FET and can be applied to the P-channel FET by changing the polarity. Further, the same effect can be obtained even when applied to a CMOS integrated circuit in which N-channel and P-channel FETs coexist.
【００２１】[0021]
【発明の効果】基板とゲート電極とを短絡することによ
り、チップ面積を増やすことなくＳＯＩＭＯＳＦＥＴの
問題点である浮遊基板効果を抑制することができる。さ
らにＦＥＴのオン状態とオフ状態との区別が明確にな
り、オン状態のドレイン電流が増加して、ＦＥＴの高速
動作が可能になった。By short-circuiting the substrate and the gate electrode, the floating substrate effect, which is a problem of the SOIMOSFET, can be suppressed without increasing the chip area. Furthermore, the distinction between the on-state and the off-state of the FET has been clarified, the drain current in the on-state has increased, and high-speed operation of the FET has become possible.
【００２２】しかもレジスト工程を追加することなく、
自己整合的に基板コンタクト領域の不純物濃度を上げ
て、コンタクト抵抗を低減することができる。Moreover, without adding a resist process,
The contact resistance can be reduced by increasing the impurity concentration in the substrate contact region in a self-aligning manner.
【図１】（ａ）は本発明の一実施例を示す平面図であ
る。（ｂ）は（ａ）の断面図である。FIG. 1A is a plan view showing an embodiment of the present invention. (B) is sectional drawing of (a).
【図２】（ａ），（ｃ），（ｅ），（ｇ）は本発明の一
実施例を工程順に示す平面図である。（ｂ），（ｄ），
（ｆ），（ｈ）は本発明の一実施例を工程順に示す断面
図である。2 (a), (c), (e) and (g) are plan views showing an embodiment of the present invention in the order of steps. (B), (d),
(F), (h) is sectional drawing which shows one Example of this invention in order of process.
【図３】ＦＥＴのゲート電圧に対するドレイン電流の特
性を示すグラフである。FIG. 3 is a graph showing characteristics of drain current with respect to gate voltage of FET.
１ 下地ウェーハ ２ 酸化シリコン膜 ３ Ｐ型シリコン層 ４ 素子分離酸化膜 ５ ゲート酸化膜 ６ ゲート電極 ７ Ｎ+ 型ソース・ドレイン ８ 層間絶縁膜 ９ Ｐ+ 型拡散層 １０ Ａｌ配線 １１，１２ コンタクト1 Base Wafer 2 Silicon Oxide Film 3 P-Type Silicon Layer 4 Element Isolation Oxide Film 5 Gate Oxide Film 6 Gate Electrode 7 N + Type Source / Drain 8 Interlayer Insulation Film 9 P + Type Diffusion Layer 10 Al Wiring 11, 12 Contacts
Claims (2)
およびゲート電極が順次積層され、前記ゲート電極およ
び前記ゲート絶縁膜に形成されたコンタクトを覆う金属
配線によって、前記ゲート電極と前記半導体薄膜とが電
気的に接続された電界効果トランジスタ。1. A semiconductor thin film, a gate insulating film, and a gate electrode are sequentially laminated on an insulator, and the gate electrode and the semiconductor thin film are formed by metal wiring covering the gate electrode and the contact formed on the gate insulating film. A field effect transistor in which and are electrically connected.
薄膜を選択酸化して素子分離酸化膜を形成する工程と、
前記素子分離酸化膜に囲まれて残された前記半導体薄膜
の表面にゲート絶縁膜を形成したのち、全面にポリシリ
コンを堆積する工程と、前記ポリシリコンおよび前記ゲ
ート絶縁膜をパターニングして、前記半導体薄膜表面に
達する第１のコンタクト開口を有する前記ポリシリコン
からなるゲート電極を形成する工程と、逆導電型不純物
をイオン注入して前記ゲート電極両側の直下の前記半導
体薄膜にソース・ドレイン層を形成する工程と、全面に
層間絶縁膜を堆積したのち前記第１のコンタクト開口の
内側に第２のコンタクト開口を形成する工程と、一導電
型不純物をイオン注入して前記第２のコンタクト開口の
前記半導体薄膜にオーミック層を形成する工程と、前記
ゲート電極および前記オーミック層に接する前記第２の
コンタクト開口近傍の絶縁膜をエッチングする工程とを
含む電界効果トランジスタの製造方法。2. A step of selectively oxidizing one conductivity type semiconductor thin film formed on an insulator to form an element isolation oxide film,
Forming a gate insulating film on the surface of the semiconductor thin film left surrounded by the element isolation oxide film, depositing polysilicon on the entire surface, and patterning the polysilicon and the gate insulating film, Forming a gate electrode made of the polysilicon having a first contact opening reaching the surface of the semiconductor thin film; and ion-implanting an impurity of opposite conductivity type to form a source / drain layer in the semiconductor thin film immediately below both sides of the gate electrode. A step of forming a second contact opening inside the first contact opening after depositing an interlayer insulating film on the entire surface, and ion-implanting one conductivity type impurity into the second contact opening. Forming an ohmic layer on the semiconductor thin film, and near the second contact opening in contact with the gate electrode and the ohmic layer. Method of manufacturing a field effect transistor comprising the step of etching the insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4237920A JP2903892B2 (en) | 1992-09-07 | 1992-09-07 | Method for manufacturing field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4237920A JP2903892B2 (en) | 1992-09-07 | 1992-09-07 | Method for manufacturing field effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0685262A true JPH0685262A (en) | 1994-03-25 |
| JP2903892B2 JP2903892B2 (en) | 1999-06-14 |
Family
ID=17022412
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4237920A Expired - Lifetime JP2903892B2 (en) | 1992-09-07 | 1992-09-07 | Method for manufacturing field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2903892B2 (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000001015A1 (en) * | 1998-06-30 | 2000-01-06 | Sharp Kabushiki Kaisha | Semiconductor device and method of manufacture thereof |
| US6172405B1 (en) | 1998-07-17 | 2001-01-09 | Sharp Kabushiki Kaisha | Semiconductor device and production process therefore |
| US6177811B1 (en) | 1995-06-06 | 2001-01-23 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit device |
| US6191449B1 (en) * | 1996-09-19 | 2001-02-20 | Kabushiki Kaisha Toshiba | SOI based transistor having an independent substrate potential control |
| US6255704B1 (en) | 1996-06-28 | 2001-07-03 | Sharp Kabushiki Kaisha | Semiconductor device and method for fabricating the same |
| JP2002509360A (en) * | 1997-12-16 | 2002-03-26 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | Silicon oxide insulator (SOI) semiconductor having a selectively connected body |
| US6841828B2 (en) | 1997-02-28 | 2005-01-11 | Kabushiki Kaisha Toshiba | Method of manufacturing SOI element having body contact |
| JP2005123565A (en) * | 2003-10-16 | 2005-05-12 | Samsung Sdi Co Ltd | Gate body contact thin film transistor |
| JP2007324530A (en) * | 2006-06-05 | 2007-12-13 | Oki Electric Ind Co Ltd | Semiconductor device |
| US11715796B2 (en) | 2021-03-12 | 2023-08-01 | Kabushiki Kaisha Toshiba | High frequency transistor |
-
1992
- 1992-09-07 JP JP4237920A patent/JP2903892B2/en not_active Expired - Lifetime
Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6177811B1 (en) | 1995-06-06 | 2001-01-23 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit device |
| US6573577B1 (en) | 1996-06-28 | 2003-06-03 | Sharp Kabushiki Kaisha | Semiconductor device and method for fabricating the same |
| KR100330782B1 (en) * | 1996-06-28 | 2002-08-13 | 샤프 가부시키가이샤 | Semiconductor device and manufacturing method thereof |
| US6927463B2 (en) | 1996-06-28 | 2005-08-09 | Sharp Kabushiki Kaisha | Semiconductor device and method for fabricating the same |
| US6255704B1 (en) | 1996-06-28 | 2001-07-03 | Sharp Kabushiki Kaisha | Semiconductor device and method for fabricating the same |
| KR100387902B1 (en) * | 1996-06-28 | 2003-06-18 | 샤프 가부시키가이샤 | semiconductor device and method for fabricating the same |
| US6191449B1 (en) * | 1996-09-19 | 2001-02-20 | Kabushiki Kaisha Toshiba | SOI based transistor having an independent substrate potential control |
| US6841828B2 (en) | 1997-02-28 | 2005-01-11 | Kabushiki Kaisha Toshiba | Method of manufacturing SOI element having body contact |
| JP2002509360A (en) * | 1997-12-16 | 2002-03-26 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | Silicon oxide insulator (SOI) semiconductor having a selectively connected body |
| US6426532B1 (en) | 1998-06-30 | 2002-07-30 | Sharp Kabushiki Kaisha | Semiconductor device and method of manufacture thereof |
| WO2000001015A1 (en) * | 1998-06-30 | 2000-01-06 | Sharp Kabushiki Kaisha | Semiconductor device and method of manufacture thereof |
| US6682966B2 (en) | 1998-06-30 | 2004-01-27 | Sharp Kabushiki Kaisha | Semiconductor device and method for producing the same |
| US6172405B1 (en) | 1998-07-17 | 2001-01-09 | Sharp Kabushiki Kaisha | Semiconductor device and production process therefore |
| JP2005123565A (en) * | 2003-10-16 | 2005-05-12 | Samsung Sdi Co Ltd | Gate body contact thin film transistor |
| US8704305B2 (en) | 2003-10-16 | 2014-04-22 | Samsung Display Co., Ltd. | Thin film transistor |
| JP2007324530A (en) * | 2006-06-05 | 2007-12-13 | Oki Electric Ind Co Ltd | Semiconductor device |
| US11715796B2 (en) | 2021-03-12 | 2023-08-01 | Kabushiki Kaisha Toshiba | High frequency transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2903892B2 (en) | 1999-06-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5266515A (en) | Fabricating dual gate thin film transistors | |
| KR0134756B1 (en) | Semiconductor device and manufacture method thereof | |
| US5804858A (en) | Body contacted SOI MOSFET | |
| JP2835216B2 (en) | Method for manufacturing semiconductor device | |
| US5214295A (en) | Thin film field effect transistor, CMOS inverter, and methods of forming thin film field effect transistors and CMOS inverters | |
| JP3455452B2 (en) | Semiconductor device and manufacturing method thereof | |
| EP0962988A2 (en) | SOI semiconductor device and method for manufacturing the same | |
| US5286663A (en) | Methods for producing thin film transistor having a diode shunt | |
| US6166412A (en) | SOI device with double gate and method for fabricating the same | |
| JPH10294465A (en) | Semiconductor device | |
| JP3103159B2 (en) | Semiconductor device | |
| JP2001156290A (en) | Semiconductor device | |
| JP2903892B2 (en) | Method for manufacturing field effect transistor | |
| JP4348757B2 (en) | Semiconductor device | |
| JP3057436B2 (en) | Semiconductor device and manufacturing method thereof | |
| JPH06268215A (en) | Mis type semiconductor device | |
| JPH05102179A (en) | Semiconductor device and its manufacture | |
| US6621118B2 (en) | MOSFET, semiconductor device using the same and production process therefor | |
| JP3057792B2 (en) | Method for manufacturing thin film transistor | |
| JPH09135029A (en) | Mis semiconductor device and manufacturing method therefor | |
| US20010001497A1 (en) | Semiconductor device and method for manufacturing the same | |
| JP2519541B2 (en) | Semiconductor device | |
| JPH0766296A (en) | Mis semiconductor device and manufacture thereof | |
| JPH09181313A (en) | Manufacturing method for mosfet | |
| JP3260200B2 (en) | Method for manufacturing semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19990223 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080326 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090326 Year of fee payment: 10 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090326 Year of fee payment: 10 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100326 Year of fee payment: 11 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100326 Year of fee payment: 11 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110326 Year of fee payment: 12 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110326 Year of fee payment: 12 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120326 Year of fee payment: 13 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120326 Year of fee payment: 13 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130326 Year of fee payment: 14 |
|
| EXPY | Cancellation because of completion of term | ||
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130326 Year of fee payment: 14 |