WO2001057930A1

WO2001057930A1 - Semiconductor device and its manufacturing method

Info

Publication number: WO2001057930A1
Application number: PCT/JP2000/000564
Authority: WO
Inventors: Tsuyoshi Kachi; Dai Hisamoto
Original assignee: Hitachi, Ltd.
Priority date: 2000-02-02
Filing date: 2000-02-02
Publication date: 2001-08-09
Also published as: TW454296B; AU2000223245A1

Abstract

The electric connection with the diffused layer formed in an SOI layer of a semiconductor element having the SOI layer, especially an SOI MISFET is realized through an electrode comprising a silicon-containing semiconductor layer in contact with a side face of the SOI layer and a metallic layer in contact with the silicon-containing semiconductor layer. The area of the contact between the metallic layer and the silicon-containing semiconductor layer is larger than that between the SOI layer and the silicon-containing semiconductor layer. Even if the SOI layer is redesigned to a thinner one, the parastic resistance of the source/drain hardly increases. A method for manufacturing a semiconductor device involves no photomask having openings for the source and drain, and the SOI MISFET can be further microminiaturized, thus manufacturing a highly-integrated semiconductor device.

Description

Description Semiconductor device and manufacturing method thereof [Technical field]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having an SOI (Silicon On Insulator) structure.

(Background technology)

In order to increase the speed and reduce the power consumption of semiconductor integrated circuits using MISFETs (Metal Insulator Semiconductor Field Effect Transistors), MIS FETs with an SOI structure that can reduce parasitic capacitance are attracting attention.

In particular, the MISF ET, in which the channel region is completely depleted by making the thickness of the SOI layer extremely small to several tens of nm or less, the so-called fully depleted SOI MISFET, has a neutral region in the channel region. In comparison with partially depleted SOI MI SFETs, the parasitic capacitance of the source and drain can be reduced, and steep subthreshold characteristics can be obtained.

However, in such a fully depleted SO I MIS FET, since the thickness of the source and drain regions is determined by the thickness of the SO I layer, the thickness of the S I I layer is lower than that of the MIS FET using a Balta substrate. The source / drain resistance created by the diffusion layer of this type increases, and in particular, the increase in source resistance has the problem that the current driving capability of the MISFET is significantly reduced. The reasons for the increase in parasitic resistance at the source and drain are considered as follows.

The source-drain parasitic resistance can be broadly divided into the so-called diffusion layer resistance and the contact resistance between the diffusion layer and the metal layer that is the wiring. The resistance of the metal layer is negligible compared to these.

FIG. 1 is a cross-sectional view of a MISFET using a bulk substrate. 500 is a gate electrode, 1200 is a source / drain diffusion layer formed in a silicon substrate, and 110 is a metal layer made of silicide formed on the surface of the source / drain diffusion layer. Also, the arrows in FIGS. 1 and 1 indicate the current path from the channel in the diffusion layer 1200 to the metal layer 110 when a current flows from the wiring 1306 to the wiring 1305. The thick dotted line indicates the surface of the contact surface between the metal layer 110 and the diffusion layer 1200 through which current flows. In the MISFET using a bulk substrate, the current path described above largely spreads in the diffusion layer 1200 so as to have a wider passage surface because of the large contact resistance between metal and silicon. Such a passing surface becomes an electrically effective contact area. Therefore, even if the contact resistance is large, the effective contact area is large, and the parasitic resistance can be reduced.

On the other hand, in a fully depleted SOIMISFET, as shown in Fig. 2, since there is an insulating layer (buried oxide film) 190, the insulating layer (buried oxide film) 190 and the metal layer 1 The diffusion layer 1 200 in the portion sandwiched by 100 becomes thin, and the diffusion layer resistance in this portion is extremely large as indicated by the symbol R in the figure. Become. For this reason, the current path indicated by the arrow The current passing surface of the contact surface between the metal layer 110 and the diffusion layer 1200 concentrates on an extremely narrow portion as shown by a thick dotted line. In other words, the effective contact area becomes extremely small, and the contact resistance between the large metal and silicon strongly controls the parasitic resistance. In other words, reducing the thickness of the SOI layer leads to a large increase in parasitic resistance.

Conventional techniques for solving the problem of increased parasitic resistance include, for example, a method of thinning the surface of the source / drain region into silicide (Imai et al., 1998 Symposium on VSI Technology, Digest p.ii6), A method of thinning the SOI layer only in the region (M. Chan et al., 1994 i-triple electron device letter vol.15 p.24) has been proposed. However, these conventional techniques cannot be applied when the thickness of the SOI layer is further reduced, so that the problem has not been essentially solved.

Also, a conventional technique of forming a contact hole reaching an insulating layer (buried oxide film) below an SOI layer, filling the contact hole with a metal layer, and making an electrical connection from a side surface of the SOI layer is disclosed in Japanese Unexamined Patent Application Publication No. No. 2,754,336, Japanese Patent Application Laid-Open No. Hei 5-344742, and Japanese Patent Application Laid-Open No. 10-70281. However, in these conventional technologies, the effective contact area between the diffusion layer and the gold layer is wider than that of the conventional technology described in Fig. 2, but the contact area depends on the thickness of the SOI layer. Therefore, there is no fundamental solution to the increase in parasitic resistance due to the thinning of the SOI layer. [Disclosure of the Invention]

A first object of the present invention is to provide a semiconductor device having a high-performance SOI MISFET that can prevent an increase in source / drain parasitic resistance even when the SOI layer becomes thin. It is in.

A second object of the present invention is to provide a method of manufacturing a semiconductor device suitable for miniaturizing the SOI MISFET.

The first object is to provide a contact hole exposing the side surface of the SOI layer and a silicon-containing semiconductor layer formed on the bottom surface and the side surface of the contact hole (for example, a polycrystalline silicon film or a silicon-germ film mixture). And a metal film formed so as to fill the contact hole on the silicon-containing semiconductor layer, and the electrical connection with the source / drain of the SOI MISFET is made from the side of the SOI layer. This is achieved by a semiconductor device having a structured structure.

According to the semiconductor device of the present invention, the side surface of the SOI layer is in contact with the semiconductor layer containing silicon, and the contact resistance at this contact surface is smaller than the contact resistance between the SOI layer and the metal layer. Since it is very small, the increase in the contact resistance component when the SOI layer is thinned can be minimized. In addition, although the contact resistance between the semiconductor layer containing silicon and the metal layer was large in the past, the content of impurities and the thickness of the semiconductor layer containing silicon can be controlled appropriately to control the semiconductor containing silicon. The resistance of the layer can be reduced, the current path can be widened sufficiently in the semiconductor layer containing silicon, the effective contact area with the metal layer can be increased, and the overall parasitic resistance can be reduced. it can. Further, the second object is to provide a step of forming an SOI MISFET in which at least the side surface and the upper side of the gate electrode are covered with a first insulating film, and an etching selectivity with respect to the first insulating film. Depositing a second insulating film, and etching the second insulating film using a resist U having an opening facing the SOI layer of the SOI MI SFET including a portion above the gate electrode as a mask. Forming a contact hole exposing each of the source and drain diffusion layers of the SOI layer; and depositing a silicon-containing semiconductor layer on the inner surface of the contact hole and the second insulating film. A step of depositing a metal layer so as to be buried, a step of polishing by a CMP method until the semiconductor layer containing silicon on the first and second insulating films is exposed, and a step of polishing the semiconductor layer containing silicon by an upper surface thereof. First and second absolute Is by connexion achieved a method of manufacturing a semiconductor device including the step of etching until the lower than the upper surface of the film.

According to the method of manufacturing a semiconductor device of the present invention, instead of forming a contact hole for each of the source and drain of the SOI MISFET, a large contact hole is formed over the source, gate electrode, and drain. After that, the semiconductor layer containing silicon is buried with a laminated film of a semiconductor layer containing silicon and a metal layer, the semiconductor layer containing silicon is polished by using the semiconductor layer containing silicon as a polishing stopper, and the exposed semiconductor layer containing silicon is removed by etching. Since the source and drain are electrically isolated, it is not necessary to keep a predetermined distance between each contact hole, which is essential when forming contact holes for each of the source and drain. S FET can be miniaturized. [Brief description of drawings]

FIG. 1 is a cross-sectional view of a typical element for explaining the problem of the conventional structure. FIG. 2 is a cross-sectional view of a typical element for explaining the problem of the conventional structure. FIG. 3 is an element cross-sectional structure diagram for explaining the first embodiment of the present invention. FIG. 4 is a plan layout diagram for explaining a photomask pattern used in the element manufacturing process. FIG. 5 is a cross-sectional structure diagram for explaining a device manufacturing process. FIG. 6 is a sectional structural view for explaining the element manufacturing process. FIG. 7 is a cross-sectional structure diagram illustrating a device manufacturing process. FIG. 8 is a cross-sectional structural view for explaining a device manufacturing process. FIG. 9 is a cross-sectional structure diagram illustrating an element manufacturing process. FIG. 10 is a cross-sectional structure diagram for explaining a device manufacturing process. FIG. 11 is a cross-sectional structure diagram illustrating an element manufacturing process. FIG. 12 is a sectional structural view for explaining the element manufacturing process. FIG. 13 is a cross-sectional structure diagram illustrating a device manufacturing process. FIG. 14 is a cross-sectional structure diagram illustrating an element manufacturing process. FIG. 15 is a sectional structural view for explaining the element manufacturing process. FIG. 16 is a cross-sectional structure diagram illustrating a device manufacturing process. FIG. 17 is a sectional structural view for explaining the element manufacturing process. FIG. 18 is a sectional view of an element for explaining another element isolation method. FIG. 19 is an element cross-sectional structure diagram for explaining still another element isolation method. FIG. 20 is an element cross-sectional structure diagram for explaining a second embodiment of the present invention. FIG. 21 is an element cross-sectional structure diagram for explaining a third embodiment of the present invention. FIG. 22 is a cross-sectional structural view of an element for explaining a fourth embodiment of the present invention. FIG. 23 is an element cross-sectional structure diagram for explaining a fifth embodiment of the present invention. FIG. 24 is a sectional structural view for explaining another element manufacturing process. FIG. 25 is a sectional structural view for explaining another element manufacturing process. FIG. 26 is a sectional structural view for explaining another element manufacturing process. FIG. 27 is a sectional structural view for explaining another element manufacturing process. Figure FIG. 28 is a sectional structural view for explaining another element manufacturing process. FIG. 29 is a sectional structural view for explaining another element manufacturing process. FIG. 30 is a cross-sectional structure diagram illustrating another element manufacturing process. FIG. 31 is a sectional structural view for explaining another element manufacturing process. FIG. 32 is a sectional structural view for explaining another element manufacturing process. FIG. 33 is a sectional structural view for explaining another element manufacturing process. FIG. 34 is a sectional structural view for explaining another element manufacturing process. FIG. 35 is a sectional structural view for explaining another element manufacturing process. FIG. 36 is a sectional structural view for explaining another element manufacturing process. FIG. 37 is a cross-sectional view illustrating another element manufacturing process. FIG. 38 is a sectional structural view for explaining another element manufacturing process. FIG. 39 is a sectional structural view for explaining another element manufacturing process. FIG. 40 is a sectional structural view for explaining another element manufacturing process. FIG. 41 is a plan layout diagram for explaining a seventh embodiment of the present invention. FIG. 42 is a sectional view of an element for explaining a seventh embodiment of the present invention. FIG. 43 is a plan layout diagram for explaining an eighth embodiment of the present invention. FIG. 44 is a sectional structural view for explaining an element manufacturing process according to the eighth embodiment of the present invention. FIG. 45 is a sectional structural view for explaining an element manufacturing process for explaining an eighth embodiment of the present invention. FIG. 46 is an equivalent circuit diagram for explaining the ninth embodiment of the present invention. FIG. 47 is a plan layout diagram for explaining an eighth embodiment of the present invention. FIG. 48 is a sectional structural view for explaining the element manufacturing process of the tenth embodiment of the present invention. FIG. 49 is a sectional structural view for explaining the element manufacturing process of the tenth embodiment of the present invention. FIG. 50 is a sectional structural view for explaining the device manufacturing process of the tenth embodiment of the present invention. FIG. 51 is a sectional structural view for explaining the element manufacturing process of the tenth embodiment of the present invention. FIG. 52 is a sectional structural view for explaining the element manufacturing process of the tenth embodiment of the present invention. FIG. 53 shows a tenth embodiment of the present invention. It is sectional structure drawing explaining an element manufacturing process.

[Best mode for carrying out the invention]

Hereinafter, the present invention will be described in more detail with reference to various embodiments.

Embodiment 1>

FIG. 3 is a schematic diagram showing a cross-sectional structure of the semiconductor device according to the first embodiment of the present invention.

Reference numeral 200 denotes a support substrate made of, for example, high-resistance single-crystal silicon. Reference numeral 210 denotes an insulating layer formed on the supporting substrate 200.For example, _c 201 made of silicon dioxide is a semiconductor region of the first conductivity type patterned on the insulating layer 210. For example, it is made of single crystal silicon. The semiconductor region 201 of the first conductivity type is the SOI layer. A source / drain region (diffusion layer) 213 of a second conductivity type opposite to the first conductivity type is formed in the SOI layer. Reference numeral 211 denotes an element isolation insulating film, for example, silicon dioxide. Reference numeral 202 denotes a gate insulating film made of, for example, silicon dioxide. Reference numeral 203 denotes a gate electrode, which is made of, for example, a polycrystalline silicon film, a multi-layer film of polycrystalline silicon and a metal such as tungsten, or a metal film such as tungsten, titanium nitride, and tungsten nitride. Note that a silicon-germanium mixed crystal may be used instead of the polycrystalline silicon. Reference numeral 205 denotes a sidewall spacer made of an insulating film such as silicon nitride. Reference numerals 206 and 207 denote first extraction electrodes, and a silicon-containing half made of polycrystalline silicon or a polycrystalline silicon-germanium mixed crystal in contact with the diffusion layer 213 on the side surface of the SOI layer 201. Guidance It has a laminated structure of a body layer 206 and a metal layer 207 made of tungsten or the like. Reference numeral 208 denotes a second extraction electrode, and reference numeral 209 denotes a distribution layer, which is made of, for example, tungsten, copper, or aluminum. Reference numerals 2 12 and 2 14 are interlayer insulating films, for example, made of silicon dioxide.

Considering the source / drain parasitic resistance in the semiconductor device of this embodiment, the silicon-containing semiconductor layer 206 formed of polycrystalline silicon or silicon-germanium mixed crystal has a thin SOI layer 201. It is in contact with the side of the diffusion layer 2 13 formed inside. The SOI layer 201 and polycrystalline silicon are of the same material and do not create an electrical barrier at the contact surface. Also, even in a silicon-germanium mixed crystal, when a high concentration of impurities is doped to make the material conductive, no barrier is formed for electrons. Therefore, the SOI layer 201 and the silicon-containing semiconductor layer 2 • 6 are electrically connected with little contact resistance. Further, the silicon-containing semiconductor layer 206 is formed so as to cover the lower side surface and the lower surface of the metal layer 207. Therefore, for example, the current path flowing from the SOI layer 201 spreads in the silicon-containing semiconductor layer 206 and can flow to the metal layer 207. In other words, a contact area between the metal layer 207 having a large contact resistance and the silicon-containing semiconductor layer 206 can effectively secure a wide contact area. For these reasons, in the semiconductor device of the present embodiment, it is possible to prevent an increase in the source-drain parasitic resistance even when the S〇I layer becomes thin.

FIG. 3 shows a structure in which the entire surface of the side surface of the SOI layer 201 is in contact with the silicon-containing semiconductor layer 206. The SOI layer 201 may be left between the semiconductor layer 206 and the insulating layer 210, and the silicon-containing semiconductor layer 206 may be in contact with a part of the side surface of the SOI layer 201. In this case, as the SOI layer 201 becomes thinner, the resistance of the diffusion layer between the silicon-containing semiconductor layer 206 and the insulating layer 210 becomes extremely large, and the effective contact area between the lead electrode and the SOI layer 201 becomes smaller. 20 One part of the side. Meanwhile, a part of the side surface of the SOI layer 201 is in contact with the silicon-containing semiconductor layer 206 having a lower contact resistance than the metal layer 207, and the metal layer 207 is part of the side surface of the SOI layer 201. The source / drain parasitic resistance due to thinning of the SOI layer is the same as when the entire surface of the side surface of the SOI layer 201 is in contact with the silicon-containing semiconductor layer 206 because the entire surface of the SOI layer 201 is in contact with the silicon-containing semiconductor layer 206. The increase can be kept small. However, when the silicon-containing semiconductor layer 206 and the entire side surface of the SOI layer 201 are in contact with each other, the parasitic resistance of the source and drain can be made smaller than when the silicon-containing semiconductor layer 206 is in contact with a part of the side surface of the SOI layer 201.

FIG. 4 shows a photomask pattern for processing and forming the semiconductor device according to the first embodiment of the present invention.

The rectangular pattern 1 • 1 shown by the bold line is used for patterning the SOI layer and defining the active region. A gate electrode pattern 102 is laid out so as to straddle the pattern 101. The pattern 103 is a pattern of a contact hole for forming a first extraction electrode. The pattern 104 is a pattern for opening a contact hole on the gate electrode. The pattern 105 is used to open a contact hole for forming a second extraction electrode on the first extraction electrode. It is a pattern of. The pattern 106 is a pattern for processing the wiring layer _c . The cross-sectional structure of the semiconductor device shown in FIG. 3 corresponds to the cross section AA in FIG.

Next, a method of manufacturing the semiconductor device according to the first embodiment will be described with reference to FIGS.

First, the surface of the SOI substrate on which the SOI layer 201 is formed via the insulating layer (buried oxide film) 210 on the support substrate 200 is thermally oxidized by about 10 nm to form the protective oxide film 222. Next, after a silicon nitride film 221 is deposited on the protective oxide film 222 by a CVD method, the silicon nitride film 221 is processed by the photomask pattern 101 shown in FIG. 2, and the silicon nitride film 221 is further protected by using the silicon nitride layer 221 as a mask. The oxide film 222 and the SOI layer 201 are processed (FIG. 5).

A silicon oxide film 223 is deposited thereon by a CVD method (FIG. 6). Thereafter, the silicon nitride film 221 and the protective oxide film 222 are polished and flattened by CMP (Chemical Mechanical Polishing) using the silicon nitride film 221 as a stopper, and then removed by wet etching (FIG. 7). As a result, an inter-element isolation insulating film 211 is formed.

Next, the surface of the SOI layer 201 is thermally oxidized by about 2 nm to form a gut insulating film 202, and then a silicon-germanium mixed crystal 203 doped with a high concentration of polon is deposited to a thickness of about 100 nm. About 150 nm, and about 100 nm of silicon nitride 224 (Fig. 8).

The silicon nitride film 224 is patterned by the photomask pattern 102 shown in FIG. Then, using the silicon nitride film 224 as a mask, the silicon oxide film 204 and the silicon / germanium mixed crystal 203 are patterned to form a gate electrode 203 (FIG. 9).

Note that the gate insulating film 202 may be an oxynitride film obtained by nitriding a thermal oxide film or a laminated film of an oxidized film and a nitride film. Further, the gate electrode 203 may be a polycrystalline silicon, a laminated film of silicon-germanium mixed crystal and a metal, or a metal alone.

Next, using the silicon nitride film 224 as a mask, an impurity is implanted into the SOI layer 201 by ion implantation to form a diffusion layer 213, and then the silicon nitride film 225 is formed by CVD to a thickness of about 50%. Deposit nm (Fig. 10). Further, after an interlayer insulating film 214 is deposited by about 5 O Onm, its surface is flattened by the CMP method (FIG. 11).

The interlayer insulating film 214 is formed of a silicon oxide film, an organic insulating film, or the like. The polishing amount by the CMP method is arbitrary as long as it is necessary for flattening the surface. However, the greater the amount, the easier the subsequent contact processing step becomes.

Using the photoresist 220 having the pattern 103 shown in FIG. 2 as an opening as a mask, the interlayer insulating film 214 is removed by dry etching. This dry etching method is desirably performed under the condition that the selectivity between the interlayer insulating film 214 and the silicon nitride film 225 is high (FIG. 12).

After that, the silicon nitride film 225 is etched away by the anisotropic dry etching method to the thickness. At this time, a sidewall spacer 205 made of silicon nitride is left on the side surface of the gate electrode 203. Furthermore, this Saidoo Using the silicon spacer 205 and the silicon nitride film 204 as a mask, the SOI layer 201 is etched and removed until the insulating layer 210 is exposed, exposing the entire side surface of the SOI layer 201 (see FIG. 13 ) .

At this time, the etching may be stopped in a state where the SOI layer 201 is slightly left on the insulating layer 210. In this case, contact is made by utilizing a part of the side surface of the SOI layer 201.

Next, a polycrystalline silicon film 206 is deposited to a thickness of about 50 nm by the CVD method, and is then conducted by ion-implanting an impurity corresponding to the conductivity type of the source and drain of the transistor. · A titanium nitride multilayer film 207 is deposited to a thickness of about 300 nm by CVD and sputter deposition (Fig. 14). As 206, a silicon-germanium mixed crystal film may be used instead of the polycrystalline silicon film. Alternatively, ion implantation after the deposition may be omitted by depositing the polycrystalline silicon film 206 while doping with impurities. This method is more preferable because it simplifies the process and makes the impurity concentration in the polycrystalline silicon film 206 uniform.

Next, the tungsten / titanium nitride laminated film 207 is polished by the CMP method. At this time, the polycrystalline silicon film 206 is used as a polishing stopper, and the CMP method is used until the polycrystalline silicon film 206 on both the interlayer insulating film 214 and the gate electrode 203 is exposed. Polishing is performed (Fig. 15). The exposed polycrystalline silicon film 206 on interlayer insulating film 214 and above gate electrode 203 is removed by dry etching. By this dry etching process, the source and drain are electrically separated. (Figure 16). In order to complete the strong electrical isolation, in this dry etching step, over-etching of the polycrystalline silicon film 206 or more is performed, and the polycrystalline silicon film 206 after etching is removed. It is preferable that the upper surface be lower than each upper surface of the insulating film (silicon nitride film 224) above the interlayer insulating film 214 and the gate electrode 203.

In the manufacturing method of the present embodiment described above, the source and drain contact holes are not formed by using a photomask pattern having openings corresponding to the source and the drain, but are formed to the same degree as the SOI layer. Using a photomask pattern with openings of the above sizes, the source and drain contact holes are collectively opened, and the conductor buried in the source contact hole and the conductor buried in the drain contact hole It is characterized in that the separated conductive material is electrically separated later. Therefore, in the conventional method, it is difficult to miniaturize the SOIMISFET because a predetermined interval is required between each contact hole of the source and the drain, whereas in the method of the present embodiment, it is difficult to miniaturize the SOIMISFET. Can be easily achieved.

Further, an interlayer insulating film 212 is deposited and planarized again by the CMP method, and then a contact hole is opened by the photomask pattern 105 shown in FIG. 2 (FIG. 17). Thereafter, metal layers 208 and 209 are deposited, and the wiring layer is processed according to the photomask pattern 106 shown in FIG. 2, whereby the semiconductor device of the first embodiment shown in FIG. 1 is formed. .

Note that the element isolation method is not limited to the method described with reference to FIGS. 5 to 7. In addition to this, after the step of FIG. 5, as shown in FIG. Alternatively, a deep groove may be formed by ching, and then the steps shown in FIGS. 6 and 7 may be performed. In addition, if the SOI layer is thin enough not to affect the subsequent processing of the gate electrode, the silicon nitride film 222 shown in FIG. Alternatively, the protective oxide film 222 may be removed, and then the process of FIG. 8 may be performed.

FIG. 20 is a schematic diagram showing a cross-sectional structure of a semiconductor device according to the second and second embodiments of the present invention. ,

In the first embodiment, since the silicon-containing semiconductor layer 206 covers the entire side surface of the sidewall spacer 205, the gate electrode 203 and the first extraction electrode 205 are formed. 6, 2 0 issues force ^s that a large parasitic capacitance is generated between the 7. '

This embodiment is to improve the problem while securing the contact area with the side surface of the SOI layer 201, and the upper surface of the silicon-containing semiconductor layer 206 is made higher than the upper surface of the SOI layer 201. And a range lower than the center of the gut electrode 203 in the height direction. Also, in this embodiment, in order to compensate for the limited space of the upward current path in the silicon-containing semiconductor layer 206, the first extraction electrodes 206 and 207 are formed. A contact hole is formed inside the insulating layer 210, and a part of the silicon-containing semiconductor layer 206 and the metal layer 20'7 is buried also in the insulating layer 201, and the silicon-containing semiconductor layer 206 is formed. The space to spread the current path downward in the middle is secured. , <Embodiment 3>

FIG. 21 is a schematic diagram showing a cross-sectional structure of a semiconductor device according to a third embodiment of the present invention.

This embodiment has a structure in which not only the side surface of the SOI layer 201 but also a part of the bottom surface is used as a contact surface between the diffusion layer 21 3 and the silicon-containing semiconductor layer 206. Such a structure can be realized by adding a step of isotropically etching the insulating layer 210 after the step shown in FIG. In the present embodiment, the contact area between the diffusion layer 211 and the silicon-containing semiconductor layer 206 is made as large as possible, so that the contact resistance can be further reduced. + <Embodiment 4>

In each of the above embodiments, the semiconductor device in which the first extraction electrode is formed in a self-aligned manner with respect to the gate electrode in order to achieve higher integration has been described. Each contact hole for the source and the drain may be formed using a photomask pattern having a pattern, and an extraction electrode may be provided therein. FIG. 22 shows a cross-sectional structure of a semiconductor device according to a fourth embodiment of the present invention prepared by this method. ''

In this embodiment, since the distance from the end of the gate electrode 203 to the extraction electrodes 206 and 207 can be formed arbitrarily, the parasitic capacitance between the two can be reduced. Further, in this embodiment, since a distance from an arbitrary gate end can be ensured, a device with a high withstand voltage can be formed by further increasing the distance between the two only on the drain side. Also in this embodiment, the contact holes for the source and the drain are formed so that the side surfaces of the diffusion layer 211 in the SOI layer are exposed, and the semiconductor layer containing silicon is formed on the side surface of the diffusion layer 211. A metal layer 207 having a contact area with the silicon-containing semiconductor layer 206 larger than the contact area between the diffusion layer 213 and the silicon-containing semiconductor layer 206 is formed. It is similar to each of the above embodiments in that it is formed, and the parasitic resistance can be reduced even when the SOI layer is thin.

In each of the embodiments described above, the case where the present invention is used for the contact formation technology for the diffusion layer in the SOI layer of the SOIMISFET has been described. However, the present invention relates to a semiconductor device using the SOI layer (eg, a resistor, a bipolar transistor, etc.). Then, it is applicable not only to SOIMISFET.

FIG. 23 is a schematic diagram showing a cross-sectional structure of a semiconductor device according to a fifth embodiment of the present invention applied to a diode formed in an SOI layer as an example.

1900 is an insulating layer, 1210 is an n-type diffusion layer, 1220 is a p-type diffusion layer, and in this embodiment, a PN junction diode is formed in the SOI layer. . The extraction electrode electrically connected to the n-type diffusion layer 1 210 and the p-type diffusion layer 122 0 contains polycrystalline silicon or silicon-genolemanium mixed crystal formed on the side and bottom surfaces. It comprises a semiconductor layer 1206 and a metal layer 1207 formed on the inside thereof, and the silicon-containing semiconductor layer 1206 on the side surface of the extraction electrode is an n-type diffusion layer 1210 It is in contact with the side surface of the p-type diffusion layer 122. In the case where only a diode is formed on an SOI substrate, simply increasing the thickness of the SOI layer can reduce the parasitic resistance even if the above-mentioned [Background Art] is applied. However, when a diode and an SO IMISFET (especially a fully depleted SOIMISFET) are formed on the same SOI substrate, the thickness of the SOI layer may be changed between the diode and the SOIMISFET. Forming differently shaped extraction electrodes complicates the manufacturing process. The present embodiment is particularly effective in such a case.

FIG. 24 to FIG. 40 are cross-sectional structural views in each step of another manufacturing method according to the present invention. In this embodiment, a CMOS in which both an NMOS and a PMOS are formed in one SOI layer will be described.

First, a protective oxide film (not shown) is formed by thermally oxidizing the surface of the SOI substrate having the S〇I layer 1101 formed on the supporting substrate via the insulating layer 1910, and then nitriding on the protective oxide film. A silicon film 1950 is deposited by a CVD method. Next, after removing 1950 nm of silicon nitride (silicon nitride) in the element isolation region, a groove is formed in the insulating layer 1910 using the silicon nitride film 1950 as a mask. Then, a silicon oxide film 1960 is deposited so as to fill the formed groove (FIG. 24). In the SOI layer 1101, p-type and n-type impurities are respectively introduced in advance into each of the NMOS and PMOS formation regions.

After depositing the silicon nitride film 1955, patterning is performed to leave the silicon nitride film 1955 only in the trench (Fig. 25). As a result, in the following polishing by CMP method, Dishing can be prevented from occurring in the element isolation region (

Next, the silicon nitride films 1950 and 1955 are polished by polishing.

After polishing, the silicon nitride films 195 and 195 and the protective oxide film are removed (FIG. 26).

A gate insulating film is formed on the surface of the SOI layer 1101, and a laminated gate electrode is formed on the gate insulating film as shown in FIG. Here, when a silicon-germanium mixed crystal doped with boron at a high concentration is used as the gate electrode material immediately above the gate insulating film, the work function can be changed by the combination of germanium and silicon. In particular, when the gate insulating film has an oxynitride film or a stacked structure of an oxide film and a nitride film, it is known that the charge in the film shifts the threshold value of the transistor to the negative side as compared with the oxide film. Therefore, by combining these gate insulating films with the gate electrode made of silicon-germanium mixed crystal, in the thin-film gut insulating film region, it is substantially equivalent to p-type polycrystalline silicon from almost the center of the silicon band gap. Work function can be covered up to valence band. Therefore, it is suitable for controlling the threshold value of the transistor. In the present embodiment, a silicon / germanium mixed crystal 150, tungsten nitride (not shown), tungsten 15010, and a silicon oxide film 1925 were laminated in this order from the bottom to form a laminated gate electrode. Using the stacked gate electrode as a mask, a source / drain diffusion layer 123 was formed by ion implantation (FIG. 27). Next, after depositing a 50 nm silicon oxide film 1935, anisotropic etching is performed to form a silicon spacer 1935 made of a silicon oxide film on the side surface of the stacked gate electrode. . (Figure 28). A silicon-germanium mixed crystal 1370 is deposited to a thickness of 300 nm and its surface is planarized by CMP (Fig. 29). At this time, the silicon-germanium mixed crystal 1370 is removed until the surface of the silicon oxide film 1925 is exposed. Further, a silicon oxide film of about 5 nm may be interposed under the silicon-germanium mixed crystal 1370.

Next, the silicon-germanium mixed crystal 1370 is etched using a resist film (not shown) covering a portion facing the SOI layer 111 (FIG. 30). At this time, in the element isolation region, the steps formed by the gate electrodes 1510 and 1500 prevent the removal of the silicon-germanium mixed crystal 1370, but the gate electrodes 1510 and 1500 Since it is protected by the thick oxide films 1925, 1935, the silicon-germanium mixed crystal 1370 in the element isolation region can be completely removed by performing sufficient overetching. After depositing an interlayer insulating film 1945 made of silicon oxide film, it is flattened by the CMP method so that the upper surface of the silicon-germanium mixed crystal 1370 is exposed (FIG. 31).

Next, the silicon-germanium mixed crystal 1370 is etched using hydrogen peroxide solution and ammonia to expose the SOI layer 1230 (Fig. 32), and then the interlayer insulating film 1945 is laminated. Etching is performed using the gate electrodes 1925, 1510, 1500 and the sidewall / resistor 1935 as masks (Fig. 33). At this time, on the SOI substrate, there is no material other than silicon-germanium mixed crystal that can be etched by hydrogen peroxide and ammonia, so that silicon-germanium mixed crystal 1370 can be completely removed. Silicon / germanium mixed crystal When a silicon oxide film is laid, the silicon oxide film is etched and then the SOI layer 1230 is etched. When a silicon oxide film is laid, polycrystalline silicon can be used instead of silicon-germanium mixed crystal 1370. _{c In} the etching of this polycrystalline silicon, a choice of a silicon oxide film is made. For example, dry etching with SF 6, wet etching with hydrazine, or the like may be used.

Next, the surface of the diffusion layer 1230 of the SΟI layer 1101, which is exposed on the side surface, is cleaned. At this time, as in the third embodiment, the surface area of the exposed S SI layer 1101 can be increased by lightly etching the insulating layer 1910.

In the dry etching process for forming the sidewall spacer on the side surface of the gate electrode, contamination damage occurs on the surface of the underlying SOI layer exposed by the dry etching. Forming a contact using such a contaminated and damaged SOI layer surface will result in a large resistance. However, in the manufacturing process according to the present embodiment, such a contaminated 'damage layer is also removed by the etching process of the SOI layer 1101, and the contact is made by using the newly exposed side surface and the like of the SOI layer 1101. Therefore, the above-described increase in resistance can be prevented. This effect can be obtained in the same manner in the method of manufacturing a semiconductor device described with reference to FIGS.

After depositing a silicon-germanium mixed crystal 1206 to be a part of the extraction electrode, the NMOS formation region is doped with phosphorus, and the PMOS formation region is doped with boron. 35).

Next, an extraction electrode is formed together with the silicon-germanium mixed crystal 1 206 Deposit 605. When the CMOS of this embodiment is applied to a memory, heat treatment may be required in the subsequent steps. In this case, tungsten should be deposited after depositing a metal with high heat resistance such as TiN (Fig. 35). Next, the CMP method is applied until the silicon-germanium mixed crystal 1206 on the interlayer insulating film 1945 and the stacked gate electrodes 1925, 1550, 1550 is exposed. The stainless steel 1605 is polished (FIG. 37). At this time, the silicon-germanium mixed crystal acts as a polishing stopper because it can secure selectivity to polishing by the CMP method between metals such as tungsten and TiN, and serves as a polishing stopper. The gate electrodes 1925, 1510, and 1500 can be protected.

Etch-back removes silicon-germanium mixed crystal 1206 on interlayer insulating film 1945 and laminated gate electrode 1925, 1510, 1500, and removes extraction electrode to gate electrode To separate them into the source side and the drain side (Fig. 38).

In the manufacturing method of the present embodiment, unlike the above-described embodiment of the manufacturing method, the gate electrodes 1510 and 1500 are formed of silicon oxide films 1925 and 1993 having a lower dielectric constant than the silicon nitride film. Since it is covered with 5, each parasitic capacitance between the gate electrode and the extraction electrode and between the source / drain diffusion layer and the extraction electrode can be reduced.

Next, a silicon nitride film 196 6 is deposited (FIG. 39), an oxidized silicon film 196 7 is deposited, and a silicon oxide film 196 up to the silicon nitride film 196 6 is formed by a wiring pattern. 7 is etched to form a groove, and the contact hole is opened by etching the silicon nitride film 966 between the groove and the lead electrode using the contact pattern. Say it. Then, after depositing a metal film 1615 made of tungsten or copper, the metal film other than the contact holes and grooves is polished and removed by the CMP method (FIG. 40). These steps are wiring forming steps known as a damascene method.

In the manufacturing method of the present embodiment described above, since the contact holes of the source and the drain are not formed using the pattern of the photomask having openings corresponding to the source and the drain, the source and the drain are not formed. A predetermined interval is not required between the contact holes, and the miniaturization of the SOIMISFET can be easily achieved similarly to the manufacturing method of the above-described embodiment. .

When a diffusion layer is formed in the SOI layer by ion implantation after processing the gate electrode, the pattern 1256 shown in Fig. 41 can be used to secure an SOI region that is not ion-implanted. . FIG. 42 shows an A-A cross-sectional structure of this region after device formation. There is no impurity diffusion layer formed by ion implantation, and the SOI layer 111 and the silicon-containing semiconductor layer 122 made of silicon-germanium mixed crystal are in direct contact. At this contact surface, impurities are also ion-implanted at a high concentration into the silicon-germanium mixed crystal 1206, so that the impurities are diffused into the SOI layer 1101 side and a junction is formed in the SOI layer 1101. It is formed. At the same time, a so-called heterojunction is formed due to the difference in band gap between silicon-germanium mixed crystal 126 and silicon. In this structure, the pn junction and the heterojunction can be formed in almost the same area, that is, near the contact surface. If the silicon.germanium mixed crystal 1 206 side is n-type and the SOI layer 1101 is p-type, the SOI layer 1 In this case, the potential barrier against hole injection can be made lower than that of a pn junction formed by silicon, and holes can easily flow to the silicon-germanium mixed crystal 1206 side. As a result, holes, which are a problem in SOIMISFETs, accumulate in the channel (SOI) portion, and the effect of floating the substrate, which makes transistor operation unstable, can be suppressed.

Since the present invention relates to a transistor element which is a basic element of a semiconductor device, it can be widely used for application devices. An eighth embodiment in which the element according to the present invention is applied to a semiconductor memory device will be described.

Fig. 44 is a plan layout diagram when applied to a dynamic random access memory (DRAM), and Figs. 45 and 46 are cross-sectional structures along the line AA in Fig. 44. Here, the folded bit line arrangement is used. To show the relative arrangement of the cells, the active area 122 and the word lines 157 1 are shown in an array, but the extraction electrodes 126, the data lines 168 1, and the capacitors 170 1 is for only the center two cells. Bold lines in the plan view indicate the lead electrodes 126 formed of a silicon-containing semiconductor layer such as polycrystalline silicon or silicon-germanium mixed crystal. FIG. 45 shows the cross-sectional structure at the stage where the extraction electrodes up to 126 are formed. In a DRAM memory cell, there is a case where it is required that the integration, that is, the formation can be made smaller than the parasitic resistance. In that case, as shown in FIG. 45, the extraction electrode 126 can be made only by the silicon-containing semiconductor layer. Even in this case, the SOI layer 1 The surface has the effect of reducing the parasitic resistance. Fig. 46 shows the cross-sectional structure at the stage when the extraction electrode 1206 was formed and the capacitor section 1701 was formed. The interlayer insulating film 1983 was deposited to form the data line. After that, an interlayer insulating film 198 4 is deposited again and subjected to a flattening process.After that, a capacitor electrode 1 701 made of a metal layer is formed, and a capacitive insulating film 198 2 made of tantalum is formed. This shows a state in which the upper electrode 1675 is formed after the formation. However, as can be seen from the plan view of FIG. 44, no data line appears in FIG.

A ninth embodiment in which the present invention is applied to SRAM using CMOS, which is another typical memory element, will be described. FIG. 46 shows a memory cell shown by an equivalent circuit. FIG. 47 shows a planar layout of the memory cell. The hatched portion shows a photomask pattern for opening contact holes for extraction electrodes. In the present invention, since the extraction electrode is separated on the gate in a self-aligned manner, the pattern 126 may be arranged so as to straddle the gate. The cell boundaries are indicated by 1 130. In the case of the SRAM combined with the CMOS inverter, it is necessary to connect the diffusion layers of the NMOS and the PMOS, which are the information storage units.However, the extraction electrode is formed so as to extend between the NMOS and the PMOS. This allows connection. As described above, in this embodiment, the extraction electrode is used as a wiring connecting each source / drain diffusion layer of a plurality of SOIMISFETs. In a normal silicon substrate, there is a problem that a parasitic capacitance is generated or a short circuit occurs between electrodes. However, in this embodiment using an SOI substrate, a thick insulating layer is provided under the SOI layer. Also under the extraction electrode Therefore, the possibility of causing such a problem can be reduced.

Note that, as in the first to seventh embodiments, the extraction electrode in this embodiment is composed of a silicon-containing semiconductor layer in contact with the side surface of the SOI layer and a metal layer in contact with the semiconductor layer. It is configured.

FIGS. 48 to 53 show a tenth embodiment showing a method for forming a substrate contact according to the present invention. There is a possibility that a higher voltage may be applied to the input section than the outside, and it is effective to form a bipolar element or the like that extracts such a current on the substrate as a protection element against this. In the present invention, such a protective element can be formed by using a supporting substrate. Hereinafter, a method for forming a contact with a support substrate will be described based on the element manufacturing method described with reference to FIGS.

After gate processing as in FIG. 28, sidewall spacers 1935 are formed on the side surfaces. An opening is formed in the element isolation film 1960 and the insulating layer 1910 using the substrate contact pattern, exposing the support substrate 1105 (FIG. 48).

A silicon-germanium mixed crystal 1370 is deposited and planarized by the CMP method, exposing the insulating film 1925 above the gate (FIG. 49). By setting the width of the opening in the support substrate to be equal to or less than half that of the mixed crystal to be deposited, the opening can be effectively filled, so that the following steps can be performed without changing the process.

(Figure 50) Using a photomask pattern with an opening from the substrate contact to the SOIMISFET, process the silicon-germanium mixed crystal 1370 by dry etching up to the element isolation film 1960 I do. After the oxidation film 1945 is deposited, the film is flattened by the CMP method to expose the silicon-germanium mixed crystal 1370 (FIG. 51).

The silicon-germanium mixed crystal 1370 is removed by etching to expose the SOI layer 1101 and the supporting substrate 1105 (FIG. 52).

A silicon-containing semiconductor layer 1206 and a metal layer 1605 are deposited and processed by CMP and etching (Fig. 53). At this time, a bond can be formed between the silicon-containing semiconductor layer and the support substrate. After the opening in the support substrate, the diffusion layer can be formed by ion implantation.

As described above, according to the present invention, the parasitic resistance of the source and the drain can be reduced in the MI SFET using the thin film SO I, particularly in the fully depleted SO I MIS FET. As a result, a high-performance MISFET with a large current driving capability can be provided.

Further, according to the present invention, a MIS FET using SOI can be miniaturized.

[Industrial applicability]

INDUSTRIAL APPLICABILITY As described above, the present invention is suitable for application to a semiconductor device using an SOI substrate and a method for manufacturing the same in general. '

Claims

The scope of the claims

1. In a semiconductor device having a semiconductor element using an SOI layer and an electrode for electrically connecting a diffusion layer formed in the SOI layer,

The electrode includes a silicon-containing semiconductor layer in contact with the diffusion layer on a side surface of the SOI layer, and a metal layer in contact with the silicon-containing semiconductor layer.

2. In the semiconductor device according to claim 1,

A semiconductor device, wherein a contact area between the metal layer and the silicon-containing semiconductor layer is larger than a contact area between the silicon-containing semiconductor layer and the SOI layer.

3. In the semiconductor device according to claim 2,

A semiconductor device, wherein the silicon-containing semiconductor layer is in contact with the diffusion layer even at a part of the bottom surface of the SOI layer.

4. The semiconductor device according to claim 2,

A semiconductor device, characterized in that the semiconductor element is a fully depleted SOI MISFET.

5. The semiconductor device according to any one of claims 1 to 4,

The semiconductor device according to claim 1, wherein the silicon-containing semiconductor layer is doped with an impurity of the same conductivity type as the impurity introduced into the diffusion layer at a high concentration.

6. The semiconductor device according to any one of claims 1 to 4,

Wherein the silicon-containing semiconductor layer is made of polycrystalline silicon.

7. The semiconductor device according to claim 1, wherein the silicon-containing semiconductor layer is made of a mixed crystal of silicon and germanium.

8. Semiconductor having a semiconductor element using a first semiconductor layer formed on an island on an insulating layer and an electrode for making electrical connection with a diffusion layer formed in the first semiconductor layer In the device,

Wherein the electrode has a second semiconductor layer in contact with the diffusion layer at a part of a side surface of the first semiconductor layer; and a metal layer in contact with the second semiconductor layer. apparatus.

9. The semiconductor device according to claim 8, wherein

A semiconductor device, wherein a contact area between the metal layer and the second semiconductor layer is larger than a contact area between the second semiconductor layer and the first semiconductor layer. '10. The semiconductor device according to claim 9,

11. The semiconductor device according to claims 8 to 10, wherein

The semiconductor device according to claim 1, wherein the second semiconductor layer has a high concentration of impurities of the same conductivity type as impurities introduced into the diffusion layer.

12. The semiconductor device according to any one of claims 8 to 10, wherein

A semiconductor device, wherein the second semiconductor layer is made of polycrystalline silicon.

3. The semiconductor device according to any one of claims 8 to 10,

The second semiconductor layer is made of a silicon-germanium mixed crystal.

14. An SOI having a source'drain formed in an SOI layer, a gate insulating film formed on the SOI layer, and a gut electrode formed on the gate insulating film MI S FET and

A metal layer electrically connected to the source and drain,

A material film having a contact resistance with the SOI layer smaller than a contact resistance between the SOI layer and the metal layer;

The material film is in contact with a side surface of the SOI layer and the metal layer, and establishes electrical continuity between the source / drain and the metal layer.

15. In the semiconductor device according to claim 14,

A semiconductor device, wherein the metal layer and the material film are in contact with each other in a larger area than the material film and the SOI layer.

16. In the semiconductor device according to claim 15,

A semiconductor device, wherein the material film is in contact with the source / drain even at a part of the bottom surface of the SOI layer.

17. In the semiconductor device according to claim 15,

A semiconductor device, wherein the SO IMISFET is a fully depleted SOIMISFET.

18. The semiconductor device according to claim 14, wherein the material film is made of a semiconductor containing silicon, and has the same conductivity type as an impurity introduced into the source and drain. A semiconductor device characterized in that impurities are introduced at a high concentration.

19. The semiconductor device according to any one of claims 14 to 17, wherein

A semiconductor device, wherein the material film is made of polycrystalline silicon.

20. The semiconductor device according to any one of claims 14 to 17,

A semiconductor, wherein the material film is made of a silicon-germanium mixed crystal; 21. a semiconductor layer formed on an insulating layer; a source-drain formed in the semiconductor layer; A field-effect transistor comprising: a formed gate insulating film; and a gate electrode formed on the gate insulating film;

A metal layer electrically connected to the source and the drain;

A material film whose contact resistance with the semiconductor layer is smaller than the contact resistance of the semiconductor layer and the metal layer,

The material film is in contact with a part of the side surface of the semiconductor layer and the metal layer, and establishes electrical continuity between the source / drain and the metal layer.

22. In the semiconductor device according to claim 21,

A semiconductor device, wherein the metal layer and the material film are in contact with each other over a larger area than the material film and the semiconductor layer.

23. The semiconductor device according to claim 22,

The semiconductor device, wherein the material film is in contact with the source and the drain even at a part of the bottom surface of the semiconductor layer.

24. The semiconductor device according to claim 22,

A semiconductor device, wherein the field-effect transistor is a fully depleted SO IMIS FET.

25. The semiconductor device according to any one of claims 21 to 24,

The semiconductor device, wherein the material film is made of a semiconductor containing silicon, and an impurity of the same conductivity type as an impurity introduced into the source / drain is introduced at a high concentration.

26. The semiconductor device according to any one of claims 21 to 24,

27. The semiconductor device according to any one of claims 21 to 24,

A semiconductor device, wherein the material film is made of a silicon-germanium mixed crystal.

28. an insulating layer formed on the support substrate;

An SOI layer formed in an island shape on the insulating layer; a gate insulating film formed on the SOI layer; a gate electrode formed on the gut insulating film; and the gut in the SOI layer A MIS FET comprising diffusion layers formed on both sides of the electrode, and an insulating film formed to cover the MIS FET,

A contact hole formed in the insulating film so that a side surface of the SOI layer is exposed. When,

A semiconductor layer containing silicon formed on a side surface and a bottom surface in the contact hole;

A metal layer formed on the semiconductor layer so as to fill the contact hole.

29. The semiconductor device according to claim 28, wherein the contact hole is formed so as to extend to the insulating layer and partially expose a bottom surface of the SOI layer. A semiconductor device characterized by being in contact with the diffusion layer on a part of the side and bottom surfaces of the SOI layer.

30. The semiconductor device according to claim 28, wherein

A semiconductor device, wherein an upper surface of the semiconductor layer is higher than an upper surface of the SOI layer and lower than a center in a height direction of the gate electrode.

31. In the semiconductor device according to claim 30,

The semiconductor device, wherein the contact hole is formed up to the insulating layer, and the semiconductor layer extends into the insulating layer.

32. In the semiconductor device according to claim 28,

A semiconductor device characterized in that the MISFET is a fully depleted SOIMSFET.

33. In the semiconductor device according to any one of claims 28 to 32,

The semiconductor device according to claim 1, wherein the semiconductor layer has an impurity of the same conductivity type as that of the impurity introduced into the diffusion layer introduced at a high concentration.

34. The semiconductor device according to claim 28, wherein said semiconductor layer is made of polycrystalline silicon. 35. In the semiconductor device according to claims 28 to 32,

A semiconductor device, wherein the semiconductor layer is made of a silicon-germanium mixed crystal. '

36. An insulating layer formed on the support substrate,

A first semiconductor layer formed in an island shape on the insulating layer; a gate insulating film formed on the first semiconductor layer; a gate electrode formed on the gate insulating film; A MISFET comprising source and drain formed on both sides of the gate electrode in the first semiconductor layer;

An insulating film formed so as to cover the MISFET,

A contact hole formed in the insulating film so that at least a part of a side surface of the first semiconductor layer is exposed;

A second semiconductor layer containing silicon formed on a side surface and a bottom surface in the contact hole;

A metal layer formed on the second semiconductor layer so as to fill the contact hole.

37. In the semiconductor device according to claim 36,

The contact hole is formed so as to extend to the upper surface of the insulating layer so that the entire side surface of the first semiconductor layer is exposed, and the second semiconductor layer is formed so as to cover the source side surface over the entire side surface of the first semiconductor layer. A semiconductor device characterized by being in contact with a drain.

38. In the semiconductor device according to claim 37,

The contact hole is further formed to extend into the insulating layer so as to also expose a part of the bottom surface of the first semiconductor layer, and the second semiconductor layer is formed so that all of the side surfaces and the bottom surface of the first semiconductor layer are formed. A semiconductor device characterized in that a part thereof is in contact with the source / drain.

39. In the semiconductor device according to claim 36,

A semiconductor device, wherein an upper surface of the second semiconductor layer is higher than an upper surface of the first semiconductor layer and lower than a center in a height direction of the gate electrode.

40. The semiconductor device according to claim 39, wherein

The semiconductor device, wherein the contact hole is formed in the insulating layer, and the second semiconductor layer also extends in the insulating layer.

41. In the semiconductor device according to claim 36,

42. In the semiconductor device according to any one of claims 36 to 41,

The semiconductor device, wherein the second semiconductor layer is doped with impurities of the same conductivity type as the impurities introduced into the source / drain at a high concentration.

43. In the semiconductor device according to any one of claims 36 to 41,

A semiconductor device, wherein the second semiconductor layer is made of polycrystalline silicon. 44. The semiconductor device according to any one of claims 36 to 41,

The second semiconductor layer is made of a mixed crystal of silicon and germanium.

45. A first step of forming a semiconductor device using the SOI layer,

A second step of depositing an interlayer insulating film covering the semiconductor element;

A third step of forming a contact hole exposing a side surface of the SOI layer in the interlayer insulating film;

A fourth step of depositing a silicon-containing semiconductor layer on the interlayer insulating film and on the inner surface of the contact hole;

A fifth step of depositing a metal layer on the silicon-containing semiconductor layer; and a sixth step of removing the silicon-containing semiconductor layer and the metal layer on the interlayer insulating film. A method for manufacturing a semiconductor device.

46. The method of manufacturing a semiconductor device according to claim 45, wherein

A method for manufacturing a semiconductor device, characterized in that the fourth step is performed by depositing while introducing impurities into the silicon-containing semiconductor layer.

47. The method of manufacturing a semiconductor device according to claim 45, wherein

The sixth step is

Polishing the silicon-containing semiconductor layer; A seventh step of polishing the metal layer until the silicon-containing semiconductor layer on the interlayer insulating film is exposed by the CMP method used as

An eighth step of removing the silicon-containing semiconductor layer on the interlayer insulating film by etching.

48. In the method for manufacturing a semiconductor device according to claim 47, A method of manufacturing a semiconductor device, characterized in that in the eighth step, overetching is performed for a film thickness of the silicon-containing semiconductor layer or more.

49. The method for manufacturing a semiconductor device according to claim 45, wherein polycrystalline silicon is deposited in the fourth step.

50. The method for manufacturing a semiconductor device according to claim 45, wherein the silicon-germanium mixed crystal is deposited in the fourth step. .

5 1. a first step of forming a semiconductor element using the first semiconductor layer formed on the island on the insulating layer layer;

A third step of forming a contact hole exposing at least a part of the side surface of the first semiconductor layer in the interlayer insulating film;

A fourth step of depositing a second semiconductor layer on the interlayer insulating film and on the inner surface of the contact hole;

A fifth step of depositing a metal layer on the second semiconductor layer;

A sixth step of removing the second semiconductor layer and the metal layer on the interlayer insulating film.

52. In the method for manufacturing a semiconductor device according to claim 51,

A method for manufacturing a semiconductor device, wherein the fourth step is performed by depositing while introducing impurities into the second semiconductor layer.

53. In the method for manufacturing a semiconductor device according to claim 51,

The sixth step is

A seventh step of polishing the metal layer until the second semiconductor layer on the interlayer insulating film is exposed by a CMP method using the second semiconductor layer as a polishing stopper;

An eighth step of removing the second semiconductor layer on the interlayer insulating film by etching.

54. In the method for manufacturing a semiconductor device according to claim 53,

A method of manufacturing a semiconductor device, characterized in that in the eighth step, overetching is performed to a thickness equal to or greater than the thickness of the second semiconductor layer.

55. The method for manufacturing a semiconductor device according to claim 51, wherein polycrystalline silicon is deposited in the fourth step.

56. The method of manufacturing a semiconductor device according to claim 51, wherein a silicon-germanium mixed crystal is deposited in the fourth step. Manufacturing method.

5 7. A first step of forming an island-shaped first semiconductor layer on the insulating layer;

A second step of forming a gut insulating film on the first semiconductor layer,

A third step of depositing a conductive film and a first insulating film on the gate insulating film, respectively;

Patterning the conductive film and the first insulating film; A fourth step of forming an electrode;

A fifth step of performing ion implantation using the gate electrode and the first insulating film as a mask to form a source and a drain in the first semiconductor layer;

A sixth step of depositing a second insulating film;

A seventh step of flattening the surface after depositing a third insulating film having a selectivity of etching with respect to the second insulating film;

An eighth step of removing the third insulating film by etching using a photomask having an opening straddling the source drain and the gate electrode, and the second insulating film exposed by anisotropic etching A ninth step of forming a sidewall spacer on the side surface of the gate electrode, a tenth step of depositing a second semiconductor layer,

A first step of depositing a metal layer;

A second step of polishing the metal layer using the second semiconductor layer as a polishing stopper to expose the second semiconductor layer on the first insulating film;

13. A method for manufacturing a semiconductor device, comprising: a step of removing the second semiconductor layer on the first insulating film by etching.

5 8. In the eighth step,

The manufacturing method of the semiconductor device according to claim 57, wherein a photomask having an opening having a size equal to or larger than that of the first semiconductor layer after the seventh step is used. Method.

5 9. In the above-mentioned 13th step, 58. The method of manufacturing a semiconductor device according to claim 57, wherein etching is performed until an upper surface of said second semiconductor layer is lower than an upper surface of said first insulating layer.

60. The method according to claims 57 to 59, wherein a silicon nitride film is used as the first and second insulating films, and a silicon oxide film is used as the third insulating film. Of manufacturing a semiconductor device. .

6 1. A first step of forming an island-shaped first semiconductor layer on the insulating layer;

A second step of forming a gate insulating film on the first semiconductor layer,

A fourth step of patterning the conductive film and the first insulating film to form a gate electrode made of the conductive film;

A fifth step of performing ion implantation using the good electrode and the first insulating film as a mask to form a source and a drain in the first semiconductor layer;

A sixth step of depositing a second insulating film;

An eighth step of removing the third insulating film by etching using a photomask having an opening over the source / drain and the gate electrode, and the second insulating film exposed by anisotropic etching. A ninth step of removing the film by the thickness thereof and forming a sidewall spacer on the side surface of the gate electrode; Etching the first semiconductor layer using the first insulating film and the sidewall spacers as a mask, and exposing at least a part of the side surface of the first semiconductor layer. When,

A first step of depositing a second semiconductor layer;

A first and second step of depositing a metal layer;

A thirteenth step of polishing the metal layer using the second semiconductor layer as a polishing stopper and exposing the second semiconductor layer on the first insulating film;

A 14th step of removing the second semiconductor layer on the first insulating film by etching.

6 2. In the eighth step,

31. The manufacturing method of a semiconductor device according to claim 61, wherein a photomask having an opening having a size equal to or larger than that of the first semiconductor layer after the seventh step is used. Method. '

6 3. In the first fourteenth step,

62. The method of manufacturing a semiconductor device according to claim 61, wherein etching is performed until an upper surface of said second semiconductor layer is lower than an upper surface of said first insulating layer.

64. Between the tenth step and the eleventh step, there is a step of performing isotropic etching on the insulating layer to expose a part of a bottom surface of the first semiconductor layer. The method for manufacturing a semiconductor device according to claim 61, wherein:

65. The third insulating film is formed by using a silicon nitride film as the first and second insulating films. 65. The method for manufacturing a semiconductor device according to claim 61, wherein a silicon oxide film is used as the film.