WO2001057930A1 - Dispositif a semi-conducteur et son procede de fabrication - Google Patents

Dispositif a semi-conducteur et son procede de fabrication Download PDF

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Publication number
WO2001057930A1
WO2001057930A1 PCT/JP2000/000564 JP0000564W WO0157930A1 WO 2001057930 A1 WO2001057930 A1 WO 2001057930A1 JP 0000564 W JP0000564 W JP 0000564W WO 0157930 A1 WO0157930 A1 WO 0157930A1
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Prior art keywords
layer
semiconductor device
semiconductor
semiconductor layer
silicon
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PCT/JP2000/000564
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English (en)
Japanese (ja)
Inventor
Tsuyoshi Kachi
Dai Hisamoto
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Hitachi, Ltd.
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Priority to PCT/JP2000/000564 priority Critical patent/WO2001057930A1/fr
Priority to AU2000223245A priority patent/AU2000223245A1/en
Priority to TW089102546A priority patent/TW454296B/zh
Publication of WO2001057930A1 publication Critical patent/WO2001057930A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/78654—Monocrystalline silicon transistors

Definitions

  • the present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having an SOI (Silicon On Insulator) structure.
  • SOI Silicon On Insulator
  • MISFETs Metal Insulator Semiconductor Field Effect Transistors
  • the MISF ET in which the channel region is completely depleted by making the thickness of the SOI layer extremely small to several tens of nm or less, the so-called fully depleted SOI MISFET, has a neutral region in the channel region.
  • the parasitic capacitance of the source and drain can be reduced, and steep subthreshold characteristics can be obtained.
  • the thickness of the source and drain regions is determined by the thickness of the SO I layer, the thickness of the S I I layer is lower than that of the MIS FET using a Balta substrate.
  • the source / drain resistance created by the diffusion layer of this type increases, and in particular, the increase in source resistance has the problem that the current driving capability of the MISFET is significantly reduced.
  • the reasons for the increase in parasitic resistance at the source and drain are considered as follows.
  • the source-drain parasitic resistance can be broadly divided into the so-called diffusion layer resistance and the contact resistance between the diffusion layer and the metal layer that is the wiring.
  • the resistance of the metal layer is negligible compared to these.
  • FIG. 1 is a cross-sectional view of a MISFET using a bulk substrate.
  • 500 is a gate electrode
  • 1200 is a source / drain diffusion layer formed in a silicon substrate
  • 110 is a metal layer made of silicide formed on the surface of the source / drain diffusion layer.
  • the arrows in FIGS. 1 and 1 indicate the current path from the channel in the diffusion layer 1200 to the metal layer 110 when a current flows from the wiring 1306 to the wiring 1305.
  • the thick dotted line indicates the surface of the contact surface between the metal layer 110 and the diffusion layer 1200 through which current flows.
  • the current path described above largely spreads in the diffusion layer 1200 so as to have a wider passage surface because of the large contact resistance between metal and silicon.
  • Such a passing surface becomes an electrically effective contact area. Therefore, even if the contact resistance is large, the effective contact area is large, and the parasitic resistance can be reduced.
  • Conventional techniques for solving the problem of increased parasitic resistance include, for example, a method of thinning the surface of the source / drain region into silicide (Imai et al., 1998 Symposium on VSI Technology, Digest p.ii6), A method of thinning the SOI layer only in the region (M. Chan et al., 1994 i-triple electron device letter vol.15 p.24) has been proposed.
  • these conventional techniques cannot be applied when the thickness of the SOI layer is further reduced, so that the problem has not been essentially solved.
  • a first object of the present invention is to provide a semiconductor device having a high-performance SOI MISFET that can prevent an increase in source / drain parasitic resistance even when the SOI layer becomes thin. It is in.
  • a second object of the present invention is to provide a method of manufacturing a semiconductor device suitable for miniaturizing the SOI MISFET.
  • the first object is to provide a contact hole exposing the side surface of the SOI layer and a silicon-containing semiconductor layer formed on the bottom surface and the side surface of the contact hole (for example, a polycrystalline silicon film or a silicon-germ film mixture). And a metal film formed so as to fill the contact hole on the silicon-containing semiconductor layer, and the electrical connection with the source / drain of the SOI MISFET is made from the side of the SOI layer. This is achieved by a semiconductor device having a structured structure.
  • the side surface of the SOI layer is in contact with the semiconductor layer containing silicon, and the contact resistance at this contact surface is smaller than the contact resistance between the SOI layer and the metal layer. Since it is very small, the increase in the contact resistance component when the SOI layer is thinned can be minimized.
  • the contact resistance between the semiconductor layer containing silicon and the metal layer was large in the past, the content of impurities and the thickness of the semiconductor layer containing silicon can be controlled appropriately to control the semiconductor containing silicon.
  • the resistance of the layer can be reduced, the current path can be widened sufficiently in the semiconductor layer containing silicon, the effective contact area with the metal layer can be increased, and the overall parasitic resistance can be reduced. it can.
  • the second object is to provide a step of forming an SOI MISFET in which at least the side surface and the upper side of the gate electrode are covered with a first insulating film, and an etching selectivity with respect to the first insulating film.
  • Forming a contact hole exposing each of the source and drain diffusion layers of the SOI layer; and depositing a silicon-containing semiconductor layer on the inner surface of the contact hole and the second insulating film.
  • First and second absolute Is by connection achieved a method of manufacturing a semiconductor device including the step of etching until the lower than the upper surface of the film.
  • a large contact hole is formed over the source, gate electrode, and drain.
  • the semiconductor layer containing silicon is buried with a laminated film of a semiconductor layer containing silicon and a metal layer, the semiconductor layer containing silicon is polished by using the semiconductor layer containing silicon as a polishing stopper, and the exposed semiconductor layer containing silicon is removed by etching. Since the source and drain are electrically isolated, it is not necessary to keep a predetermined distance between each contact hole, which is essential when forming contact holes for each of the source and drain.
  • S FET can be miniaturized. [Brief description of drawings]
  • FIG. 1 is a cross-sectional view of a typical element for explaining the problem of the conventional structure.
  • FIG. 2 is a cross-sectional view of a typical element for explaining the problem of the conventional structure.
  • FIG. 3 is an element cross-sectional structure diagram for explaining the first embodiment of the present invention.
  • FIG. 4 is a plan layout diagram for explaining a photomask pattern used in the element manufacturing process.
  • FIG. 5 is a cross-sectional structure diagram for explaining a device manufacturing process.
  • FIG. 6 is a sectional structural view for explaining the element manufacturing process.
  • FIG. 7 is a cross-sectional structure diagram illustrating a device manufacturing process.
  • FIG. 8 is a cross-sectional structural view for explaining a device manufacturing process.
  • FIG. 9 is a cross-sectional structure diagram illustrating an element manufacturing process.
  • FIG. 10 is a cross-sectional structure diagram for explaining a device manufacturing process.
  • FIG. 11 is a cross-sectional structure diagram illustrating an element manufacturing process.
  • FIG. 12 is a sectional structural view for explaining the element manufacturing process.
  • FIG. 13 is a cross-sectional structure diagram illustrating a device manufacturing process.
  • FIG. 14 is a cross-sectional structure diagram illustrating an element manufacturing process.
  • FIG. 15 is a sectional structural view for explaining the element manufacturing process.
  • FIG. 16 is a cross-sectional structure diagram illustrating a device manufacturing process.
  • FIG. 17 is a sectional structural view for explaining the element manufacturing process.
  • FIG. 18 is a sectional view of an element for explaining another element isolation method.
  • FIG. 19 is an element cross-sectional structure diagram for explaining still another element isolation method.
  • FIG. 11 is a cross-sectional structure diagram illustrating an element manufacturing process.
  • FIG. 12 is a sectional structural view for explaining the element manufacturing process.
  • FIG. 13 is a
  • FIG. 20 is an element cross-sectional structure diagram for explaining a second embodiment of the present invention.
  • FIG. 21 is an element cross-sectional structure diagram for explaining a third embodiment of the present invention.
  • FIG. 22 is a cross-sectional structural view of an element for explaining a fourth embodiment of the present invention.
  • FIG. 23 is an element cross-sectional structure diagram for explaining a fifth embodiment of the present invention.
  • FIG. 24 is a sectional structural view for explaining another element manufacturing process.
  • FIG. 25 is a sectional structural view for explaining another element manufacturing process.
  • FIG. 26 is a sectional structural view for explaining another element manufacturing process.
  • FIG. 27 is a sectional structural view for explaining another element manufacturing process.
  • Figure FIG. 28 is a sectional structural view for explaining another element manufacturing process.
  • FIG. 29 is a sectional structural view for explaining another element manufacturing process.
  • FIG. 30 is a cross-sectional structure diagram illustrating another element manufacturing process.
  • FIG. 31 is a sectional structural view for explaining another element manufacturing process.
  • FIG. 32 is a sectional structural view for explaining another element manufacturing process.
  • FIG. 33 is a sectional structural view for explaining another element manufacturing process.
  • FIG. 34 is a sectional structural view for explaining another element manufacturing process.
  • FIG. 35 is a sectional structural view for explaining another element manufacturing process.
  • FIG. 36 is a sectional structural view for explaining another element manufacturing process.
  • FIG. 37 is a cross-sectional view illustrating another element manufacturing process.
  • FIG. 38 is a sectional structural view for explaining another element manufacturing process.
  • FIG. 39 is a sectional structural view for explaining another element manufacturing process.
  • FIG. 30 is a cross-sectional structure diagram illustrating another element manufacturing process.
  • FIG. 31 is a sectional structural view for explaining another element manufacturing process.
  • FIG. 40 is a sectional structural view for explaining another element manufacturing process.
  • FIG. 41 is a plan layout diagram for explaining a seventh embodiment of the present invention.
  • FIG. 42 is a sectional view of an element for explaining a seventh embodiment of the present invention.
  • FIG. 43 is a plan layout diagram for explaining an eighth embodiment of the present invention.
  • FIG. 44 is a sectional structural view for explaining an element manufacturing process according to the eighth embodiment of the present invention.
  • FIG. 45 is a sectional structural view for explaining an element manufacturing process for explaining an eighth embodiment of the present invention.
  • FIG. 46 is an equivalent circuit diagram for explaining the ninth embodiment of the present invention.
  • FIG. 47 is a plan layout diagram for explaining an eighth embodiment of the present invention.
  • FIG. 41 is a plan layout diagram for explaining a seventh embodiment of the present invention.
  • FIG. 42 is a sectional view of an element for explaining a seventh embodiment of the present invention.
  • FIG. 43 is a plan layout diagram for explaining an eighth embodiment of the present invention.
  • FIG. 48 is a sectional structural view for explaining the element manufacturing process of the tenth embodiment of the present invention.
  • FIG. 49 is a sectional structural view for explaining the element manufacturing process of the tenth embodiment of the present invention.
  • FIG. 50 is a sectional structural view for explaining the device manufacturing process of the tenth embodiment of the present invention.
  • FIG. 51 is a sectional structural view for explaining the element manufacturing process of the tenth embodiment of the present invention.
  • FIG. 52 is a sectional structural view for explaining the element manufacturing process of the tenth embodiment of the present invention.
  • FIG. 53 shows a tenth embodiment of the present invention. It is sectional structure drawing explaining an element manufacturing process.
  • FIG. 3 is a schematic diagram showing a cross-sectional structure of the semiconductor device according to the first embodiment of the present invention.
  • Reference numeral 200 denotes a support substrate made of, for example, high-resistance single-crystal silicon.
  • Reference numeral 210 denotes an insulating layer formed on the supporting substrate 200.
  • c 201 made of silicon dioxide is a semiconductor region of the first conductivity type patterned on the insulating layer 210. For example, it is made of single crystal silicon.
  • the semiconductor region 201 of the first conductivity type is the SOI layer.
  • a source / drain region (diffusion layer) 213 of a second conductivity type opposite to the first conductivity type is formed in the SOI layer.
  • Reference numeral 211 denotes an element isolation insulating film, for example, silicon dioxide.
  • Reference numeral 202 denotes a gate insulating film made of, for example, silicon dioxide.
  • Reference numeral 203 denotes a gate electrode, which is made of, for example, a polycrystalline silicon film, a multi-layer film of polycrystalline silicon and a metal such as tungsten, or a metal film such as tungsten, titanium nitride, and tungsten nitride. Note that a silicon-germanium mixed crystal may be used instead of the polycrystalline silicon.
  • Reference numeral 205 denotes a sidewall spacer made of an insulating film such as silicon nitride.
  • Reference numerals 206 and 207 denote first extraction electrodes, and a silicon-containing half made of polycrystalline silicon or a polycrystalline silicon-germanium mixed crystal in contact with the diffusion layer 213 on the side surface of the SOI layer 201.
  • Guidance It has a laminated structure of a body layer 206 and a metal layer 207 made of tungsten or the like.
  • Reference numeral 208 denotes a second extraction electrode, and reference numeral 209 denotes a distribution layer, which is made of, for example, tungsten, copper, or aluminum.
  • Reference numerals 2 12 and 2 14 are interlayer insulating films, for example, made of silicon dioxide.
  • the silicon-containing semiconductor layer 206 formed of polycrystalline silicon or silicon-germanium mixed crystal has a thin SOI layer 201. It is in contact with the side of the diffusion layer 2 13 formed inside.
  • the SOI layer 201 and polycrystalline silicon are of the same material and do not create an electrical barrier at the contact surface. Also, even in a silicon-germanium mixed crystal, when a high concentration of impurities is doped to make the material conductive, no barrier is formed for electrons. Therefore, the SOI layer 201 and the silicon-containing semiconductor layer 2 • 6 are electrically connected with little contact resistance. Further, the silicon-containing semiconductor layer 206 is formed so as to cover the lower side surface and the lower surface of the metal layer 207.
  • the current path flowing from the SOI layer 201 spreads in the silicon-containing semiconductor layer 206 and can flow to the metal layer 207.
  • a contact area between the metal layer 207 having a large contact resistance and the silicon-containing semiconductor layer 206 can effectively secure a wide contact area.
  • FIG. 3 shows a structure in which the entire surface of the side surface of the SOI layer 201 is in contact with the silicon-containing semiconductor layer 206.
  • the SOI layer 201 may be left between the semiconductor layer 206 and the insulating layer 210, and the silicon-containing semiconductor layer 206 may be in contact with a part of the side surface of the SOI layer 201.
  • the resistance of the diffusion layer between the silicon-containing semiconductor layer 206 and the insulating layer 210 becomes extremely large, and the effective contact area between the lead electrode and the SOI layer 201 becomes smaller. 20
  • One part of the side is one part of the side.
  • the metal layer 207 is part of the side surface of the SOI layer 201.
  • the source / drain parasitic resistance due to thinning of the SOI layer is the same as when the entire surface of the side surface of the SOI layer 201 is in contact with the silicon-containing semiconductor layer 206 because the entire surface of the SOI layer 201 is in contact with the silicon-containing semiconductor layer 206. The increase can be kept small.
  • the parasitic resistance of the source and drain can be made smaller than when the silicon-containing semiconductor layer 206 is in contact with a part of the side surface of the SOI layer 201.
  • FIG. 4 shows a photomask pattern for processing and forming the semiconductor device according to the first embodiment of the present invention.
  • the rectangular pattern 1 • 1 shown by the bold line is used for patterning the SOI layer and defining the active region.
  • a gate electrode pattern 102 is laid out so as to straddle the pattern 101.
  • the pattern 103 is a pattern of a contact hole for forming a first extraction electrode.
  • the pattern 104 is a pattern for opening a contact hole on the gate electrode.
  • the pattern 105 is used to open a contact hole for forming a second extraction electrode on the first extraction electrode. It is a pattern of.
  • the pattern 106 is a pattern for processing the wiring layer c .
  • the cross-sectional structure of the semiconductor device shown in FIG. 3 corresponds to the cross section AA in FIG.
  • the surface of the SOI substrate on which the SOI layer 201 is formed via the insulating layer (buried oxide film) 210 on the support substrate 200 is thermally oxidized by about 10 nm to form the protective oxide film 222.
  • a silicon nitride film 221 is deposited on the protective oxide film 222 by a CVD method, the silicon nitride film 221 is processed by the photomask pattern 101 shown in FIG. 2, and the silicon nitride film 221 is further protected by using the silicon nitride layer 221 as a mask.
  • the oxide film 222 and the SOI layer 201 are processed (FIG. 5).
  • a silicon oxide film 223 is deposited thereon by a CVD method (FIG. 6). Thereafter, the silicon nitride film 221 and the protective oxide film 222 are polished and flattened by CMP (Chemical Mechanical Polishing) using the silicon nitride film 221 as a stopper, and then removed by wet etching (FIG. 7). As a result, an inter-element isolation insulating film 211 is formed.
  • CMP Chemical Mechanical Polishing
  • the surface of the SOI layer 201 is thermally oxidized by about 2 nm to form a gut insulating film 202, and then a silicon-germanium mixed crystal 203 doped with a high concentration of polon is deposited to a thickness of about 100 nm.
  • a silicon-germanium mixed crystal 203 doped with a high concentration of polon is deposited to a thickness of about 100 nm.
  • about 150 nm, and about 100 nm of silicon nitride 224 (Fig. 8).
  • the silicon nitride film 224 is patterned by the photomask pattern 102 shown in FIG. Then, using the silicon nitride film 224 as a mask, the silicon oxide film 204 and the silicon / germanium mixed crystal 203 are patterned to form a gate electrode 203 (FIG. 9).
  • the gate insulating film 202 may be an oxynitride film obtained by nitriding a thermal oxide film or a laminated film of an oxidized film and a nitride film.
  • the gate electrode 203 may be a polycrystalline silicon, a laminated film of silicon-germanium mixed crystal and a metal, or a metal alone.
  • an impurity is implanted into the SOI layer 201 by ion implantation to form a diffusion layer 213, and then the silicon nitride film 225 is formed by CVD to a thickness of about 50%.
  • Deposit nm Fig. 10
  • an interlayer insulating film 214 is deposited by about 5 O Onm, its surface is flattened by the CMP method (FIG. 11).
  • the interlayer insulating film 214 is formed of a silicon oxide film, an organic insulating film, or the like.
  • the polishing amount by the CMP method is arbitrary as long as it is necessary for flattening the surface. However, the greater the amount, the easier the subsequent contact processing step becomes.
  • the interlayer insulating film 214 is removed by dry etching.
  • This dry etching method is desirably performed under the condition that the selectivity between the interlayer insulating film 214 and the silicon nitride film 225 is high (FIG. 12).
  • the silicon nitride film 225 is etched away by the anisotropic dry etching method to the thickness.
  • a sidewall spacer 205 made of silicon nitride is left on the side surface of the gate electrode 203.
  • the SOI layer 201 is etched and removed until the insulating layer 210 is exposed, exposing the entire side surface of the SOI layer 201 (see FIG. 13 ) .
  • the etching may be stopped in a state where the SOI layer 201 is slightly left on the insulating layer 210. In this case, contact is made by utilizing a part of the side surface of the SOI layer 201.
  • a polycrystalline silicon film 206 is deposited to a thickness of about 50 nm by the CVD method, and is then conducted by ion-implanting an impurity corresponding to the conductivity type of the source and drain of the transistor.
  • a titanium nitride multilayer film 207 is deposited to a thickness of about 300 nm by CVD and sputter deposition (Fig. 14).
  • a silicon-germanium mixed crystal film may be used instead of the polycrystalline silicon film.
  • ion implantation after the deposition may be omitted by depositing the polycrystalline silicon film 206 while doping with impurities. This method is more preferable because it simplifies the process and makes the impurity concentration in the polycrystalline silicon film 206 uniform.
  • the tungsten / titanium nitride laminated film 207 is polished by the CMP method.
  • the polycrystalline silicon film 206 is used as a polishing stopper, and the CMP method is used until the polycrystalline silicon film 206 on both the interlayer insulating film 214 and the gate electrode 203 is exposed. Polishing is performed (Fig. 15).
  • the exposed polycrystalline silicon film 206 on interlayer insulating film 214 and above gate electrode 203 is removed by dry etching. By this dry etching process, the source and drain are electrically separated. ( Figure 16).
  • the upper surface be lower than each upper surface of the insulating film (silicon nitride film 224) above the interlayer insulating film 214 and the gate electrode 203.
  • the source and drain contact holes are not formed by using a photomask pattern having openings corresponding to the source and the drain, but are formed to the same degree as the SOI layer.
  • a photomask pattern with openings of the above sizes the source and drain contact holes are collectively opened, and the conductor buried in the source contact hole and the conductor buried in the drain contact hole It is characterized in that the separated conductive material is electrically separated later. Therefore, in the conventional method, it is difficult to miniaturize the SOIMISFET because a predetermined interval is required between each contact hole of the source and the drain, whereas in the method of the present embodiment, it is difficult to miniaturize the SOIMISFET. Can be easily achieved.
  • an interlayer insulating film 212 is deposited and planarized again by the CMP method, and then a contact hole is opened by the photomask pattern 105 shown in FIG. 2 (FIG. 17). Thereafter, metal layers 208 and 209 are deposited, and the wiring layer is processed according to the photomask pattern 106 shown in FIG. 2, whereby the semiconductor device of the first embodiment shown in FIG. 1 is formed. .
  • the element isolation method is not limited to the method described with reference to FIGS. 5 to 7.
  • a deep groove may be formed by ching, and then the steps shown in FIGS. 6 and 7 may be performed.
  • the silicon nitride film 222 shown in FIG. Alternatively, the protective oxide film 222 may be removed, and then the process of FIG. 8 may be performed.
  • FIG. 20 is a schematic diagram showing a cross-sectional structure of a semiconductor device according to the second and second embodiments of the present invention.
  • the silicon-containing semiconductor layer 206 covers the entire side surface of the sidewall spacer 205, the gate electrode 203 and the first extraction electrode 205 are formed. 6, 2 0 issues force s that a large parasitic capacitance is generated between the 7. '
  • This embodiment is to improve the problem while securing the contact area with the side surface of the SOI layer 201, and the upper surface of the silicon-containing semiconductor layer 206 is made higher than the upper surface of the SOI layer 201. And a range lower than the center of the gut electrode 203 in the height direction. Also, in this embodiment, in order to compensate for the limited space of the upward current path in the silicon-containing semiconductor layer 206, the first extraction electrodes 206 and 207 are formed. A contact hole is formed inside the insulating layer 210, and a part of the silicon-containing semiconductor layer 206 and the metal layer 20'7 is buried also in the insulating layer 201, and the silicon-containing semiconductor layer 206 is formed. The space to spread the current path downward in the middle is secured. , ⁇ Embodiment 3>
  • FIG. 21 is a schematic diagram showing a cross-sectional structure of a semiconductor device according to a third embodiment of the present invention.
  • This embodiment has a structure in which not only the side surface of the SOI layer 201 but also a part of the bottom surface is used as a contact surface between the diffusion layer 21 3 and the silicon-containing semiconductor layer 206.
  • Such a structure can be realized by adding a step of isotropically etching the insulating layer 210 after the step shown in FIG.
  • the contact area between the diffusion layer 211 and the silicon-containing semiconductor layer 206 is made as large as possible, so that the contact resistance can be further reduced.
  • FIG. 22 shows a cross-sectional structure of a semiconductor device according to a fourth embodiment of the present invention prepared by this method. ''
  • the distance from the end of the gate electrode 203 to the extraction electrodes 206 and 207 can be formed arbitrarily, the parasitic capacitance between the two can be reduced. Further, in this embodiment, since a distance from an arbitrary gate end can be ensured, a device with a high withstand voltage can be formed by further increasing the distance between the two only on the drain side. Also in this embodiment, the contact holes for the source and the drain are formed so that the side surfaces of the diffusion layer 211 in the SOI layer are exposed, and the semiconductor layer containing silicon is formed on the side surface of the diffusion layer 211. A metal layer 207 having a contact area with the silicon-containing semiconductor layer 206 larger than the contact area between the diffusion layer 213 and the silicon-containing semiconductor layer 206 is formed. It is similar to each of the above embodiments in that it is formed, and the parasitic resistance can be reduced even when the SOI layer is thin.
  • the present invention relates to a semiconductor device using the SOI layer (eg, a resistor, a bipolar transistor, etc.). Then, it is applicable not only to SOIMISFET.
  • FIG. 23 is a schematic diagram showing a cross-sectional structure of a semiconductor device according to a fifth embodiment of the present invention applied to a diode formed in an SOI layer as an example.
  • the extraction electrode electrically connected to the n-type diffusion layer 1 210 and the p-type diffusion layer 122 0 contains polycrystalline silicon or silicon-genolemanium mixed crystal formed on the side and bottom surfaces. It comprises a semiconductor layer 1206 and a metal layer 1207 formed on the inside thereof, and the silicon-containing semiconductor layer 1206 on the side surface of the extraction electrode is an n-type diffusion layer 1210 It is in contact with the side surface of the p-type diffusion layer 122.
  • FIG. 24 to FIG. 40 are cross-sectional structural views in each step of another manufacturing method according to the present invention.
  • CMOS in which both an NMOS and a PMOS are formed in one SOI layer will be described.
  • a protective oxide film (not shown) is formed by thermally oxidizing the surface of the SOI substrate having the S ⁇ I layer 1101 formed on the supporting substrate via the insulating layer 1910, and then nitriding on the protective oxide film.
  • a silicon film 1950 is deposited by a CVD method.
  • a groove is formed in the insulating layer 1910 using the silicon nitride film 1950 as a mask.
  • a silicon oxide film 1960 is deposited so as to fill the formed groove (FIG. 24).
  • p-type and n-type impurities are respectively introduced in advance into each of the NMOS and PMOS formation regions.
  • the silicon nitride films 1950 and 1955 are polished by polishing.
  • the silicon nitride films 195 and 195 and the protective oxide film are removed (FIG. 26).
  • a gate insulating film is formed on the surface of the SOI layer 1101, and a laminated gate electrode is formed on the gate insulating film as shown in FIG.
  • the work function can be changed by the combination of germanium and silicon.
  • the gate insulating film has an oxynitride film or a stacked structure of an oxide film and a nitride film, it is known that the charge in the film shifts the threshold value of the transistor to the negative side as compared with the oxide film.
  • a silicon / germanium mixed crystal 150, tungsten nitride (not shown), tungsten 15010, and a silicon oxide film 1925 were laminated in this order from the bottom to form a laminated gate electrode.
  • a source / drain diffusion layer 123 was formed by ion implantation (FIG. 27).
  • a silicon-germanium mixed crystal 1370 is deposited to a thickness of 300 nm and its surface is planarized by CMP (Fig. 29). At this time, the silicon-germanium mixed crystal 1370 is removed until the surface of the silicon oxide film 1925 is exposed. Further, a silicon oxide film of about 5 nm may be interposed under the silicon-germanium mixed crystal 1370.
  • the silicon-germanium mixed crystal 1370 is etched using a resist film (not shown) covering a portion facing the SOI layer 111 (FIG. 30).
  • the steps formed by the gate electrodes 1510 and 1500 prevent the removal of the silicon-germanium mixed crystal 1370, but the gate electrodes 1510 and 1500 Since it is protected by the thick oxide films 1925, 1935, the silicon-germanium mixed crystal 1370 in the element isolation region can be completely removed by performing sufficient overetching.
  • an interlayer insulating film 1945 made of silicon oxide film it is flattened by the CMP method so that the upper surface of the silicon-germanium mixed crystal 1370 is exposed (FIG. 31).
  • the silicon-germanium mixed crystal 1370 is etched using hydrogen peroxide solution and ammonia to expose the SOI layer 1230 (Fig. 32), and then the interlayer insulating film 1945 is laminated. Etching is performed using the gate electrodes 1925, 1510, 1500 and the sidewall / resistor 1935 as masks (Fig. 33). At this time, on the SOI substrate, there is no material other than silicon-germanium mixed crystal that can be etched by hydrogen peroxide and ammonia, so that silicon-germanium mixed crystal 1370 can be completely removed. Silicon / germanium mixed crystal When a silicon oxide film is laid, the silicon oxide film is etched and then the SOI layer 1230 is etched.
  • polycrystalline silicon can be used instead of silicon-germanium mixed crystal 1370.
  • a choice of a silicon oxide film is made. For example, dry etching with SF 6, wet etching with hydrazine, or the like may be used.
  • the surface of the diffusion layer 1230 of the S ⁇ I layer 1101, which is exposed on the side surface, is cleaned.
  • the surface area of the exposed S SI layer 1101 can be increased by lightly etching the insulating layer 1910.
  • the NMOS formation region is doped with phosphorus, and the PMOS formation region is doped with boron. 35).
  • an extraction electrode is formed together with the silicon-germanium mixed crystal 1 206 Deposit 605.
  • heat treatment may be required in the subsequent steps.
  • tungsten should be deposited after depositing a metal with high heat resistance such as TiN (Fig. 35).
  • the CMP method is applied until the silicon-germanium mixed crystal 1206 on the interlayer insulating film 1945 and the stacked gate electrodes 1925, 1550, 1550 is exposed.
  • the stainless steel 1605 is polished (FIG. 37).
  • the silicon-germanium mixed crystal acts as a polishing stopper because it can secure selectivity to polishing by the CMP method between metals such as tungsten and TiN, and serves as a polishing stopper.
  • the gate electrodes 1925, 1510, and 1500 can be protected.
  • Etch-back removes silicon-germanium mixed crystal 1206 on interlayer insulating film 1945 and laminated gate electrode 1925, 1510, 1500, and removes extraction electrode to gate electrode To separate them into the source side and the drain side (Fig. 38).
  • the gate electrodes 1510 and 1500 are formed of silicon oxide films 1925 and 1993 having a lower dielectric constant than the silicon nitride film. Since it is covered with 5, each parasitic capacitance between the gate electrode and the extraction electrode and between the source / drain diffusion layer and the extraction electrode can be reduced.
  • a silicon nitride film 196 6 is deposited (FIG. 39), an oxidized silicon film 196 7 is deposited, and a silicon oxide film 196 up to the silicon nitride film 196 6 is formed by a wiring pattern. 7 is etched to form a groove, and the contact hole is opened by etching the silicon nitride film 966 between the groove and the lead electrode using the contact pattern. Say it. Then, after depositing a metal film 1615 made of tungsten or copper, the metal film other than the contact holes and grooves is polished and removed by the CMP method (FIG. 40). These steps are wiring forming steps known as a damascene method.
  • the contact holes of the source and the drain are not formed using the pattern of the photomask having openings corresponding to the source and the drain, the source and the drain are not formed.
  • a predetermined interval is not required between the contact holes, and the miniaturization of the SOIMISFET can be easily achieved similarly to the manufacturing method of the above-described embodiment. .
  • FIG. 42 shows an A-A cross-sectional structure of this region after device formation.
  • impurities are also ion-implanted at a high concentration into the silicon-germanium mixed crystal 1206, so that the impurities are diffused into the SOI layer 1101 side and a junction is formed in the SOI layer 1101. It is formed.
  • a so-called heterojunction is formed due to the difference in band gap between silicon-germanium mixed crystal 126 and silicon.
  • the pn junction and the heterojunction can be formed in almost the same area, that is, near the contact surface.
  • the silicon.germanium mixed crystal 1 206 side is n-type and the SOI layer 1101 is p-type, the SOI layer 1
  • the potential barrier against hole injection can be made lower than that of a pn junction formed by silicon, and holes can easily flow to the silicon-germanium mixed crystal 1206 side.
  • holes which are a problem in SOIMISFETs, accumulate in the channel (SOI) portion, and the effect of floating the substrate, which makes transistor operation unstable, can be suppressed.
  • the present invention relates to a transistor element which is a basic element of a semiconductor device, it can be widely used for application devices.
  • An eighth embodiment in which the element according to the present invention is applied to a semiconductor memory device will be described.
  • Fig. 44 is a plan layout diagram when applied to a dynamic random access memory (DRAM), and Figs. 45 and 46 are cross-sectional structures along the line AA in Fig. 44.
  • the folded bit line arrangement is used.
  • the active area 122 and the word lines 157 1 are shown in an array, but the extraction electrodes 126, the data lines 168 1, and the capacitors 170 1 is for only the center two cells.
  • Bold lines in the plan view indicate the lead electrodes 126 formed of a silicon-containing semiconductor layer such as polycrystalline silicon or silicon-germanium mixed crystal.
  • FIG. 45 shows the cross-sectional structure at the stage where the extraction electrodes up to 126 are formed.
  • a DRAM memory cell there is a case where it is required that the integration, that is, the formation can be made smaller than the parasitic resistance.
  • the extraction electrode 126 can be made only by the silicon-containing semiconductor layer. Even in this case, the SOI layer 1 The surface has the effect of reducing the parasitic resistance.
  • Fig. 46 shows the cross-sectional structure at the stage when the extraction electrode 1206 was formed and the capacitor section 1701 was formed. The interlayer insulating film 1983 was deposited to form the data line.
  • an interlayer insulating film 198 4 is deposited again and subjected to a flattening process.
  • a capacitor electrode 1 701 made of a metal layer is formed, and a capacitive insulating film 198 2 made of tantalum is formed.
  • no data line appears in FIG.
  • FIG. 46 shows a memory cell shown by an equivalent circuit.
  • FIG. 47 shows a planar layout of the memory cell.
  • the hatched portion shows a photomask pattern for opening contact holes for extraction electrodes.
  • the pattern 126 may be arranged so as to straddle the gate.
  • the cell boundaries are indicated by 1 130.
  • the SRAM combined with the CMOS inverter, it is necessary to connect the diffusion layers of the NMOS and the PMOS, which are the information storage units.However, the extraction electrode is formed so as to extend between the NMOS and the PMOS.
  • the extraction electrode is used as a wiring connecting each source / drain diffusion layer of a plurality of SOIMISFETs.
  • a parasitic capacitance is generated or a short circuit occurs between electrodes.
  • a thick insulating layer is provided under the SOI layer. Also under the extraction electrode Therefore, the possibility of causing such a problem can be reduced.
  • the extraction electrode in this embodiment is composed of a silicon-containing semiconductor layer in contact with the side surface of the SOI layer and a metal layer in contact with the semiconductor layer. It is configured.
  • FIGS. 48 to 53 show a tenth embodiment showing a method for forming a substrate contact according to the present invention.
  • a higher voltage may be applied to the input section than the outside, and it is effective to form a bipolar element or the like that extracts such a current on the substrate as a protection element against this.
  • a protective element can be formed by using a supporting substrate.
  • a method for forming a contact with a support substrate will be described based on the element manufacturing method described with reference to FIGS.
  • a silicon-germanium mixed crystal 1370 is deposited and planarized by the CMP method, exposing the insulating film 1925 above the gate (FIG. 49).
  • the width of the opening in the support substrate is equal to or less than half that of the mixed crystal to be deposited, the opening can be effectively filled, so that the following steps can be performed without changing the process.
  • Figure 50 Using a photomask pattern with an opening from the substrate contact to the SOIMISFET, process the silicon-germanium mixed crystal 1370 by dry etching up to the element isolation film 1960 I do. After the oxidation film 1945 is deposited, the film is flattened by the CMP method to expose the silicon-germanium mixed crystal 1370 (FIG. 51).
  • the silicon-germanium mixed crystal 1370 is removed by etching to expose the SOI layer 1101 and the supporting substrate 1105 (FIG. 52).
  • a silicon-containing semiconductor layer 1206 and a metal layer 1605 are deposited and processed by CMP and etching (Fig. 53). At this time, a bond can be formed between the silicon-containing semiconductor layer and the support substrate. After the opening in the support substrate, the diffusion layer can be formed by ion implantation.
  • the parasitic resistance of the source and the drain can be reduced in the MI SFET using the thin film SO I, particularly in the fully depleted SO I MIS FET.
  • a high-performance MISFET with a large current driving capability can be provided.
  • a MIS FET using SOI can be miniaturized.
  • the present invention is suitable for application to a semiconductor device using an SOI substrate and a method for manufacturing the same in general. '

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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

La connexion électrique avec la couche diffusée formée dans une couche SOI d'un élément à semi-conducteur contenant la couche SOI, en particulier un MISFET SOI, est réalisée au moyen d'une électrode comprenant une couche à semi-conducteur contenant du silicium en contact avec une face latérale de la couche SOI et une couche métallique en contact avec la couche à semi-conducteur contenant du silicium. La zone du contact entre la couche métallique et la couche à semi-conducteur contenant du silicium est plus grande que celle située entre la couche SOI et la couche à semi-conducteur contenant du silicium. Même si la couche SOI est reconçue pour être plus mince, la résistance aux parasites de la source/du drain diminue peu. Un procédé de fabrication d'un dispositif à semi-conducteur n'utilise aucun photomasque à ouvertures pour la source et le drain, et le MISFET SOI peut être microminiaturisé davantage, produisant ainsi un dispositif à semi-conducteur hautement intégré.
PCT/JP2000/000564 2000-02-02 2000-02-02 Dispositif a semi-conducteur et son procede de fabrication WO2001057930A1 (fr)

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PCT/JP2000/000564 WO2001057930A1 (fr) 2000-02-02 2000-02-02 Dispositif a semi-conducteur et son procede de fabrication
AU2000223245A AU2000223245A1 (en) 2000-02-02 2000-02-02 Semiconductor device and its manufacturing method
TW089102546A TW454296B (en) 2000-02-02 2000-02-15 Semiconductor device and its manufacturing method

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JP2010171444A (ja) * 2010-03-18 2010-08-05 Renesas Electronics Corp スタティック・ランダム・アクセス・メモリ
JP2013089646A (ja) * 2011-10-13 2013-05-13 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法及び半導体装置
JP2013102134A (ja) * 2011-09-23 2013-05-23 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法及び半導体装置
JP2013105852A (ja) * 2011-11-11 2013-05-30 Semiconductor Energy Lab Co Ltd 半導体装置及び半導体装置の作製方法
JP2013211536A (ja) * 2012-03-01 2013-10-10 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法、及び半導体装置
JP2013211529A (ja) * 2012-02-29 2013-10-10 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法

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JPH02246398A (ja) * 1989-03-20 1990-10-02 Fujitsu Ltd 半導体装置の製造方法
JPH0536624A (ja) * 1991-07-26 1993-02-12 Fujitsu Ltd 半導体装置の製造方法及び半導体装置
JPH05299435A (ja) * 1991-03-27 1993-11-12 Semiconductor Energy Lab Co Ltd 絶縁ゲイト型電界効果トランジスタの作製方法
JPH0951101A (ja) * 1995-08-07 1997-02-18 Hitachi Ltd 半導体装置およびその製造方法
US5773331A (en) * 1996-12-17 1998-06-30 International Business Machines Corporation Method for making single and double gate field effect transistors with sidewall source-drain contacts
JPH11177089A (ja) * 1997-12-16 1999-07-02 Hitachi Ltd 半導体装置の製造方法

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JPH02246398A (ja) * 1989-03-20 1990-10-02 Fujitsu Ltd 半導体装置の製造方法
JPH05299435A (ja) * 1991-03-27 1993-11-12 Semiconductor Energy Lab Co Ltd 絶縁ゲイト型電界効果トランジスタの作製方法
JPH0536624A (ja) * 1991-07-26 1993-02-12 Fujitsu Ltd 半導体装置の製造方法及び半導体装置
JPH0951101A (ja) * 1995-08-07 1997-02-18 Hitachi Ltd 半導体装置およびその製造方法
US5773331A (en) * 1996-12-17 1998-06-30 International Business Machines Corporation Method for making single and double gate field effect transistors with sidewall source-drain contacts
JPH11177089A (ja) * 1997-12-16 1999-07-02 Hitachi Ltd 半導体装置の製造方法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010171444A (ja) * 2010-03-18 2010-08-05 Renesas Electronics Corp スタティック・ランダム・アクセス・メモリ
JP2013102134A (ja) * 2011-09-23 2013-05-23 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法及び半導体装置
JP2013089646A (ja) * 2011-10-13 2013-05-13 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法及び半導体装置
JP2013105852A (ja) * 2011-11-11 2013-05-30 Semiconductor Energy Lab Co Ltd 半導体装置及び半導体装置の作製方法
JP2013211529A (ja) * 2012-02-29 2013-10-10 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法
JP2013211536A (ja) * 2012-03-01 2013-10-10 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法、及び半導体装置

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