JP4749134B2 - 自己整合ダブルゲートデバイス及びその形成方法 - Google Patents
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- 239000004065 semiconductor Substances 0.000 claims description 20
- 238000002955 isolation Methods 0.000 claims description 11
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 229910052710 silicon Inorganic materials 0.000 description 11
- 239000010703 silicon Substances 0.000 description 11
- 238000005530 etching Methods 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 150000003377 silicon compounds Chemical group 0.000 description 6
- 229940125936 compound 42 Drugs 0.000 description 5
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 5
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 5
- 229910052721 tungsten Inorganic materials 0.000 description 5
- 239000010937 tungsten Substances 0.000 description 5
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- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
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- 239000000203 mixture Substances 0.000 description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
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- 229910017052 cobalt Inorganic materials 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
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- 238000007796 conventional method Methods 0.000 description 2
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- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- OAKJQQAXSVQMHS-UHFFFAOYSA-N Hydrazine Chemical compound NN OAKJQQAXSVQMHS-UHFFFAOYSA-N 0.000 description 1
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- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 150000002736 metal compounds Chemical class 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- 150000004767 nitrides Chemical class 0.000 description 1
- 229910000069 nitrogen hydride Inorganic materials 0.000 description 1
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- XUIMIQQOPSSXEZ-NJFSPNSNSA-N silicon-30 atom Chemical compound [30Si] XUIMIQQOPSSXEZ-NJFSPNSNSA-N 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
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- 229910052905 tridymite Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
- H01L29/78648—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
- Thin Film Transistor (AREA)
- Element Separation (AREA)
- Semiconductor Memories (AREA)
Description
Claims (9)
- ダブルゲート領域とバルク領域がその上に形成された第1基板と、
前記第1基板の上にあって、前記ダブルゲート領域にのみ形成された埋込絶縁層と、
前記埋込絶縁層と合計した厚さが50nm未満となるように、前記埋込絶縁層の上にのみ形成された第2基板と、
前記第2基板と前記埋込絶縁層とを貫いて延びると共に前記第1基板を途中まで貫いて延びる第1分離領域と、
前記第1分離領域内に基板接点と、
前記ダブルゲート領域に形成されたダブルゲートデバイスと、
前記バルク領域に形成された非ダブルゲートデバイスとを備え、
前記ダブルゲートデバイスは、前記第2基板上に形成されたゲート誘電体と、前記ゲート誘電体上に形成されたゲート電極とを備え、前記ゲート電極の下方にある下部ゲートを前記第1基板内に形成し、前記ゲート電極と前記下部ゲートとの間にあるチャネルと、前記チャネルの両側にあるソース及びドレインを、前記第2基板内に形成してなることを特徴とする半導体構造。 - 前記第1分離領域は、前記埋込絶縁層の下方に10nmより大きい延長部を有するものであることを特徴とする請求項1記載の半導体構造。
- 前記第2基板の上面が、前記バルク領域の上面を超える段高さを有していることを特徴とする請求項1記載の半導体構造。
- 前記バルク領域の面積に対して、前記埋込絶縁層と前記第2基板とを備えた前記ダブルゲート領域の面積の比率が0.5未満であることを特徴とする請求項1記載の半導体構造。
- ダブルゲート領域とバルク領域がその上に形成される第1基板を形成し、
前記第1基板上に埋込絶縁層を形成し、
前記埋込絶縁層と合計した厚さが50nm未満となるように、前記埋込絶縁層上に第2基板を形成し、
前記第1基板上にある前記ダブルゲート領域の部分の前記第2基板及び前記埋込絶縁層を保留しつつ、前記第1基板上にある前記バルク領域の部分の前記第2基板及び前記埋込絶縁層を除去し、
前記第2基板上にマスク層を形成し、
前記第2基板と前記埋込絶縁層を貫いて、前記第1基板内に延びる第1溝を形成し、
前記第1溝を第1分離部で充填し、
前記第1分離部の余分な部分を除去し、
前記マスク層を除去し、
第2溝が前記第1基板を露出するように前記第1分離部に前記第2溝を形成し、導電材料で前記第2溝を充填すると共に、余分な導電材料を除去し、
前記ダブルゲート領域にダブルゲートデバイスを形成し、前記バルク領域に非ダブルゲートデバイスを形成するために、
前記ダブルゲート領域内の前記第2基板上に第1ゲート誘電体を形成すると同時に、前記バルク領域内の前記第1基板上に第2ゲート誘電体を形成し、
前記第1ゲート誘電体上に第1ゲート電極を形成すると同時に、前記第2ゲート誘電体上に第2ゲート電極を形成し、
前記第1ゲート誘電体及び前記第1ゲート電極の両側壁に沿って一対の第1スペーサを形成すると同時に、前記第2ゲート誘電体及び前記第2ゲート電極の両側壁に沿って一対の第2スペーサを形成し、
前記第1スペーサの脇に位置して、前記第2基板内に第1ソース及び第1ドレインを形成し、前記第1ソースと第1ドレインとの間の前記第2基板内をチャネルにし、
前記第2スペーサの脇に位置して、前記第1基板内に第2ソース及び第2ドレインを形成し、
前記上部ゲートの下方に位置して、前記第1基板内に下部ゲートを形成することを特徴とする半導体構造の形成方法。 - 前記埋込絶縁層及び前記第2基板の形成方法は、第1熱酸化物層を形成するために前記第1基板を熱酸化するステップと、前記第1基板と前記第2基板との間を隔てる前記第1酸化物層に前記第1基板と前記第2基板とを結合するステップと、前記第2基板を化学機械研磨(CMP)するステップと、第2熱酸化物層を形成する前記第2基板を熱酸化するステップと、前記第2熱酸化物層を除去するステップとから構成されることを特徴とする請求項5記載の半導体構造の形成方法。
- ダブルゲート構造を有するダブルゲート領域を備え、前記ダブルゲート領域が第1基板上の第1部分に形成された半導体チップであって、
前記ダブルゲート構造は、
前記第1基板の上にあって、前記第1部分にのみ形成された埋込絶縁層と、
前記埋込絶縁層と合計した厚さが50nm未満となるように、前記埋込絶縁層の上方にのみ形成された第2基板と、
前記第2基板と前記埋込絶縁層を横断して前記第1基板内に延びる第1分離領域と、
前記第1分離領域内にある基板接点と、
前記第2基板上に形成されたゲート誘電体と、
前記ゲート誘電体上に形成された上部ゲートと、
前記上部ゲートの下方にあって、前記第1基板内に形成される下部ゲートと、
前記上部ゲートと前記下部ゲートとの間にあって、前記第2基板内に形成されるチャネルと、
前記チャネルの両側にあって、前記第2基板内に形成されるソース及びドレインとを備え、
前記第1基板上の第2部分に、非ダブルゲートデバイスを有するバルク領域が形成されたことを特徴とする半導体チップ。 - 前記バルク領域の合計面積に対して、前記ダブルゲート領域の面積の比率が0.5未満であり、且つ前記バルク領域は前記ダブルゲート構造を有しないものであることを特徴とする請求項7記載の半導体チップ。
- 複数のダブルゲート領域にある複数のダブルゲート構造と、前記ダブルゲート構造を有しておらず、前記複数のダブルゲート領域以外に形成された複数のバルク領域とを備え、半導体チップ上で、前記バルク領域の合計面積に対して、前記ダブルゲート領域の合計面積の比率が0.5未満であるように構成されたことを特徴とする請求項7記載の半導体チップ。
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US10/997,446 | 2004-11-24 | ||
US10/997,446 US7230270B2 (en) | 2004-11-24 | 2004-11-24 | Self-aligned double gate device and method for forming same |
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JP2006148141A JP2006148141A (ja) | 2006-06-08 |
JP4749134B2 true JP4749134B2 (ja) | 2011-08-17 |
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US (1) | US7230270B2 (ja) |
JP (1) | JP4749134B2 (ja) |
CN (1) | CN100378985C (ja) |
TW (1) | TWI302747B (ja) |
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US6521947B1 (en) | 1999-01-28 | 2003-02-18 | International Business Machines Corporation | Method of integrating substrate contact on SOI wafers with STI process |
US6365465B1 (en) * | 1999-03-19 | 2002-04-02 | International Business Machines Corporation | Self-aligned double-gate MOSFET by selective epitaxy and silicon wafer bonding techniques |
JP3523531B2 (ja) * | 1999-06-18 | 2004-04-26 | シャープ株式会社 | 半導体装置の製造方法 |
JP2001320018A (ja) * | 2000-05-08 | 2001-11-16 | Seiko Instruments Inc | 半導体装置 |
DE10054109C2 (de) | 2000-10-31 | 2003-07-10 | Advanced Micro Devices Inc | Verfahren zum Bilden eines Substratkontakts in einem Feldeffekttransistor, der über einer vergrabenen Isolierschicht gebildet ist |
US6498057B1 (en) * | 2002-03-07 | 2002-12-24 | International Business Machines Corporation | Method for implementing SOI transistor source connections using buried dual rail distribution |
US6780686B2 (en) * | 2002-03-21 | 2004-08-24 | Advanced Micro Devices, Inc. | Doping methods for fully-depleted SOI structures, and device comprising the resulting doped regions |
US6664598B1 (en) * | 2002-09-05 | 2003-12-16 | International Business Machines Corporation | Polysilicon back-gated SOI MOSFET for dynamic threshold voltage control |
JP2004146550A (ja) * | 2002-10-24 | 2004-05-20 | Oki Electric Ind Co Ltd | 半導体装置及びその製造方法 |
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2004
- 2004-11-24 US US10/997,446 patent/US7230270B2/en not_active Expired - Fee Related
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- 2005-11-24 CN CNB2005101284228A patent/CN100378985C/zh active Active
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US20060108644A1 (en) | 2006-05-25 |
TW200618163A (en) | 2006-06-01 |
TWI302747B (en) | 2008-11-01 |
CN100378985C (zh) | 2008-04-02 |
CN1797762A (zh) | 2006-07-05 |
US7230270B2 (en) | 2007-06-12 |
JP2006148141A (ja) | 2006-06-08 |
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