JP2000124458A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a manufacturing method of a semiconductor device whereby a semiconductor device with a high breakdown strength MOS type transistor can be manufactured readily at a low cost, by forming a drift region of complete dielectric isolation and a proper thickness by using a semiconductor device with a high breakdown strength MOS transistor, especially an SOI board. SOLUTION: This manufacturing method of a semiconductor device has a process for laminating a second insulation film and a third insulation film one by one on a substrate 101, with at least a first insulation film 102 and a silicon layer 103 comprising impurities of one conductivity type on the first insulation film 102; a process for selectively etching a part of the second insulation film, the third insulation film and the silicon layer 103 for forming an isolation film; a process for selectively etching at least the third insulation film for forming a drift region; and a process for forming an oxide film by selectively oxidizing a part etched for forming the isolation film and an etched part of the third insulation film.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a high withstand voltage MOS transistor, and more particularly to a thin SOI (S
The present invention relates to a method for manufacturing a semiconductor device having a high-breakdown-voltage MOS transistor capable of forming a complete dielectric isolation and forming a drift region having an appropriate thickness by using an silicon-on-insulator substrate.

[0002]

2. Description of the Related Art With the recent demand for higher integration, lower power consumption, and higher speed of semiconductor devices, research and development of semiconductor devices having high withstand voltage and radiation resistance are progressing. For example, JP-A-3-79
080, JP-A-4-78170 or JP-A-8-172189 disclose a high-breakdown-voltage MOS transistor having an offset region (or an offset oxide film). In these, by providing an offset region (or an offset oxide film), the electric field concentration is reduced and a high breakdown voltage is realized.

[0003]

On the other hand, there is known a technique of forming a silicon single crystal layer on an insulator (SOI substrate) to improve device characteristics such as high withstand voltage. This SOI
The technology that uses a substrate reduces stray capacitance, enables higher-speed devices, and eliminates the need for a well formation process.
In recent years, it has attracted particular attention because of its advantages such as high integration and a significant reduction in malfunction due to radiation and the like.

Hereinafter, a conventional method for manufacturing a semiconductor device using this technique will be described with reference to the drawings. In the following, an SOI substrate is used, and trench isolation and L
High breakdown voltage MOS by combining OCOS method
13 illustrates an example of manufacturing a semiconductor device having a transistor.

[0005] First, as shown in FIG.
Support substrate 2 such as an n-type silicon semiconductor substrate having a relatively high concentration
First, an SOI substrate including a buried silicon oxide layer 202 and a silicon single crystal layer 203 into which a relatively low concentration of n-type impurity is introduced is prepared. As described later, this S
The OI substrate can be manufactured by using, for example, a so-called bonding method and an etch-back technique.

Next, as shown in FIG. 4B, a region where a trench element isolation film is to be formed is selectively etched until it reaches the buried silicon oxide layer 202 to form a trench D.
To form Next, a relatively thin silicon oxide film 204 is formed in the trench D and on the entire surface by, for example, a thermal oxidation method.

Further, polysilicon (for example, CVD (Chemical Vapor De) using polysilicon) is formed on the silicon oxide film 204 in the trench D.
The buried silicon layer 205 is formed by burying the film by a position method and then flattening the surface by etching back to form the buried silicon layer 205, thereby obtaining the state shown in FIG.

Next, as shown in FIG. 5D, after removing the silicon oxide film 204, a silicon oxide film 206 and a silicon nitride film 207 are formed on the silicon oxide film 206 over the entire surface. Further, as shown in FIG.
At least the silicon nitride film 207 on the drift region D is selectively removed by etching.

Next, as shown in FIG. 5 (f), the etched portion is, for example, LOCOS (Local Ox).
The silicon oxide film 208 having a large thickness is formed by selective oxidation using an ion of silicon method.

Thereafter, although not shown, a gate oxide film,
A desired semiconductor device having a lateral NMOS transistor can be manufactured by sequentially forming a gate electrode, a source / drain region, a source / drain, and the like.

As described above, a semiconductor device having excellent device characteristics such as high withstand voltage can be obtained by using a combination of trench isolation and LOCOS techniques using an SOI substrate.

However, according to the above-described method, although a semiconductor device having excellent device characteristics such as high withstand voltage can be obtained, the number of steps is increased because both the trench isolation and the LOCOS method are used. However, there is a problem that the cost is relatively high.

Therefore, a semiconductor device having a MOS transistor having excellent device characteristics such as a high withstand voltage can be manufactured more simply and more easily.
In addition, there is a need for a technology that can be manufactured at lower cost.

Therefore, the present invention provides a semiconductor device having a high breakdown voltage MOS transistor, in particular, a thin SOI substrate and a complete dielectric isolation and formation of a drift region having an appropriate thickness. It is an object of the present invention to provide a method for manufacturing a semiconductor device which can manufacture a semiconductor device having a type transistor more simply and at lower cost.

[0015]

According to the present invention, there is provided a substrate having at least a first insulating film and a silicon layer containing an impurity of one conductivity type on the first insulating film. A step of sequentially stacking a second insulating film and a third insulating film thereon, and forming the second insulating film, the third insulating film, and a part of the silicon layer into a device isolation film. A step of selectively etching, at least a step of selectively etching the third insulating film to form a drift region, and a step of etching the portion etched to form the element isolation film and the third insulating film. Provided is a method for manufacturing a semiconductor device, which includes a step of forming an oxide film by selectively oxidizing an etched portion.

In the method of manufacturing a semiconductor device according to the present invention, the substrate having at least the first insulating film and the silicon layer containing one conductivity type impurity on the first insulating film is an SOI substrate. Is preferred.

Preferably, the third insulating film is a film having oxidation resistance when oxidizing the second insulating film and the silicon layer containing the one conductivity type impurity.

In the method of manufacturing a semiconductor device according to the present invention, the first insulating film is a silicon oxide film, the second insulating film is a silicon oxide film, and the third insulating film is More preferably, it is a silicon nitride film.

According to the present invention, there is provided a method of manufacturing a semiconductor device having a MOS transistor, comprising: a substrate having at least a first insulating film and a silicon layer containing an impurity of one conductivity type on the first insulating film. A step of sequentially stacking a silicon oxide film and a silicon nitride film thereon, and a step of selectively etching the silicon oxide film, the silicon nitride film and part of the silicon layer to form an element isolation film, At least the step of selectively etching the third insulating film to form a drift region and the step of simultaneously etching the portion etched for forming the element isolation film and the etched portion of the third insulating film are performed simultaneously.
Forming a silicon oxide film by oxidizing by a COS method; forming a gate oxide film in an element isolation region; forming a gate electrode on the gate oxide film; Forming a channel region, forming a source region and a drain region in the element isolation region of the silicon layer, and forming a source and a drain electrically connected to the source region and the drain region, respectively. And a method of manufacturing a semiconductor device having a MOS transistor.

According to the method of manufacturing a semiconductor device of the present invention,
A semiconductor device having a MOS transistor having a high withstand voltage and the like, and a semiconductor device having a MOS transistor with a high withstand voltage capable of completely forming a dielectric region and forming a drift region having an appropriate thickness can be more simply and It can be manufactured at lower cost.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings according to embodiments of the present invention. FIG.
(I) shows an example of a semiconductor device having a lateral field-effect NMOS transistor manufactured by the method for manufacturing a semiconductor device of the present invention. This semiconductor device includes an SOI substrate including a buried oxide film 102 made of silicon oxide and a silicon single crystal layer 103 doped with a relatively low concentration of n-type impurity on an n-type silicon semiconductor substrate 101 serving as a support substrate. Embedded LOCOS (Rec
Essed LOCOS) A thick LO film is formed on the drift region C of the element isolation region separated by the oxide film 107.
A COS (Non-recessed LOCOS) oxide film 107 and a gate oxide film 108 on the oxide film 107
And a gate electrode 109 interposed therebetween.

Further, a diffusion layer 1 is provided in the element isolation region.
11 and the source diffusion layer 112 are provided in the channel diffusion layer 110 and are electrically connected to the source 115. Drain 1
Reference numeral 16 is provided so as to conduct with the drain diffusion layer 113.

The gate electrode 109 is made of the LOCOS oxide film 1
07 over a short predetermined distance of a small extent,
From the ends of the drain 116 and the source 115 to L
It functions as a field plate so as to reduce a high electric field generated over the drift region C below the OCOS oxide film 107.

Hereinafter, a procedure for manufacturing the semiconductor device shown in FIG. 3 (i) will be described in detail with reference to the drawings. First,
As shown in FIG. 3A, as the supporting substrate, for example, n
An SOI substrate including a silicon semiconductor substrate 101, a buried oxide film 102 made of silicon oxide, and a silicon single crystal layer 103 doped with an n-type impurity such as phosphorus or arsenic at a relatively low concentration is prepared. The thickness of the silicon single crystal layer 103 of the SOI substrate is, for example, 700 to 1000 nm.
Degree.

In the present invention, any substrate having the above-mentioned layer structure can be used without any particular limitation.
It is more preferable to use an OI substrate. In the present embodiment, an example of an SOI substrate using a silicon substrate is described. However, the buried insulating layer may not be a silicon oxide layer. For example, an SOS ( (Silicon on Sapphire) substrate may be used.

The SOI substrate is, for example, a silicon substrate,
A step of implanting oxygen into a predetermined amount and a predetermined depth by an ion implantation method, an oxygen ion implantation method (SIMOX method) for producing an SOI substrate by a high-temperature annealing step at 1300 ° C. or more for crystallinity recovery, and a base wafer. Cleaning and bonding at room temperature with bond wafer covered with oxide film, 1100
After bonding through a bonding annealing process at about 2 ° C. for about 2 hours, bonding is performed, followed by polishing to form a bonded SOI substrate.
In addition to I method, solid phase epi method, lateral vapor phase epi method, FIPO
S (Full Isolation by Puro)
us Oxidized Silicon) method, smart cut method (hydrogen ion implantation method) and the like.

Of the above-described SOI substrate manufacturing methods, the oxygen ion implantation method and the combined SOI method are generally used from the viewpoint of quality and versatility.

Next, as shown in FIG. 1B, a second insulating film 105 and a third insulating film 106 are sequentially stacked on the silicon single crystal layer 103.

In the present invention, the material of the second and third insulating films is not particularly limited. However, as will be described in a later step, a non-reactive oxide film is formed on the element isolation film and the drift region.
A LOCOS oxide film, which is a ESSOC film, is formed in one step by a LOCOS oxidation method. Therefore, when oxidizing the second oxide film and the silicon single crystal layer, it is necessary to form the third oxide film using a substance having oxidation resistance to the oxidation.

For example, a silicon oxide film can be used as the second insulating film, and a silicon nitride film can be used as the third insulating film. When the second insulating film 105 is a silicon oxide film, for example, a thermal oxidation method, SiH ₄ —O ₂ or TEOS (tetraethylorthosilic) is used.
ate) By a CVD method using -O ₂ or the like, for example,
It can be formed with a film thickness of about 50 to 100 nm.

When the third insulating film is a silicon nitride film, for example, a SiH ₄ + O ₂ + N ₂ system or a SiH 4
By a CVD method using a ₄ + N ₂ O-based gas, for example,
It can be formed with a thickness of about 50 to 150 nm.

Next, as shown in FIG. 1C, a resist film (not shown) is formed on the entire surface at a portion where an element isolation film is to be formed, and the third insulating film 106 is formed using the resist film as a mask. , Second insulating film 105 and silicon single crystal layer 10
3 is selectively etched to form an opening. At this time, the depth of the opening A is, for example, about 400 nm from the upper surface of the silicon single crystal layer 103. This depth can be appropriately changed depending on the type of the substrate to be used, the thickness of each layer of the substrate, and the like. The degree of etching depends on the output of the etching apparatus, the etching time, the flow rate of the etching gas, etc.
It can be set appropriately. Etching at this time,
For example, as an etching gas, CF ₄ , CHF ₃ —O
₂ , C ₄ F ₈ + CHF ₃ + O ₂ , S ₂ F ₂ , SF _{6 and the} like can be used.

Thereafter, as shown in FIG. 2D, at least the third insulating film 105 on a region where a drain region is to be formed in the future is selectively removed by etching. At this time,
Although a part of the second insulating film 104 may be etched, it is preferable to perform etching so that the second insulating film 104 remains. The etching at this time is, for example,
CF ₄ , CHF ₃ —O ₂ , C ₄
F ₈ + CHF ₃ + O ₂ , S ₂ F ₂ , SF ₆ or the like can be used. The degree of etching can be appropriately set according to the output of the etching apparatus, the etching time, the flow rate of the etching gas, and the like.

Next, as shown in FIG. 2E, the surface is selectively oxidized by about 1 μm from the surface by a thermal oxidation method. The oxidation temperature at this time is about 1000 to 1300 ° C. By this operation, the LOCOS oxide film 10 is formed in the opening A.
6 is formed, and the oxide film 106 is
To reach 2. By doing so, complete element isolation (dielectric isolation) can be performed. When the size of the opening is small, the opening A
The LOCOS oxide film formed therein has a shape protruding around the opening as shown in FIG.

Further, a LOCOS oxide film 107 is simultaneously formed on the drift region. The lower portion of the oxide film 107 becomes a drift region. By this operation, the drift region can have an appropriate thickness of, for example, about 0.3 to 0.4 μm. By doing so, when the drain is highly biased, the silicon single crystal layer in the drift region is completely depleted, and high breakdown voltage characteristics are secured.

According to the present invention, the above-mentioned recessed LOC is used.
OS oxide film 106 and Non-Recessed LO
The feature is that the COS oxide film 107 is formed simultaneously in the same step. In order to secure an appropriate drift region thickness and achieve complete element isolation, the depth of the opening A and the LOC are determined by the thickness and material of the SOI substrate.
It is necessary to appropriately adjust the degree of OS oxidation.

Next, after the remaining second insulating film 105 is removed, the LO
Over the COS oxide film 107, the gate electrode 109 is
The gate oxide film 108 is formed. Gate oxide film 1
08 can be formed, for example, by depositing a silicon oxide film on the entire surface by a CVD method using SiH ₄ —O ₂ , TEOS—O _2, or the like, and then performing a predetermined patterning and photoetching technique.

The gate electrode 109 can be formed by forming a gate oxide film 108, depositing, for example, polysilicon over the entire surface by a CVD method, and then performing predetermined processing. The gate electrode 109 has a LOC
By extending the OS 11 on the OS oxide film 107 by a predetermined distance as short as possible, the drain 11
6 and the source 115 are formed so as to function as a field plate so as to reduce a high electric field generated from the end of the source 115 to the drift region C under the LOCOS oxide film 107. FIG. 2 shows the structure obtained as described above.
(F).

Then, as shown in FIG. 3G, a p-channel region 110 is formed by ion-implanting an impurity such as boron into the element isolation region where the source is to be formed, and then a drain is formed. The drain diffusion region 113 and the source diffusion region 112 are formed by ion-implanting n-type impurities such as phosphorus and arsenic into the element isolation region and the p-channel region 110 to be formed.
In addition, a p-type impurity such as boron is ion-implanted at a relatively high concentration into a portion where the source diffusion region is not formed in the p-channel region, thereby forming the p ⁺ diffusion layer 111.

Next, as shown in FIG. 3H, an interlayer insulating film 114 is formed on the entire surface. Since it is preferable that the surface of the interlayer insulating film 114 is flat, for example, PH ₃ -B
It can be formed by a CVD method using ₂ H ₆ -TEOS. It is also preferable that the surface is heat-treated after the film is formed, so that the surface is flattened.

Further, the p-channel region 110 and the source diffusion region 112 and the drain diffusion region 11
An opening for forming a source and a drain is formed in the interlayer insulating film 114 on the third layer. The opening can be formed, for example, by using a photo-etching technique using a resist film (not shown) as a mask.

Next, a conductive material such as aluminum, tungsten, an aluminum alloy, a tungsten alloy, copper or a copper alloy is deposited by sputtering,
The structure shown in FIG. 3 (i) is obtained by depositing the entire surface so as to fill the opening by vacuum deposition, vacuum deposition, or the like, and then performing a predetermined process for forming the source and drain. Can be.

Thereafter, a desired semiconductor device can be manufactured by forming an interlayer insulating film on the entire surface and then performing predetermined wiring processing or the like.

According to the present embodiment, the recessed LOCOS oxide film and the non-R
To manufacture a semiconductor device having a high-breakdown-voltage N-channel lateral MOS transistor having a completely dielectric isolation and a drift region having an appropriate thickness, capable of forming an etched LOCOS oxide film, more simply and at lower cost. Can be.

In the above embodiment, the N-channel lateral MOS
Although the example of manufacturing a semiconductor device having a transistor has been described, the present invention can be preferably applied to the manufacture of other N-channel and P-channel devices having a drift region in addition to a semiconductor device having a PMOS transistor.

[0046]

As described above, according to the present invention,
A semiconductor device having a high breakdown voltage MOS transistor capable of forming a complete dielectric isolation and a drift region having an appropriate thickness can be manufactured more easily and at lower cost.

[Brief description of the drawings]

FIG. 1 is a sectional view of a main process of a semiconductor device having an N-channel lateral MOS transistor according to a method of manufacturing a semiconductor device of the present invention.

FIG. 2 is a cross-sectional view showing main steps of a semiconductor device having an N-channel lateral MOS transistor according to a method of manufacturing a semiconductor device of the present invention.

FIG. 3 is a cross-sectional view showing main processes of a semiconductor device having an N-channel lateral MOS transistor according to a method of manufacturing a semiconductor device of the present invention.

FIG. 4 is a diagram showing N by a conventional semiconductor device manufacturing method;
FIG. 3 is a cross-sectional view of main processes of a semiconductor device having a MOS transistor.

FIG. 5 is a diagram showing N by a conventional semiconductor device manufacturing method;
FIG. 3 is a cross-sectional view of main processes of a semiconductor device having a MOS transistor.

[Explanation of symbols]

101, 201: support substrate; 102, 202: buried oxide film (first insulating film); 103, 203: silicon single crystal layer; 104: second insulating film (silicon oxide film);
05: third insulating film (silicon nitride film), 106: element isolation film, 107, 208: LOCOS oxide film, 108:
Gate oxide film, 109 gate electrode, 110 p channel region, 111 p ⁺ diffusion region, 112 source diffusion region, 113 drain drain region, 114 interlayer insulating film,
115 ... source, 116 ... drain, 204, 205 ...
Embedded silicon layer, 206: silicon oxide film, 207
... Silicon nitride film, A, D ... opening, B, E ... etching part on drift region, C ... drift region

Continued on the front page F-term (reference) 5F040 DA20 DB01 EC07 ED09 EH02 EK01 EK05 EM05 FB04 5F110 AA11 DD04 DD05 DD13 DD24 EE09 EE22 EE45 EE50 FF02 FF29 GG02 GG12 HJ01 HJ13 HL02 HL03 HL04 NN04 NN06

Claims (7)

[Claims] A second insulating film and a third insulating film are formed on a substrate having at least a first insulating film and a silicon layer containing an impurity of one conductivity type on the first insulating film. Sequentially stacking; selectively etching the second insulating film, the third insulating film, and part of the silicon layer to form an element isolation film; at least the third insulating film Selectively etching to form a drift region; and selectively oxidizing a portion etched for forming the element isolation film and an etched portion of the third insulating film. A method for manufacturing a semiconductor device, comprising a step of forming an oxide film. 2. The method according to claim 1, wherein the substrate having at least the first insulating film and the silicon layer containing the one-conductivity-type impurity on the first insulating film is formed using an SOI (silicon oxide).
The method for manufacturing a semiconductor device according to claim 1, wherein the substrate is an nInsulator substrate. 3. The film according to claim 1, wherein the third insulating film is a film having oxidation resistance when oxidizing the second insulating film and the silicon layer containing the one conductivity type impurity. Of manufacturing a semiconductor device. 4. The method according to claim 1, wherein the first insulating film is a silicon oxide film. 5. The method according to claim 1, wherein said second insulating film is a silicon oxide film. 6. The method according to claim 1, wherein said third insulating film is a silicon nitride film. 7. A method for manufacturing a semiconductor device having a MOS transistor, comprising: at least a first insulating film;
On the other hand, a step of sequentially stacking a silicon oxide film and a silicon nitride film on a substrate having a silicon layer containing a conductive type impurity; and isolating the silicon oxide film, the silicon nitride film and a part of the silicon layer by element isolation. Selectively etching for forming a film; selectively etching at least the third insulating film for forming a drift region; 3 and the etched portion of the insulating film at the same time, LOCOS (Local Oxidation of
Forming a silicon oxide film by oxidizing by a silicon (Silicone) method; forming a gate oxide film in an element isolation region; forming a gate electrode on the gate oxide film; Forming a source region and a drain region in the element isolation region of the silicon layer; and forming a source and a drain electrically connected to the source region and the drain region, respectively. A method for manufacturing a semiconductor device having a MOS transistor.