JP2839088B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates is related to <br/> in semiconductor equipment, and more particularly to a semiconductor device having an insulating isolation structure.

[0002]

2. Description of the Related Art Among conventional techniques for monolithically integrating a high-voltage large-current power element having a current path from the front surface to the back surface of a semiconductor substrate and a control circuit element, a technique for forming a power element formation region by epitaxial growth is known. ,
For example, IEEE 1987 CICC (CUSTOM INTEGRA
As proposed in TED CIRCUITS CONFERENCE, pp. 443-446, there is a type using a bonded substrate.

[0003] Hereinafter, such a conventional insulating and separating structure will be described.
The description will be made based on the cross-sectional views in the order of steps shown in FIGS. First, as shown in FIG. 15, a high-concentration impurity layer (N ⁺
Monocrystalline silicon substrate (N-type) 100 having
And a second single-crystal silicon substrate (N ⁺ type) having an impurity concentration higher than that of the first single-crystal silicon substrate 100
An oxide film is formed on one surface of the substrate 101, respectively. Next, FIG.
As shown in FIG. 6, the surfaces on which the oxide films are formed are directly joined by a bonding technique.

Subsequently, as shown in FIG. 17, the first single-crystal silicon substrate 100 is etched until it reaches the second single-crystal silicon substrate 101 from the surface beyond the bonding surface. Next, as shown in FIG. 18, a single crystal silicon epitaxial layer (N
(Mold) 102 is grown on the etched surface. Thereafter, as shown in FIG. 19, lapping and surface polishing are performed to flatten the substrate, and then, as shown in FIG. 20, a trench groove reaching the oxide film bordering the bonding surface is formed by anisotropic reactive etching. The inner wall of the trench is thermally oxidized by ion etching (RIE) to form a thermal oxide film 103.
After the formation, dielectric isolation is performed by filling the inside of the trench with polycrystalline silicon 104.

In the semiconductor substrate thus formed, a region A formed by the N ⁺ type silicon substrate 101 and the epitaxial layer 102 and a region B surrounded by the thermal oxide film 103 and the polysilicon 104 are thermally oxidized. Membrane 103
Then, the two substrates 100 and 101 are electrically separated from each other by the oxide film. In this area A, a power element such as a power MOS transistor, which has the back surface of the N ⁺ type silicon substrate 101 as one electrode, is formed. In a area B, a circuit element for controlling the operation of the power element is provided. For example, a bipolar transistor or a CMOS element is formed, and a so-called intelligent power device can be constituted as a whole.

[0006]

In this prior art, in order to separate a control circuit element formation area B and a power element formation area A, a power element formation area A is formed by an epitaxial method, and then a trench groove, The thermal oxide film 103 and the polycrystalline silicon 104 are formed (step shown in FIG. 20). This not only complicates the manufacturing process, but also requires high-precision alignment when forming the trench groove so that the trench groove always encounters the internal oxide film partially present inside the substrate.

The present invention has been made in view of the above problems, and a main object of the present invention is to provide an insulating device for monolithically integrating a power device having a current path from the front surface to the back surface of a substrate and a control circuit device. to provide a semiconductor equipment which can easily manufacture a semiconductor substrate having a separation structure.

[0008]

A feature of the present invention is that a single crystal silicon substrate, a first insulating film provided on a first region on one main surface of the single crystal silicon substrate, A first single-crystal silicon layer provided over the insulating film, a second insulating film covering a side surface of the first single-crystal silicon layer, and a first insulating film provided on a side surface of the second insulating film. The first polycrystalline silicon layer is provided on the second region of one main surface of the single crystal silicon substrate in contact with the side surface of the first polycrystalline silicon layer, and is electrically insulated from the first single crystal silicon layer. And a second single-crystal silicon layer separated.

In the above structure, the first single-crystal silicon layer further includes a plurality of isolation trenches, the inside of which is filled with a polycrystalline silicon layer, and a third insulating film is provided on a side wall. A plurality of island-shaped regions electrically isolated from each other in the first single-crystal silicon layer. In the above structure, a circuit element can be arranged in the first single-crystal silicon layer,
On the other hand, a vertical power element can be formed in the second single crystal silicon layer which is electrically connected to the single crystal silicon substrate.

It is preferable that the first insulating film has an oxide film in contact with the lower surface of the first single crystal silicon layer and a nitride film disposed below the oxide film. An oxide film commonly used as an insulating film generates a tensile stress. This tensile stress acts on the first single-crystal silicon layer which is a circuit element formation region, and gives a strain inside the first single-crystal silicon layer, causing a crystal defect. This problem becomes more remarkable as the thickness of the first single crystal silicon layer decreases. The tensile stress of the oxide film can be reduced by the compressive stress of the nitride film by disposing the nitride film below the oxide film. Note that the nitride film is prevented from directly contacting the first single crystal silicon layer which is a circuit element formation region by disposing an oxide film between the nitride film and the first single crystal silicon layer.
Therefore, the generation of crystal defects in the element formation region due to the compressive stress of the nitride film is prevented, and the electrical characteristics of the control circuit element can be stabilized.

[0011]

[0012]

[0013]

[0014]

[0015]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view showing a semiconductor device according to a first embodiment of the present invention. In FIG. 1, S
An N ^- epitaxial layer 26 of a single crystal semiconductor is formed on the surface of i substrate 25, and a drain electrode 44 is formed on the back surface of Si substrate 25. N ^- at a predetermined portion on the epitaxial layer 26 of single crystal semiconductor N ^- epitaxial layer 33 is formed, SiO ₂ film 27 in addition to the predetermined portion
Are formed. The power MOS transistor 43 is formed in the N ⁻ epitaxial layer 33.

Also, poly-S is formed on the SiO ₂ film 27.
An i film 24 is formed, and a predetermined portion on the film is
A poly-Si layer 34 is formed, and an Si ₃ N ₄ film 23 is formed on a portion other than the predetermined portion. This Si ₃ N
_An SiO ₂ film 22 is formed on the _four films 23, and an N ⁺ epitaxial layer 21 and an N ⁻ -type Si substrate 20 as element forming layers are sequentially stacked on the SiO ₂ film 22.

Here, the conductive poly-Si film is made of each S
Since the side and bottom surfaces of the OI region (island region) are covered, by applying a potential to this poly-Si film via the Al electrode 38, the poly-Si film can function as an electric shield layer. Therefore, according to the above-described configuration, each SOI region has the oxide film 30, the SiO ₂ film 2
2 and the poly-Si film acts as an electric shield layer, so that, for example, a vertical power M
Even if the drain displacement of the Si substrate 25 greatly fluctuates due to the operation of the OS transistor, it is not affected,
Each SOI region can be electrically stabilized.

Bonding of Si substrate 20 and Si substrate 25
In the vicinity of the part, SiO_TwoFilms 22, 27 and Si_ThreeN_FourMembrane 23
Are formed. This SiO_TwoFilms 22, 27 and Si
_ThreeN _FourThe film 23 relieves stress generated inside the SOI layer.
Has the function of_TwoThe films 22, 27 are made of SOI
Exerts tensile stress on the_ThreeN_FourThe film 23 is an SOI layer
To compressive stress. As a result, an SOI layer is formed.
The region can be in a state where the stress is relaxed.

In addition, Si_ThreeN_FourThe lower layer of the film 23 is pol
y-Si film 24, even if Si _ThreeN_FourCompression of membrane 23
Crystal defects occur in the poly-Si film 24 due to the stress
Even so, the poly-Si film 24 is merely an electric shield.
There is no problem because only the potential is fixed as a layer.
No. Next, the manufacturing procedure of the semiconductor device shown in FIG.
This will be described with reference to FIGS. 2A and 2B and FIGS.
You. 3 to 10 show semiconductors shown in the order of the manufacturing process.
It is sectional drawing of an apparatus.

(Basic Forming Step) First, an N ⁺ epitaxial layer 21 is formed on an N ⁻ type Si substrate 20 having a (100) plane orientation and an electric resistivity of 3 to 10 Ω · cm by epitaxial growth. It is formed with a film thickness. In addition,
Instead of using epitaxial growth, impurities such as As and Sb may be diffused.

Subsequently, a SiO ₂ film having a thickness of 0.2 to ₂ μm is formed by thermal oxidation at 900 to 1100 ° C. or CVD.
A film 22 is formed on the N ⁺ epitaxial layer 21, and is further formed by LPCVD to a thickness of 0.1 to 0.3 μm.
The ₃ N ₄ film 23 is deposited on the SiO ₂ film 22. Next, L
A poly-Si film 24 containing impurities such as As and Phos at a high concentration by a PCVD method to a thickness of 1 to 10 [mu] m.
The poly-S is deposited on the i ₃ N ₄ film 23, and then the poly-S
The surface of the i-film 24 is mirror-polished by chemical polishing until the surface smoothness becomes 30 ° or less (preferably 10 ° or less).

After passing through the manufacturing means described above, FIG.
The sectional view shown in FIG. In the first embodiment, the poly-Si film 24 doped with As, Phos, or the like is used. However, when the poly-Si film is thin, an undoped poly-Si film is deposited, and thereafter, ,
Poly-Si by diffusion or ion implantation, etc.
A film 24 may be formed.

On the other hand, aside from the above-described Si substrate 20, a Si substrate 25 as described below is formed. That is,
High concentration N ⁺ type Si substrate 25 having (100) plane orientation
An N ^- epitaxial layer 26 is formed with a predetermined thickness by epitaxial growth. Then 900 ~ 11
Heat treatment at 00 ° C. to form a SiO 2 layer having a thickness of 0.2 to 2 μm.
₂ film 27 is formed on N ⁻ epitaxial layer 26. Then, after the above-described manufacturing procedure, a sectional view shown in FIG.

(Lamination Step) Next, FIG.
Surface of poly-Si film 24 of Si substrate 20 and diagram
SiO of the Si substrate 25 shown in FIG._TwoOn the surface of the membrane 27
And a hydrogen peroxide solution (H _TwoO_Two) And sulfuric acid (H_TwoSO
_FourPerform hydrophilic treatment with the mixed solution of
After combining, N at 1000 to 1100 ° C_Two1 to 2 in
Between the wafers.

Subsequently, the Si substrate 20 is mirror-polished to a predetermined thickness. At this time, for example, a substrate (SOI region described later)
If a bipolar transistor is to be formed thereon, the Si substrate 20 is mirror-polished to a thickness of about 3 to 10 μm, and if a MOS transistor is to be formed, the Si substrate 20 is mirror-polished to a thickness of 5 μm or less. Grind.

After the above-described manufacturing procedure, a sectional view as shown in FIG. 3 is obtained, and a so-called SOI layer is formed. (Trench portion forming step) Next, a resist having a predetermined pattern is applied on the Si substrate 20, and the Si substrate 20, N ^{+ in a} region where the resist is not applied by dry etching or the like.
When the epitaxial layer 21 and the SiO ₂ film 22 are removed, a trench portion 28 is formed, and a sectional view shown in FIG. 4 is obtained.

(Power Element Region Forming Step) Next, as shown in FIG. 5, a resist is applied to the region other than the region 29 where the power MOS transistor is to be formed, and the Si ₃ N in the power element forming region 29 is etched by etching or the like. ₄ membrane 23 and p
The poly-Si film 24 is removed. (Thermal Oxidation Process) Next, thermal oxidation is performed at 900 to 1100 ° C. to form an oxide film (SiO ₂ film) having a thickness of 0.1 to 1 μm.
Form 30. Then, a sectional view shown in FIG. 6 is obtained.

Here, an oxide film is formed on the end face of the poly-Si film 24 facing the power element formation region 29 by this thermal oxidation treatment. (Silicon Nitride Removal Step) Next, as shown in the cross-sectional view of FIG. 7, a resist film 31 is applied to the formation region 29 of the power MOS transistor, and is etched below the trench 28 by plasma etching or hot phosphoric acid. The existing Si ₃ N ₄ film 23 is removed.

(Silicon Oxide Removal Step) Next, as shown in the sectional view of FIG. 8, after removing the resist film 31, another portion for removing the SiO ₂ film remaining in the formation region 29 of the power MOS transistor is removed. Is coated with a resist film 32,
The SiO ₂ film 27 in the formation region 29 of the power MOS transistor is removed by etching or the like, and the underlying N ⁻ epitaxial layer 26 is exposed.

The underlying N ^- epitaxial layer 26 may be removed to a desired thickness. (Embedding Step) Next, after removing the resist film 32 of the wafer through the above-described silicon oxide removing step, the wafer is put into an epitaxial growth apparatus to perform epitaxial growth.

Since the underlying region of the power MOS transistor formation region 29 is a single crystal, when epitaxial growth is performed, an N ⁻ epitaxial layer 33 of single crystal Si is formed on the surface of the N ⁻ epitaxial layer 26. . On the other hand, in portions other than the power element formation region 29, p
Since the growth is performed based on the poly-Si film 24,
In order to cover the O ₂ film 27 and the oxide film 30, pol
The y-Si layer 34 is formed, and the inside of the trench portion 28 is buried.

After the above-described manufacturing procedure, a sectional view shown in FIG. 9 is obtained. In the first embodiment, since the resistance of the poly-Si layer 34 buried in the trench portion 28 is relatively high, the impurity is diffused or ion-implanted after the following planarization step. It is recommended to introduce a low resistance. (Planarization Step) Next, as shown in FIG. 10, the poly-Si layer 34 and the single-crystal Si N ^- epitaxial layer 33 deposited on the oxide film 30 are planarized by selective polishing. Thus, the poly-Si layer 34 remains only in the trench portion 28.

(Element Forming Step) Next, a P-type diffusion layer 37, an N ⁺ -type diffusion layer 36 and an A ⁺ type diffusion layer 36 are formed in the formation region 35 shown in FIG.
The bipolar transistor 39 is formed by disposing the 1 electrode 38. The power element formation region 29 shown in FIG.
By using known semiconductor processing technology,
A power MOS transistor 43 is formed by disposing a gate electrode 42, a P-type diffusion layer 41, an N ⁺ -type diffusion layer 40, and an Al electrode 38, and further forming a drain electrode 44 on the back surface of the Si substrate 25.

Note that, other than the above-described bipolar transistor, a semiconductor element such as a CMOS transistor may be formed, or a combination thereof. Through the above-described manufacturing steps, the semiconductor device according to the first embodiment as shown in the cross-sectional view of FIG. 1 is manufactured. Next, a description will be given of a manufacturing method capable of further reducing the stress generated inside the SOI layer.

FIGS. 11 to 13 are cross-sectional views of the semiconductor device shown in the order of the manufacturing steps, showing the SOI layer portion (region 35). This manufacturing method is performed after the above-described thermal oxidation treatment step. (Silicon Nitride Deposition Step) Here, a Si ₃ N ₄ layer 45 is deposited by LPCVD on a semiconductor device as shown in the sectional view of FIG. Then, a sectional view shown in FIG. 11 is obtained.

(Etching Step) Next, anisotropic RIE
(Reactive ion etching; Reactive
e Ion Etching), the Si ₃ N ₄ layer 45 deposited on the oxide film 30 by the above process and the Si ₃ N ₄ film 23 present under the trench portion 28 are removed.
Then, the Si ₃ N deposited on the side surface of the trench portion 28
_{The four} layers are not removed, resulting in the cross section shown in FIG.
Note that this etching step corresponds to the above-described silicon nitride removing step.

Thereafter, through the above-described steps shown in FIGS.
A poly-Si layer 34 is deposited. Then, a sectional view shown in FIG. 13 is obtained. After that, after the planarization step and the element formation step, the sectional view shown in FIG. 14 is obtained. In the element forming step, the bipolar transistor 46 and the MOS transistor 47 are formed. Therefore, through the above-described manufacturing process, stress is also alleviated to the oxide film (SiO ₂ film) formed on the side surface of the trench portion, so that the semiconductor device is further formed in consideration of the stress alleviation. be able to.

However, without using the above-described manufacturing method,
Through the manufacturing process of the first embodiment, the stress
It is clear that the mitigation is sufficient. Because half
Conductive devices generally tend to be thinner and more integrated.
Therefore, the film thickness of the element formation region is small. Therefore
SiO_TwoOf the portions where the film is formed, poly-S
SiO formed around i-layer_TwoSi than film area_Three
N _FourSiO formed on the film_TwoThe area of the membrane is much larger
Therefore, as shown in the first embodiment, SiO 2_Twofilm
Below the element formation region where_Three
N_FourIf a film is formed, stress can be sufficiently relaxed.
It is.

As described above in detail, in the embodiment of the present invention, the element isolation between the power element formation region and the control circuit element formation region is performed before forming the single crystal silicon epitaxial layer as the power element formation region. The feature is that the groove formed in the above is used as one configuration of the element isolation region. That is, before forming an epitaxial layer on the side wall of the groove, an insulating film is formed, and the element between the power element forming region and the control circuit element forming region is formed by the insulating film and the insulating film bordering the bonding surface. Due to the separation,
It has the effect of being easy to manufacture. Also, when an island-shaped region for forming an individual element is formed in the control circuit element formation region, the effect that manufacturing can be performed in the same number of steps occurs, and the individual element is formed. The trench (trench 28) for insulating and isolating the island-shaped regions from each other is also filled with polycrystalline silicon by the epitaxial method for forming a single-crystal silicon epitaxial layer as a power element formation region. This has the effect that it can be performed simultaneously with the formation of the single crystal silicon epitaxial layer.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a semiconductor device according to a first embodiment of the present invention.

FIGS. 2A and 2B are cross-sectional views of a semiconductor device in a substrate forming step according to the first embodiment.

FIG. 3 is a sectional view of the semiconductor device in a bonding step according to the first embodiment;

FIG. 4 is a sectional view of the semiconductor device in a trench portion forming step of the first embodiment;

FIG. 5 is a sectional view of the semiconductor device in a power element region forming step according to the first embodiment;

FIG. 6 is a sectional view of the semiconductor device in a thermal oxidation process according to the first embodiment;

FIG. 7 is a sectional view of the semiconductor device in a silicon nitride removing step of the first embodiment;

FIG. 8 is a sectional view of the semiconductor device in a silicon oxide removing step of the first embodiment.

FIG. 9 is a sectional view of the semiconductor device in an embedding step according to the first embodiment;

FIG. 10 is a sectional view of the semiconductor device in a planarization step according to the first embodiment;

FIG. 11 is an essential part cross sectional view of a semiconductor device in another manufacturing step;

FIG. 12 is an essential part cross sectional view of a semiconductor device in another manufacturing step;

FIG. 13 is an essential part cross sectional view of a semiconductor device in another manufacturing step;

FIG. 14 is an essential part cross sectional view of a semiconductor device in another manufacturing step;

FIG. 15 is a cross-sectional view of a main part of a semiconductor device in a conventional manufacturing process.

FIG. 16 is a cross-sectional view of a main part of a semiconductor device in a conventional manufacturing process.

FIG. 17 is an essential part cross sectional view of a semiconductor device in a conventional manufacturing process.

FIG. 18 is a cross-sectional view of a main part of a semiconductor device in a conventional manufacturing process.

FIG. 19 is an essential part cross sectional view of a semiconductor device in a conventional manufacturing process.

FIG. 20 is an essential part cross sectional view of a semiconductor device in a conventional manufacturing process.

[Explanation of symbols]

Reference Signs List 20 N ^- type Si substrate 25 N ⁺ -type Si substrate 27 SiO ₂ film 28 Trench portion 29 Power element formation region 30 Oxide film 33 N ^- epitaxial layer 34 Poly-Si layer 39 Bipolar transistor 43 Power MOS transistor 44 Drain electrode

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 29/78 H01L 29/78 658K

Claims (4)

(57) [Claims] 1. A single-crystal silicon substrate, a first insulating film provided on a first region of one main surface of the single-crystal silicon substrate, and a first insulating film provided on the first insulating film A single-crystal silicon layer, a second insulating film covering a side surface of the first single-crystal silicon layer, a first polycrystalline silicon layer provided in contact with the side surface of the second insulating film, A first side surface in contact with the first polycrystalline silicon layer and provided on a second region of one main surface of the single crystal silicon substrate and electrically insulated and separated from the first single crystal silicon layer; A semiconductor device comprising: two single-crystal silicon layers. 2. The semiconductor device according to claim 1, wherein the first single-crystal silicon layer has a plurality of isolation trenches, the inside of which is filled with a polycrystalline silicon layer and a third insulating film is provided on a side wall. 2. The semiconductor device according to claim 1, further comprising a plurality of island-shaped regions electrically isolated from each other in the single-crystal silicon layer. 3. A semiconductor device formed on the first single-crystal silicon layer and a vertical power device formed on the second single-crystal silicon layer electrically connected to the single-crystal silicon substrate. The semiconductor device according to claim 1, comprising: 4. The semiconductor device according to claim 1, wherein the first insulating film includes an oxide film in contact with a lower surface of the first single-crystal silicon layer and a nitride film disposed under the oxide film. Item 4. The semiconductor device according to any one of Items 3.