JPH0837312A - Soi-type semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To adjust the threshold voltage of an NMOS transistor, by making the thickness of the gate insulation film of the NMOS transistor different from that of a PMOS transistor. CONSTITUTION:After the formations of element separating regions 5, by the performing of a thermal oxidation, the oxide film to be changed into a gate insulation film 6 of a PMOS region is formed. Subsequently, after the formation of the silicon nitride film to be changed into a mask layer 7, by the performing of a patterning, only a PMOS forming region II is masked with a resist 9, etc., and the mask layer 7 of an NMOS forming region I is removed. Then, after removal of the resist 9, by the performing of a thermal oxidation, the oxide film to be changed into a gate insulation film 8 of the NMOS forming region I is formed. Thereby, the thickness of the gate insulation film 8 of the NMOS transistor can be larger than the one of the gate insulation film 6 of the PMOS transistor, and as a result, the threshold voltage of the NMOS transistor can be adjusted without its wrong effect on the threshold voltage of the PMOS transistor.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an SOI type semiconductor device and a method for manufacturing the same. In particular, the present invention relates to a method of manufacturing an SOI type semiconductor device including an NMOS transistor and a PMOS transistor, each of which is an SOI type element. In this specification, “SOI type” refers to a semiconductor device having a structure in which a semiconductor portion is generally formed in a thin film shape and exists in an isolated (island) shape on an insulating material (not necessarily limited to a silicon-based semiconductor device). It is not something that can be done).
In this specification, "MOS" generally means a transistor having a structure including a conductive material-insulating material-semiconductor,
It is not limited to metal-oxide-semiconductor.

[0002]

2. Description of the Related Art Conventionally, there is known a semiconductor device having a structure in which a semiconductor portion is formed in a thin film shape and exists in an island shape on an insulating material. For example, as this type, an SOI (Sili) in which a thin silicon layer is formed on an insulating film is used.
A con on insulator) type semiconductor device is known. Such a semiconductor device has advantages such as no latch-up, good radiation resistance, a small junction capacitance, and a high-speed circuit, as compared with a bulk semiconductor device, and also a fully depleted SOI device. In the semiconductor device, compared with the partially depleted SOI semiconductor device,
It has many advantages such as a small S value and a low substrate bias effect.

SO for forming an SOI type semiconductor device
The manufacturing method of the I substrate is such that the semiconductor substrate and another substrate are bonded to each other via at least an insulating film, and the semiconductor substrate is polished from the back surface (generally, grinding up to near the polishing end point and a final precision polishing step). A bonding method for forming an element in the SOI layer obtained by thinning the structure, or a so-called SIMOX in which oxygen is ion-implanted into a silicon substrate and heat treatment is performed to form a buried oxide film.
There are various methods such as the law. Here, a conventional example of a method for manufacturing an SOI type semiconductor device using the SIMOX method will be described with reference to FIGS.

First, as shown in FIG.
1. Implantation of oxygen ion into 1 (implantation amount is, for example, 10 ¹⁸ /
cm ² , and implantation depth is 100 nm or more). Reference numeral 22 indicates a portion into which oxygen ions are implanted (oxygen ion implantation layer).

Next, heat treatment (for example, 1270 to 1350) is performed.
Heat treatment) is performed to react the ion-implanted oxygen with silicon to form a silicon oxide film 23 that forms a buried oxide film. FIG. 11 shows a state in which a silicon oxide film is formed as the buried oxide film 23.

This method is based on SIMO that is generally used.
Similar to the X method, the buried oxide film (silicon oxide film) 23 is formed by alternately repeating ion implantation and heat treatment.
The crystallinity of the silicon layer 24 (which becomes the SOI layer) on the top can be kept good.

Next, an element isolation region 25 is formed (see FIG. 1).
2). Although the element isolation by the general LOCOS method is illustrated here, there are various element isolation methods, and for example, trench isolation or the like may be used, and the element isolation method is not limited to the LOCOS element isolation. Reference numerals I and II indicate an NMOS formation region and a PMOS formation region, respectively, which are element-isolated.

Next, a gate oxide film 26 to be a gate insulating film is formed by thermal oxidation (for example, thermal oxidation at a temperature of 850 ° C.) (FIG. 13).

Subsequently, polycrystalline silicon 30 is deposited as a gate material by CVD to a thickness of 50 to 150 nm. At this time, during the deposition process (so-called in-situ)
It is common practice to dope with phosphorus, or later by predeposition to dope with n ⁺ type. Furthermore, the wiring resistance of the gate can be reduced by depositing the silicide 31, for example, WSi (FIG. 14).

Next, the gate is patterned and anisotropically etched to form a gate electrode 32 (FIG. 15).

Further, ion implantation for forming LDD33, LD
Formation of D sidewall 34, source / drain region 3
Through processes such as ion implantation for forming 5a, 35b, 36a and 36b, a transistor having an NMOS portion I and a PMOS portion II is formed as shown in FIG.

[0012]

In the SOI type transistor manufactured by the conventional method described above, when the n ⁺ type gate is used as the NMOS transistor, the threshold voltage is almost affected by the work function. Since it becomes 0, a large amount of doping is required for the channel. However, in order to obtain a fully depleted SOI, the channel doping amount is limited, and it is very difficult to raise it to a desired threshold voltage.

In addition, further miniaturization of devices will progress in the future, and SOI
When the layer is thinned, the absolute amount of impurities in the channel portion decreases and the variation increases, so that it becomes impossible to control the threshold with the impurities in the channel portion.

Therefore, a method of controlling the threshold voltage by utilizing the work function of the gate electrode has been considered. N
P ⁺ gate MOS transistor, the method of adjusting the threshold voltage by a so-called dual gate process using n ⁺ gate PMOS transistor, the NMOS transistor using the p ⁺ gate, penetration from p ⁺ gate of boron into the channel , The problem of sucking up boron into WSi, and the problem of mutual diffusion in using n ⁺ gate and p ⁺ gate,
That is, since it is not an established process yet, it has various problems.

There is a method of increasing the gate oxide film thickness as a method of increasing the threshold voltage, but there is a problem that the threshold voltage of the PMOS transistor is also increased at the same time by simply increasing the thickness.

The present invention was devised to solve these conventional problems and solves them, and provides a technique capable of controlling the threshold voltage without causing any inconvenience. For example, fully depleted SOI
With this maintained, it is possible to adjust the threshold voltage of the NMOS transistor without affecting the threshold voltage of the PMOS transistor S.
The object is to obtain an OI semiconductor device and a manufacturing method thereof.

[0017]

According to the invention of claim 1 of the present application, an NMOS transistor and a PMOS are respectively formed of an SOI type element in which a thin semiconductor portion is formed on an insulating film.
In an SOI type semiconductor device including a transistor,
The SOI type semiconductor device is characterized in that the gate insulating films of the NMOS transistor and the PMOS transistor are formed to have different thicknesses from each other, thereby achieving the above object.

According to a second aspect of the present invention, the NMOS is provided.
2. The S according to claim 1, wherein the gate insulating film is formed thicker than the gate insulating film of the PMOS.
An OI type semiconductor device, which achieves the above object.

According to the invention of claim 3 of the present application, an oxide film to be a buried insulating film is formed by implanting oxygen ions into a semiconductor substrate, and after forming an element isolation region, a thin insulating film is formed. By masking one transistor formation part separated in the element, an insulating film is further formed on the other transistor formation part, and a gate electrode is further formed on the west part of each transistor, so that a thin semiconductor part is formed on the insulation film. An SOI type semiconductor device comprising an NMOS transistor and a PMOS transistor, each of which is formed of an SOI type element, wherein the gate oxide films of the NMOS transistor and the PMOS transistor are different in thickness from each other. A method of manufacturing a semiconductor device, which achieves the above object.

According to a fourth aspect of the present invention, the NMOS is provided.
4. The method of manufacturing an SOI semiconductor device according to claim 3, wherein the gate insulating film of the transistor is formed thicker than the gate insulating film of the PMOS transistor. To do.

[0021]

According to the present invention, there is provided an SOI element having a semiconductor portion such as a thin silicon layer formed on an insulating film, and these elements form a complementary element consisting of an NMOS transistor and a PMOS transistor. It is possible to adjust the threshold voltage by making the thickness of the gate insulating film of the NMOS transistor different from that of the PMOS transistor, and in particular, by making the gate oxide film of the NMOS transistor thicker than that of the PMOS transistor, PMO while maintaining the depletion type SOI structure
The threshold voltage of the NMOS transistor can be adjusted without affecting the threshold voltage of the S transistor.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of an SOI type semiconductor device and a method of manufacturing the same according to the present invention will be described below with reference to the embodiments shown in the drawings. However, it should be understood that the present invention is not limited to the illustrated embodiments.

Example 1 The SOI type semiconductor device of this example is as shown in FIG.
A thin film semiconductor portion 4 is formed on the insulating film 3 (here, SiO ₂ ).
An SOI type semiconductor device comprising an NMOS transistor I and a PMOS transistor II, each of which is composed of an SOI type element in which (a silicon layer in this case) is formed, the gate insulation film 8 of the NMOS transistor and the gate insulation of the PMOS transistor. The films 6 are formed with different thicknesses.

In particular, the SOI type semiconductor device of this embodiment has N
The thickness of the gate insulating film 8 of the MOS transistor I is set to PMO.
It was formed to be thicker than the gate insulating film 6 of the S transistor II.

The SOI type semiconductor device of this example was manufactured as follows. Please refer to FIG. 2 to FIG. 9 and FIG.

In this embodiment, an oxide film to be the buried insulating film 3 is formed by implanting oxygen ions into the semiconductor substrate 1 (here, the Si substrate) (FIG. 2) (FIG. 3), and the element isolation region is formed. After forming 5 (FIG. 4), a thin insulating film 6 is formed.
Then, one of the transistor formation portions II separated from each other is masked (see FIGS. 5 and 6; the silicon nitride film serving as the mask is shown by reference numeral 7). 1 is formed by forming a thick gate insulating film 8 (FIGS. 5 to 7) and further forming a gate electrode 12 in each transistor formation portion I and II (FIGS. 8 and 9). NMOS transistors I and PMO, each of which is composed of an SOI type element in which a thin semiconductor portion 4 (SOI layer) is formed on the insulating film 3 as described above.
An SOI type semiconductor device including an S-transistor II, in which the gate insulating film 8 of the NMOS transistor and the gate insulating film 6 of the PMOS transistor are made different in thickness from each other.

Here, the gate insulating film 8 of the NMOS transistor I is formed thicker than the gate insulating film 6 of the PMOS transistor II.

More specifically, the following steps were used in this example. First, as shown in FIG. 2, implantation of oxygen ions into the semiconductor substrate 1 (implantation amount is, for example, 10 ¹⁸ / cm ² ,
The implantation depth is 100 nm or more). In FIG. 2, reference numeral 2 indicates a portion into which oxygen ions are implanted (oxygen ion implantation layer).

Next, heat treatment (for example, 1270 to 135) is performed.
(0 ° C.) to react the ion-implanted oxygen with silicon to form a silicon oxide film to be the buried insulating film 3. FIG. 3 shows a state in which the buried insulating film 3 (silicon oxide film) is formed. A portion above the embedded insulating film 3 is a semiconductor portion 4 forming an SOI layer.

The above method is a commonly used SIMO.
Similar to the X method, by repeating ion implantation and heat treatment alternately, the crystallinity of the semiconductor portion 4 (silicon layer which is the SOI layer) on the embedded insulating film 3 (silicon oxide film) can be kept good. it can.

Next, the element isolation region 5 is formed (FIG. 4). Here, the element isolation by the general LOCOS method is schematically shown, but there are various methods for the element isolation means, and any method may be used. For example, trench isolation may be used, and the method is not limited to the LOCOS method.

Next, thermal oxidation of about 10 nm (for example, the temperature is 850 ° C.) is performed to form an oxide film to be the gate insulating film 6 in the PMOS region. Then, a silicon nitride film to be the mask layer 7 is deposited by the CVD method. Here, the thickness is about 10 to 30 nm. It may be thinner if it serves as a mask for the next oxidation (FIG. 5).

Next, by patterning, only the region II where the PMOS is formed is masked with the resist 9 or the like, and the mask layer 7 (silicon nitride film) in the region I where the NMOS is formed is removed by, for example, phosphoric acid (FIG. 6). .

Subsequently, after the resist 9 is removed, thermal oxidation is further performed to form an oxide film to be the gate insulating film 8 in the NMOS formation region I (FIG. 7). As a result, the gate insulating film 8 of the NMOS transistor is made thicker than the gate insulating film 6 of the PMOS transistor.

After removing the silicon nitride film by using it as the mask layer 7, polycrystalline silicon 10 which is a gate material is deposited to a thickness of 50 to 150 nm by the CVD method (FIG. 8). At this time,
At the same time during the process, the so-called in-situ is doped with phosphorus or later by pre-deposition to be doped with n ⁺ -type. Further, the silicide 11 such as WSi is deposited to reduce the wiring resistance of the gate, and the structure shown in FIG. 8 is obtained.

Thereafter, the gate is patterned and anisotropically etched to form the gate electrode 12 (FIG. 9).

Further, ion implantation for LDD 13 formation, LD
Formation of D sidewall 14, source / drain region 1
The transistor shown in FIG. 1 is formed through processes such as ion implantation for forming 5a, 15b, 16a and 16b.

As described above, in the present embodiment, the SOI element having the thin silicon layer 4 formed on the insulating film 3 is provided, and the complementary element including the NMOS transistor I and the PMOS transistor II is further provided. In a semiconductor device having various elements, a gate insulating film 8 (oxide film) in the NMOS section
By making the thickness of the gate thicker than the gate insulating film 6 (oxide film) of the PMOS portion, the threshold voltage of the NMOS can be adjusted without affecting the threshold voltage of the PMOS transistor.

As a result, both the NMOS and PMOS transistors can be kept fully depleted, so that the advantages of the fully depleted SOI are not lost. Furthermore, in the process using the existing n ⁺ gate, the off current is small,
It is possible to form a well-balanced element of NMOS and PMOS.

[0040]

According to the SOI type semiconductor device and the method of manufacturing the same of the present invention, it is possible to control a desired threshold voltage without any inconvenience. It has been made possible to adjust the threshold voltage of NMOS transistors without affecting the threshold voltage of the.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of an SOI semiconductor device according to a first embodiment.

2A to 2C are sectional views showing steps of Example 1 in order. (1)

3A to 3C are sectional views showing steps of Example 1 in order. (2)

FIG. 4 is a sectional view showing the steps of Example 1 in order. (3)

5A to 5C are cross-sectional views showing steps of Example 1 in order. (4)

6A to 6C are cross-sectional views showing the steps of Example 1 in order. (5)

7A to 7C are sectional views showing steps of Example 1 in order. (6)

FIG. 8 is a sectional view showing the steps of the first embodiment in order. (7)

FIG. 9 is a cross-sectional view showing the steps of Example 1 in order. (8)

10A to 10D are sectional views sequentially showing steps of a method for manufacturing an SOI semiconductor device according to a conventional method. (1)

FIG. 11 is a sectional view sequentially showing steps of a method for manufacturing an SOI type semiconductor device by a conventional method. (2)

FIG. 12 is a sectional view sequentially showing steps of a method for manufacturing an SOI semiconductor device according to a conventional method. (3)

13A to 13C are sectional views sequentially showing steps of a method for manufacturing an SOI semiconductor device according to a conventional method. (4)

FIG. 14 is a sectional view sequentially showing steps of a method for manufacturing an SOI semiconductor device according to a conventional method. (5)

FIG. 15 is a sectional view sequentially showing steps of a method for manufacturing an SOI semiconductor device according to a conventional method. (6)

FIG. 16 is a sectional view sequentially showing steps of a method for manufacturing an SOI semiconductor device according to a conventional method. (7)

[Explanation of symbols]

1 Semiconductor Substrate (Si Substrate) 2 Oxygen Ion Implanted Layer 3 Buried Insulation Film (Oxide Film) 4 Semiconductor Part (SOI Layer) 5 Element Isolation Area 6 Thin Gate Insulation Film (Oxide Film to Become PMOS Gate Insulation Film) 7 Mask Layer (Silicon nitride film) 8 Thick gate insulating film (oxide film to be the gate insulating film of NMOS) 9 Resist 10 Gate material (polycrystalline silicon) 11 Gate material (silicide) 12 Gate electrode

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H01L 27/092 27/08 331 E 21/336 H01L 27/08 321 C 9056-4M 29/78 617 S

Claims (4)

[Claims] 1. An SOI type semiconductor device comprising an NMOS transistor and a PMOS transistor, each of which is composed of an SOI type element in which a thin semiconductor portion is formed on an insulating film, and a gate insulating film of the NMOS transistor and the PMOS transistor is provided. An SOI type semiconductor device characterized by being formed with different thicknesses. 2. The SO according to claim 1, wherein the gate insulating film of the NMOS transistor is formed thicker than the gate insulating film of the PMOS transistor.
I-type semiconductor device. 3. A semiconductor substrate is formed with an oxide film to serve as a buried insulating film by implanting oxygen ions, and after forming an element isolation region, a thin insulating film is formed, and then one of the transistor elements is isolated. By masking the formation part and further forming an insulating film on the other transistor formation part, and further forming a gate electrode on each transistor formation part, from the SOI type element in which the thin film semiconductor part is formed on the insulation film, respectively. Comprising an NMOS transistor and a PMOS transistor, and the NMOS transistor and the PMOS transistor
An SOI type semiconductor device having a transistor and a gate oxide film having different thicknesses from each other is obtained.
Type semiconductor device manufacturing method. 4. The SO according to claim 3, wherein the gate insulating film of the NMOS transistor is formed thicker than the gate insulating film of the PMOS transistor.
I-type semiconductor device manufacturing method.