JP2002118261A - Semiconductor device and its fabricating method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and its fabricating method in which process control is facilitated and a full depletion transistor can be fabricated easily. SOLUTION: The method for fabricating a semiconductor device comprises steps for preparing an SOI substrate 1, forming a gate oxide film 6 on the surface of a single crystal Si layer, forming a dummy gate electrode on the gate oxide film, implanting impurity ions into the single crystal Si layer using the dummy gate as a mask, forming diffusion layers 16 and 17 of the source- drain region in the single crystal Si layer by annealing, depositing a silicon oxide layer 21 on the entire surface including the dummy gate and then exposing the upper surface of the dummy gate by CMP, removing the dummy gate by etching, implanting oxygen ions into the single crystal Si layer using the silicon oxide layer 21 as a mask, forming a buried oxidized insulation layer 11 at a position deeper than 10 nm in the single crystal Si layer beneath the gate electrode by heat treatment, and then forming a gate electrode 7b.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device having an SOI structure and a method for manufacturing the same. In particular, it relates to a semiconductor device capable of easily manufacturing a fully depleted SOI device and a method of manufacturing the same.

[0002]

2. Description of the Related Art FIG. 7 shows a conventional SOI (Silicon On Insu).
2 is a cross-sectional view showing a fully depleted semiconductor device having a (lator) structure. First, the SOI substrate 1 manufactured by the bonding method
Prepare 01. The SOI substrate 101 includes a support substrate 102 made of single crystal silicon, an insulating film 103 formed on the support substrate 102, and a single crystal Si layer 104 formed on the insulating film 103. I have.

That is, a first silicon substrate (support substrate 102) having a first insulating film formed on its surface is prepared, and a second silicon substrate (single-crystal Si) having a second insulating film formed on its surface is prepared.
Prepare layer 104). Next, the first insulating film and the second insulating film are bonded to each other to form an insulating film 103 including the first and second insulating films formed on the support substrate 102 and a second insulating film 103 formed on the insulating film 103. An SOI substrate 101 including two silicon substrates (single-crystal Si layer 104) is formed. Thereafter, the thickness of the second silicon substrate is reduced to about 10 nm by polishing the back surface of the second silicon substrate.
As a result, the S including the single-crystal Si layer 104 having a small thickness is
An OI substrate 101 is formed.

Next, a trench is formed in the single-crystal Si layer 104, and a silicon oxide film is buried in the trench. Thus, an element isolation film 105 made of a silicon oxide film is formed in an element isolation region on the insulating film 103. next,
P-type impurities are ion-implanted into the single crystal Si layer 104.

Thereafter, a gate oxide film 106 is formed on the surface of the single crystal Si layer 104 by a thermal oxidation method. Next, a polysilicon film is deposited on the entire surface including the gate oxide film 106, and the polysilicon film is patterned to form a gate electrode 107 on the gate oxide film.

Next, low concentration N-type impurity ions are implanted using the gate electrode 107 as a mask. Thereafter, a CVD (Chemical Vapor) is formed on the entire surface including the gate electrode 107.
By depositing a silicon oxide film by a Deposition method and etching the entire surface of the silicon oxide film, a sidewall 113 made of a silicon oxide film is formed on the side wall of the gate electrode 107.

Next, N-type impurity ions are implanted using the side wall 113 and the gate electrode 107 as a mask. Thereafter, the SOI substrate 101 is annealed to form a low-concentration N-type diffusion layer 115 and N-type diffusion layers 116 and 117 of source / drain regions in the single-crystal Si layer. Thus, the SOI structure fully depleted M
An OS transistor is formed. Fully depleted MOS transistors have various features such as being able to sufficiently suppress the short channel effect.

After that, the oxide film on the N-type diffusion layers 116 and 117 in the source / drain regions is removed, and the gate electrode 10 is removed.
7. A metal layer (not shown) is deposited on the entire surface including 7. Next, by subjecting the SOI substrate to a heat treatment, the single-crystal Si
By causing a silicide reaction between the layer and the gate electrode and the metal layer, a silicide layer (not shown) is formed on each of the N-type diffusion layers 116 and 117 and the gate electrode.

Next, an interlayer insulating film (not shown) is deposited on the entire surface including the gate electrode, and the interlayer insulating film is etched to form an N type diffusion layer 116,
A contact hole (not shown) located on each of the 117 is formed.

[0010]

In the above-mentioned conventional method for manufacturing a semiconductor device, the thickness of the single-crystal Si layer 104 is made extremely small in order to form a fully depleted MOS transistor. For this reason, if the silicide reaction on the diffusion layer in the source / drain region proceeds excessively, the single-crystal Si
All of the diffusion layers 116 and 117 in the layer 104 may be silicided. If the amount of over-etching in the etching for forming the contact hole is too large, the contact hole becomes
In some cases, the insulating film 103 may be penetrated through the layer 104. As described above, it is difficult to control the process of a fully depleted MOS transistor in which a single-crystal Si layer is formed thin. Therefore, it is difficult to manufacture a fully depleted SOI device.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to provide a semiconductor device and a method of manufacturing the same, which can easily manufacture a fully depleted transistor by easily controlling a process. It is in.

[0012]

In order to solve the above-mentioned problems, a method of manufacturing a semiconductor device according to the present invention comprises a supporting substrate,
A step of preparing an SOI substrate having a first insulating film formed thereon and a single crystal Si layer formed thereon, a step of forming a gate insulating film on the surface of the single crystal Si layer, A step of forming a dummy gate electrode on the film, a step of implanting impurity ions into the single-crystal Si layer using the dummy gate electrode as a mask, and annealing the single-crystal Si layer to form a source / source on the single-crystal Si layer. Forming a diffusion layer in the drain region; depositing a second insulating film on the entire surface including the dummy gate electrode;
A step of exposing the upper surface of the dummy gate electrode by polishing or etching back, a step of removing the dummy gate electrode by etching using the second insulating film as a mask, and a step of adding oxygen to the single crystal Si layer using the second insulating film as a mask. Implanting ions and performing a heat treatment to form a buried oxide insulating layer at a position deeper than a predetermined depth of the single crystal Si layer below the gate electrode, and a step of forming a gate electrode on the gate insulating film , Is provided.

According to the method of manufacturing a semiconductor device, the buried oxide insulating layer is formed at a position deeper than the predetermined depth of the single crystal Si layer below the gate electrode, so that the thickness of the single crystal Si layer can be relatively reduced. Even if it is formed thick, a fully depleted MOS transistor can be easily formed. Further, since it is not necessary to reduce the thickness of the single-crystal Si layer as in a conventional semiconductor device, process control is facilitated.

A semiconductor device according to the present invention comprises an SOI substrate having a support substrate, an insulating film formed thereon and a single-crystal Si layer formed thereon, and a gate formed on the surface of the single-crystal Si layer. An insulating film, a gate electrode formed on the gate insulating film, a source / drain region diffusion layer formed on the single-crystal Si layer below the side wall of the gate electrode, and a single A buried oxide insulating layer formed in the crystalline Si layer and formed at a position deeper than a predetermined depth of the single crystal Si layer. Note that the predetermined depth is preferably 10 nm or less.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. 1 to 6 are sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

First, the SO manufactured by the laminating method is used.
An I substrate 1 is prepared. The SOI substrate 1 includes a supporting substrate 2 made of single-crystal silicon, an insulating film 3 formed on the supporting substrate 2, and a single crystal S formed on the insulating film 3.
and an i-layer 4.

That is, a first silicon substrate (support substrate 2) having a first insulating film formed on the surface is prepared, and a second silicon substrate is formed on the surface.
A second silicon substrate (single-crystal Si layer 4) on which an insulating film has been formed is prepared. Next, the first insulating film and the second insulating film are bonded to each other to form an insulating film 3 made of the first and second insulating films formed on the support substrate 2 and a second insulating film formed on the insulating film 3. An SOI substrate 1 including two silicon substrates (single-crystal Si layer 4) is formed. Then, the thickness of the second silicon substrate is reduced to, for example, about 150 nm by polishing the back surface of the second silicon substrate.

Next, as shown in FIG.
A trench is formed on the entire surface including the inside of the trench.
A silicon oxide film is deposited by the VD method. Thereafter, the silicon oxide film existing on the single crystal Si layer 4 is removed by etch back or CMP (Chemical Mechanical Polishing) polishing. As a result, a silicon oxide film is buried in the trench, and an element isolation film 5 made of a silicon oxide film is formed in an element isolation region on the insulating film 3. next,
P-type impurities are ion-implanted into the single crystal Si layer 4.

Thereafter, a gate oxide film 6 is formed on the surface of the single crystal Si layer 4 by a thermal oxidation method. Next, a polysilicon film is deposited on the entire surface including the gate oxide film 6 by a CVD method, and the polysilicon film is patterned to form a dummy gate electrode 7a on the gate oxide film.

Then, low concentration N-type impurity ions are implanted using the dummy gate electrode 7a as a mask. next,
A silicon oxide film is deposited on the entire surface including the dummy gate electrode 7a by the CVD method, and the entire surface of the silicon oxide film is etched to form a sidewall 13 made of the silicon oxide film on the side wall of the dummy gate electrode 7a. .

Thereafter, N-type impurity ions are implanted using the sidewall 13 and the dummy gate electrode 7a as a mask, and the single crystal Si layer 4 is annealed. Thus, the low-concentration N-type diffusion layer 15 and the N-type diffusion layers 16 and 17 in the source / drain regions are formed in the single-crystal Si layer.

Next, the oxide film on the N-type diffusion layers 16 and 17 in the source / drain regions is removed, and the dummy gate electrode 7a is removed.
A metal layer (not shown) such as a Ti layer is deposited on the entire surface including the above. Next, heat treatment is performed on the SOI substrate to cause a silicide reaction between the single-crystal Si layer and the dummy gate electrode and the metal layer, thereby forming the N-type diffusion layers 16 and 1.
On each of the dummy gate electrode 7 and the dummy gate electrode 7a, a silicide layer (not shown) is formed.

Next, as shown in FIG. 2, a silicon oxide film 2 is formed on the entire surface including the dummy gate electrode 7a by the CVD method.
1 is thickly deposited, and the silicon oxide film 21 is polished by CMP or etched back to form a dummy gate electrode 7.
The upper surface of a is exposed.

Thereafter, as shown in FIG.
The electrode 7a is removed by etching. Next, Silico
Using the oxide film 21 and the side walls 13 as a mask
By implanting elemental ions 9, the gate
Deeper than the depth of 10 nm in the single crystal Si layer 4 under the pole 7b
The oxygen injection layer 8 is formed at a position where no oxygen is injected. Oxygen ion at this time
Although the ion implantation conditions of No. 9 are not particularly limited,
For example, dose amount 5 × 10 ¹⁷~ 1 × 10¹⁸cm^-2Using
Is preferred.

Next, as shown in FIG. 4, by subjecting the SOI substrate 1 to a heat treatment, a portion corresponding to the oxygen injection layer 8 in the single crystal Si layer 4 is changed to a buried oxide insulating layer 11. The heat treatment conditions at this time are not particularly limited,
For example, it is preferable to use the condition of 1050 ° C to 1350 ° C. As described above, the buried oxide insulating layer 11 is made of a single crystal S
By forming the single-crystal Si layer 4 below the gate electrode 7b, the thickness of the single-crystal Si layer 4 can be reduced to about 10 nm by forming the i-layer 4.

Then, after forming a gate oxide film on the surface of the single crystal Si layer, a polysilicon film 22 is deposited on the entire surface including the silicon oxide film 21 by the CVD method.

Next, as shown in FIG. 5, the polysilicon film 22 is subjected to CMP polishing or etch back to form a gate electrode 7b made of a polysilicon film between the sidewalls 13. Thus, a fully depleted MOS transistor having an SOI structure is formed. That is, the depth 1 in the single crystal Si layer 4 under the gate electrode 7b
By forming the buried oxide insulating layer 11 at a position deeper than 0 nm, the single-crystal Si layer
nm, and as a result, the SOI
A fully depleted MOS transistor having a structure can be formed. In addition, the fully-depleted MOS transistor has various features such as being able to sufficiently suppress the short channel effect.
Next, an interlayer insulating film 23 made of a silicon oxide film or the like is deposited on the entire surface including the gate electrode 7b.

Next, as shown in FIG.
And by etching the silicon oxide film 21,
Contact holes 23a and 23b are formed on the N-type diffusion layers 16 and 17 in the source / drain regions, respectively. Thereafter, a wiring layer 25 is formed in the contact hole and on the interlayer insulating film.

According to the above embodiment, single-crystal Si layer 4
Is relatively thick, about 150 nm, but by forming the buried oxide insulating layer 11 as described above, the single crystal Si layer in the channel portion below the gate electrode 7b can be thinned. A fully depleted MOS transistor can be formed. In this transistor, it is not necessary to reduce the thickness of the single-crystal Si layer unlike a conventional semiconductor device, so that process control is facilitated. That is,
Since the thickness of the single-crystal Si layer is relatively large, even if the silicide reaction on the diffusion layer in the source / drain region progresses excessively, the diffusion layers 16 and 17 in the single-crystal Si layer 4 may be formed.
Is not silicided. Further, even if the amount of over-etching in the etching for forming the contact holes 23a and 23b is too large, the contact hole does not penetrate the single-crystal Si layer 4 and reach the insulating film 3. Therefore, process control is easy, and a fully depleted transistor can be easily manufactured.

The present invention is not limited to the above-described embodiment, but can be implemented with various modifications. For example,
Specific conditions for implanting the oxygen ions 9 can be variously selected and performed depending on conditions such as the thickness of the single-crystal Si layer 4.

[0031]

As described above, according to the present invention, a buried oxide insulating layer is formed at a position deeper than a predetermined depth of a single crystal Si layer below a gate electrode. Therefore, it is possible to provide a semiconductor device and a method of manufacturing the semiconductor device, in which process control is easy and a fully depleted transistor can be easily manufactured.

[Brief description of the drawings]

FIG. 1 is a sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the embodiment of the present invention, showing a step subsequent to FIG. 1;

FIG. 3 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the embodiment of the present invention, showing a step subsequent to FIG. 2;

FIG. 4 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the embodiment of the present invention, which shows the step subsequent to FIG. 3;

FIG. 5 is a cross-sectional view illustrating the method of manufacturing the semiconductor device according to the embodiment of the present invention, which shows the step subsequent to FIG. 4;

FIG. 6 is a cross-sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention, which illustrates the next step of FIG. 5;

FIG. 7 is a cross-sectional view showing a conventional fully depleted semiconductor device having an SOI structure.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1,101 SOI substrate 2,102 Support substrate 3,103 Insulating film 4,104 Single-crystal Si layer 5,105 Element isolation film 6,106 Gate oxide film 7a Dummy gate electrode 7b, 107 Gate electrode 8 Oxygen injection layer 9 Oxygen ion REFERENCE SIGNS LIST 11 buried oxide insulating layer 13, 113 sidewall 15, 115 low-concentration N-type diffusion layer 16, 116 source diffusion layer 17, 117 drain diffusion layer 21 silicon oxide film 22 polysilicon film 23 interlayer insulating film 23 a, 23 b contact hole 25 Wiring layer

Claims (3)

[Claims] An SOI having a support substrate, a first insulating film formed thereon, and a single-crystal Si layer formed thereon
A step of preparing a substrate; a step of forming a gate insulating film on the surface of the single-crystal Si layer; a step of forming a dummy gate electrode on the gate insulating film; By implanting impurity ions and annealing the single crystal Si layer, the single crystal Si
Forming a source / drain region diffusion layer in the layer; depositing a second insulating film on the entire surface including the dummy gate electrode;
A step of exposing the upper surface of the dummy gate electrode by CMP polishing or etching back the second insulating film, a step of removing the dummy gate electrode by etching using the second insulating film as a mask, and a step of using the second insulating film as a mask Forming a buried oxide insulating layer at a position deeper than a predetermined depth of the single-crystal Si layer below the gate electrode by implanting oxygen ions into the single-crystal Si layer and performing a heat treatment; and forming a gate on the gate insulating film. A method for manufacturing a semiconductor device, comprising: forming an electrode. 2. An SOI substrate having a supporting substrate, an insulating film formed thereon and a single-crystal Si layer formed thereon, a gate insulating film formed on the surface of the single-crystal Si layer, A gate electrode formed on the insulating film; a source / drain region diffusion layer formed below the side wall of the gate electrode formed on the single crystal Si layer; and a single crystal Si layer formed below the gate electrode. , The single crystal Si
A buried oxide insulating layer formed at a position deeper than a predetermined depth of the layer. 3. The semiconductor device according to claim 1, wherein said predetermined depth is 10 nm or less.