JP2005064194A - Semiconductor substrate having soi structure, manufacturing method thereof and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor substrate having an SOI structure capable of stably mounting devices of different characteristics such as a high-speed application element or a high breakdown voltage application element, to provide its manufacturing method and a semiconductor device. <P>SOLUTION: A semiconductor substrate 10 having the SOI structure has a first region A and a second region B as a region used in a substantial device formation. Both of the first region A and the second region B are on an identical flattening plane. In the first region A, a first insulating layer 111 and a second insulating layer 112 are doubly provided, and a silicon monocrystalline layer 122 on the second insulating layer 112 is used for the substantial device formation. In the second region B, the second insulating layer 112 is selectively removed, and the silicon monocrystalline layer (including 121, 123) on the first insulating layer 111 is used for the substantial device formation. A thickness of each silicon monocrystalline layer on the first insulating layer 111 and the second insulating layer 112 is decided in accordance with characteristics of a formed element. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an SOI (Silicon On Insulator) substrate, a semiconductor substrate having an SOI structure in which devices having different Si layer thicknesses are mounted, a manufacturing method thereof, and a semiconductor device.

  The SOI (Silicon On Insulator) technique is known as a technique for forming an integrated circuit device such as a MOSFET on a silicon single crystal formed on a buried insulating film. The SOI structure MOS device has an advantage that the junction capacitance between the source and the drain can be suppressed as compared with the bulk technology. For this reason, it operates at a higher speed than a MOSFET (bulk MOSFET) fabricated on a normal bulk silicon substrate. In addition, since it operates at a high speed even with a low voltage power supply, its application to a low power consumption LSI is being studied.

In an SOI transistor integrated circuit, in consideration of low power consumption performance, high-speed operation performance, and stability during operation, a high-speed application element and a high breakdown voltage application element may be mixedly mounted on the same substrate. At that time, a relatively thick Si layer is required in the high breakdown voltage device region in order to provide a drift layer and reduce the on-resistance. Therefore, a high-speed application element uses a fully depleted transistor in which the channel region of the transistor is completely depleted, and a high-voltage application element is a transistor in which the depletion layer in the transistor channel region does not reach the buried insulating film, for example, a partially depleted transistor To use. Conventionally, a technique related to a hybrid device of such FD type (fully depleted type) and other types such as PD type (partially depleted type) is known, and is described in, for example, [Patent Document 1].
JP-A-9-260679 (page 6-8, FIGS. 1 and 2)

  The thickness of the SOI layer greatly affects the device characteristics. Conventionally, it has been difficult to control the thickness of a uniform Si layer for each target device. Further, because of the step between different devices adjacent to each other on the same SOI substrate, it is difficult to control the gate dimension, and there is a concern that the subsequent wiring process may be adversely affected.

  The present invention has been made in view of the above circumstances, and a semiconductor substrate having an SOI structure capable of more stably mounting devices having different characteristics, such as a high-speed application element and a high-voltage application element, and its manufacture A method and a semiconductor device are to be provided.

  A semiconductor substrate having an SOI structure according to the present invention relates to a semiconductor substrate having an SOI structure in which a silicon single crystal layer for device formation is provided on an insulating layer, and the insulating layer is a first layer between the silicon single crystal layers. A region including a double layer with the insulating layer and the second insulating layer is included.

  A semiconductor substrate having an SOI structure as a more preferred embodiment according to the present invention relates to a semiconductor substrate having an SOI structure in which a silicon single crystal layer for device formation is provided on an insulating layer, and the insulating layer is the silicon single crystal layer Between the first insulating layer and the second insulating layer, the silicon single crystal layer on the second insulating layer is used for substantial device formation, and the first region A second region in which the silicon single crystal layer on the first insulating layer is used for substantial device formation, and the first region and the second region are selectively removed. They are on the same flat surface.

According to each of the semiconductor substrates having the SOI structure according to the present invention, the silicon single crystal layer on the first insulating layer is used for device formation, or the silicon single crystal layer on the second insulating layer is used for device formation. Or can be selected as needed. In addition, the first region and the second region are on the same flat surface, and the control of the gate dimension across the first region and the second region and the multilayer wiring structure can be easily configured with reliability.
The semiconductor substrate having an SOI structure according to the present invention preferably includes an element isolation insulating film that reaches the second insulating layer at least at the boundary between the first region and the second region.

  A method for manufacturing a semiconductor substrate having an SOI structure according to the present invention includes a step of forming a first stack of at least a first insulating layer and a first silicon single crystal layer, and at least a second insulating layer and a second silicon. A step of forming a second stack of single crystal layers, the first stack and the second stack are bonded together, and the first insulating layer, the second insulating layer and the insulating layer are doubled on a supporting substrate. And a step of forming an SOI structure having the same.

  According to the method for manufacturing a semiconductor substrate having an SOI structure according to the present invention, an SOI structure having a double insulating layer is easily formed by bonding the first stack and the second stack. Whether the silicon single crystal layer on the first insulating layer is used for device formation or the silicon single crystal layer on the second insulating layer is used for device formation can be selected as necessary.

  Therefore, more preferably, in the method of manufacturing a semiconductor substrate having an SOI structure according to the present invention, the first silicon single crystal layer of the first stack by selectively removing a partial region of the second stack. And exposing the first silicon single crystal layer to epitaxial growth and forming a third silicon single crystal layer to a thickness equal to or greater than at least the same planarized surface as the second silicon single crystal layer And a step of making the silicon single crystal layer including the first silicon single crystal layer and the third silicon single crystal layer the same planarized surface.

  More preferably, in the method for manufacturing a semiconductor substrate having an SOI structure according to the present invention, the first silicon single crystal layer of the first stack by selectively removing a partial region of the second stack. And exposing the first silicon single crystal layer to an epitaxial growth to form a third silicon single crystal layer to a thickness equal to or greater than at least the same planarized surface as the second silicon single crystal layer A step of making the silicon single crystal layer including the first silicon single crystal layer and the third silicon single crystal layer the same flat surface, and a step of making the silicon single crystal layer the same flat surface And a step of forming an element isolation region before or after.

  The method for manufacturing a semiconductor substrate having an SOI structure according to the present invention includes a step of preparing a first silicon single crystal substrate and a second silicon single crystal substrate, and a step of forming a first silicon single crystal substrate on the first silicon single crystal substrate. A heat treatment step for forming one insulating layer, a heat treatment step for forming a second insulating layer on the second silicon single crystal substrate, a support substrate, and the support substrate and the first silicon single crystal substrate. Bonding the first insulating layer side to the first insulating layer side, thinning and flattening the first silicon single crystal substrate to form a first silicon single crystal layer, A second bonding step of bonding the main surface of the silicon single crystal layer and the second insulating layer side of the second silicon single crystal substrate; and thinning and flattening the second silicon single crystal substrate; 2 silicon single connection Characterized by comprising a step of forming a layer, the.

  As a more preferred embodiment, a method of manufacturing a semiconductor substrate having an SOI structure according to the present invention includes a step of preparing a first silicon single crystal substrate and a second silicon single crystal substrate, and the first silicon A heat treatment step of forming a first insulating layer on the single crystal substrate; a heat treatment step of forming a second insulating layer on the second silicon single crystal substrate; and a support substrate, and the support substrate and the first A first bonding step for bonding the first silicon single crystal substrate to the first insulating layer side, and a step of thinning and flattening the first silicon single crystal substrate to form a first silicon single crystal layer A second bonding step of bonding the main surface of the first silicon single crystal layer and the second insulating layer side of the second silicon single crystal substrate; and thinning the second silicon single crystal substrate into a thin film Change A step of forming a second silicon single crystal layer and selectively removing a part of the stack composed of the second silicon single crystal layer and the second insulating layer to form the first silicon single crystal layer. A step of exposing a crystal layer; and a third silicon single crystal layer that is epitaxially grown from the exposed first silicon single crystal layer and has a thickness equal to or greater than at least the same planarized surface as the second silicon single crystal layer And a step of making the silicon single crystal layer including the first silicon single crystal layer and the third silicon single crystal layer the same planarized surface.

According to the method for manufacturing a semiconductor substrate having an SOI structure according to the present invention, an insulating layer is formed on each silicon single crystal substrate, and the insulating layer is easily formed by the first bonding step and the second bonding step. A heavy SOI structure can be formed. Whether the silicon single crystal layer on the first insulating layer is used for device formation or the silicon single crystal layer on the second insulating layer is used for device formation can be selected as necessary. The process of making the silicon single crystal layer on which the device is formed the same planarized surface contributes to the stable gate size control, wiring process, and achievement of the wiring structure.
The method for manufacturing a semiconductor substrate having an SOI structure according to the present invention further comprises the step of forming an element isolation region before or after the step of making the silicon single crystal layer the same planarized surface. To do.

  A semiconductor device according to the present invention is a semiconductor device configured on a semiconductor substrate having an SOI structure in which a silicon single crystal layer for device formation is provided on an insulating layer, and the insulating layer is formed of the silicon single crystal layer. A first region between the first insulating layer and the second insulating layer, the silicon single crystal layer on the second insulating layer being used for substantial device formation, and the second insulating layer A part of the layer is removed and the silicon single crystal layer on the first insulating layer on the same flat surface as the silicon single crystal layer on the second insulating layer adjacent to the second insulating layer substantially forms a device. A second region used, a first transistor element formed in the first region, and a second transistor element formed in the second region are provided.

According to the semiconductor device of the present invention, the first transistor element and the second transistor element are configured on the same planarized surface and have different thicknesses on the first insulating layer or the second insulating layer, respectively. A silicon single crystal layer is used.
The semiconductor device according to the present invention preferably has the following characteristics that can be easily realized when configuring elements having different characteristics.
The first transistor element includes a fully depleted MOS transistor.
The second transistor element includes a partially depleted MOS transistor.
The second transistor element includes a MOS transistor having a higher breakdown voltage than the first transistor element.

BEST MODE FOR CARRYING OUT THE INVENTION

  FIG. 1 is a main part configuration diagram of a semiconductor substrate having an SOI structure according to the first embodiment of the present invention. The semiconductor substrate 10 having an SOI structure includes a region where the insulating layer 11 is doubled with the first insulating layer 111 and the second insulating layer 112 between the silicon single crystal layers 12. In such a structure, the stacked layer 101 of the first insulating layer 111 and the silicon single crystal layer 121 and the stacked layer 102 of the second insulating layer 112 and the silicon single crystal layer 122 are separately formed, and are sequentially applied to the supporting substrate 100. Manufactured together.

  FIG. 2 is a main part configuration diagram of a semiconductor substrate having an SOI structure according to the second embodiment of the present invention. A configuration is shown in which the first embodiment is further developed to make it easier to form a substantial device. The same parts as those in FIG. 1 are described with the same reference numerals. As regions used for substantial device formation, a first region A and a second region B are provided. Both the first region A and the second region B are on the same flat surface. The first region A is doubled with the first insulating layer 111 and the second insulating layer 112, and the silicon single crystal layer 122 on the second insulating layer 112 is used for substantial device formation. In the second region B, the second insulating layer 112 is selectively removed, and the silicon single crystal layer (including 121 and 123) on the first insulating layer 111 is used for substantial device formation. The thickness of each silicon single crystal layer on the first insulating layer 111 and the second insulating layer 112 is determined according to the characteristics of the element to be formed.

  Such a configuration of the second region B is formed as follows, for example. From the structure of FIG. 1, the silicon single crystal layer 122 and the second insulating layer 112 in a predetermined region are selectively removed through a photolithography process. The silicon single crystal layer 121 on the first insulating layer 111 exposed thereby is epitaxially grown, and the silicon single crystal layer 123 is formed to a thickness of at least the same planarized surface as the silicon single crystal layer 122. Flattening using a mechanical polishing technique.

  According to the first and second embodiments, respectively, is the silicon single crystal layer on the first insulating layer 111 used for device formation or the silicon single crystal layer on the second insulating layer 112 is used for device formation? , Can be selected as needed. Further, the first region A and the second region B are on the same flat surface, and even if there is a gate wiring or a multilayer wiring structure straddling the first region A and the second region B, it can be easily configured with reliability. .

3 to 9 are cross-sectional views showing the main part of the method of manufacturing a semiconductor substrate having an SOI structure according to the third embodiment of the present invention in the order of steps. Here, as an example, the ELTRAN manufacturing method is used as the manufacturing method of the bonding SOI. Further, the same parts as those in the first and second embodiments will be described with the same reference numerals.
As shown in FIGS. 3A and 3B, silicon single crystal substrates 311 and 312 serving as a basis for realizing the SOI structure are prepared, and porous silicon layers 321 and 322 are formed, respectively. On top of that, silicon single crystal layers 121 and 122 of a predetermined conductivity type, for example, low-concentration P type (P ⁻ type), are epitaxially grown for device formation. The thickness of each silicon single crystal layer 121, 122 is determined according to the element to be formed. Thereafter, thermal oxidation is performed to further form insulating layers (oxide films) 111 and 112.

  On the other hand, as shown in FIG. 4, a support substrate (silicon substrate) 100 of a predetermined conductivity type, for example, P type, is prepared. The support substrate 100 and the insulating layer 111 side of the silicon single crystal substrate 311 are bonded together. The bonding is accompanied by a heat treatment to bond the substrates to each other (first bonding step). Thereafter, the silicon single crystal substrate 311 is separated. For example, a separation technique by spraying a water jet onto the end face of the porous silicon layer 321 by an ELTRAN manufacturing method is used. Thereafter, the porous silicon layer 321 left on the silicon single crystal layer 121 is selectively removed, and the surface of the silicon single crystal layer 121 is planarized by a hydrogen annealing process.

  Next, as shown in FIG. 5, the silicon single crystal layer 121 and the insulating layer 112 side of the silicon single crystal substrate 312 are bonded together. The bonding is accompanied by a heat treatment to bond the substrates to each other (second bonding step). Thereafter, the silicon single crystal substrate 312 is separated in the same manner as described above (by ELTRAN manufacturing method). The porous silicon layer 322 left on the silicon single crystal layer 122 side is selectively removed, and the surface of the silicon single crystal layer 122 is planarized by a hydrogen annealing process. The configuration of FIG. 1 is realized in the form of FIG.

Further, as shown in FIG. 6, using a photolithography process, the first region A is masked with, for example, a stack of titanium nitride film 41 / silicon nitride film 42, and the silicon single crystal layer 122 and the second region B in the second region B are masked. The insulating layer 112 is selectively removed.
Next, as shown in FIG. 7, after removing the silicon nitride film 42, epitaxial growth is performed from the silicon single crystal layer 121 on the exposed first insulating layer 111, and at least the same planarized surface as the silicon single crystal layer 122 is formed. The silicon single crystal layer 123 is formed to the above thickness.
Next, as shown in FIG. 8, planarization is performed using a CMP (Chemical Mechanical Polishing) technique. After the detection of the titanium nitride film 41 during polishing, the polishing is continued for a predetermined time, and the titanium nitride film 41 is completely removed. Through the cleaning process and the hydrogen annealing process, the surface of the silicon single crystal layer (122, 123) is planarized. The configuration of FIG. 2 is realized in the form of FIG.

Next, as shown in FIG. 9, an element isolation insulating film 43 is formed by a trench element isolation method. The element isolation insulating film 43 reaches at least the second insulating layer 112 between the first region A and the second region B. Needless to say, as shown in the isolation region 45, part of the insulating layer 111 may be formed. Such a configuration of the element isolation insulating film 43 depends on an etching mask (not shown) of the silicon single crystal layer. It is also conceivable that the element isolation insulating film 43 is formed before the silicon single crystal layer planarization step by CMP.
In this way, it is possible to provide a substrate having an SOI structure in which the first element region A, the second region B, and the element isolation insulating film 43 having different silicon single crystal layer thicknesses are provided.

  According to the method of the above embodiment, the silicon single crystal layers 121 and 122 and the insulating layers 111 and 112 are formed on the silicon single crystal substrates 311 and 312, respectively, and can be easily performed by the first bonding process and the second bonding process. An SOI structure having double insulating layers can be formed. Whether the silicon single crystal layer 121 on the insulating layer 111 is used for device formation or the silicon single crystal layer 122 on the insulating layer 112 is used for device formation can be selected as necessary. The process of making the silicon single crystal layer (121, 122, 123) on which the device is formed the same planarized surface contributes to the stable gate dimension control, the wiring process, and the achievement of the wiring structure.

  In the substrate bonding technique, there is another manufacturing method called smart cut. In the case of smart cut, for example, the porous silicon layers (321, 322) on the silicon single crystal substrate in FIG. 3 (a) are not necessary, and after bonding, the silicon bond has a predetermined depth in FIG. 4 and FIG. Hydrogen is introduced at a predetermined energy and concentration so as to be cut off in this region. Thereby, each silicon single crystal substrate can also be separated by performing a heat treatment with the boundary between each silicon single crystal substrate (311, 312) and the silicon single crystal layer (121, 122) being fragile. There is also a method of completely polishing and removing each silicon single crystal substrate (311, 312) without undergoing such a separation process.

  FIG. 10 is a cross-sectional view showing the main configuration of a semiconductor device having an SOI structure according to the fourth embodiment of the present invention. The same parts as those shown in any of the first to third embodiments will be described with the same reference numerals. A MOS type element is formed on the substrate having the SOI structure shown in FIG. Here, in the first region A, a fully depleted (FD) N-channel MOSFET 501 is formed. In the second region B, a partially depleted (PD) N-channel MOSFET 502 is formed.

In the N-channel MOSFET 501, a gate insulating film 511 and a gate electrode 521 are formed on a P ⁻ type substrate of a silicon single crystal layer 122 controlled to a thickness of 100 nm or less, preferably about 10 to 50 nm. A side wall (spacer) 541 provided after the extension region (N ⁻ region 531) having a concentration lower than that of the source / drain region is formed on the side of the gate electrode 521. In the N ⁺ region 551 of the source / drain region, a predetermined contact wiring is taken at a portion not shown.

In the N-channel MOSFET 502, a gate insulating film 512 and a gate electrode 522 are formed on a P ⁻ type substrate of a silicon single crystal layer 123 (including 121) controlled to a thickness of 100 nm or more, preferably about 100 to 200 nm. . A side wall (spacer) 542 provided after the extension region (N ⁻ region 532) having a concentration lower than that of the source / drain region is formed on the side portion of the gate electrode 522. In the N ⁺ region 552 of the source / drain region, a predetermined contact wiring is taken at a portion not shown.

  FIG. 11 is a cross-sectional view showing a main configuration of a semiconductor device having an SOI structure according to the fifth embodiment of the present invention. The same parts as those shown in any of the first to third embodiments will be described with the same reference numerals. A MOS type element is formed on the substrate having the SOI structure shown in FIG. Here, in the first region A, a fully depleted (FD) N-channel MOSFET 501 is formed. In the second region B, a partially depleted (PD) high breakdown voltage type N-channel MOSFET 602 is formed.

The N-channel MOSFET 501 has the same configuration as that of the first region A shown in FIG.
The N-channel MOSFET 602 includes a high-voltage-resistant gate insulating film 612 and a gate electrode 622 on a P ⁻ type substrate of a silicon single crystal layer 123 (including 122) controlled to a thickness of 200 nm or more, preferably about 500 to 5000 nm. Is formed. A side wall (spacer) 642 provided after formation of the N ⁻ region 632 having a lower concentration than the source / drain region is formed on the side portion of the gate electrode 622. The N ⁻ region 632 is formed with a depth reaching the insulating layer 111. An N ⁺ region 652 of a source / drain region is formed in the N ⁻ region 632. In the N ⁺ region 652, a predetermined contact wiring is taken at a portion not shown.

  According to the fourth and fifth embodiments, the respective MOSFETs 501 and 502 (or 602) are configured on the same planarized surface, and the silicon single crystal layers having different thicknesses on the insulating layer 112 or the insulating layer 111, respectively. 122 and 121 (including 123) are used. Elements with different characteristics such as pressure resistance and high speed can be formed as necessary. In addition, since a large step does not occur, it contributes to stable gate size control, a wiring process, and a wiring structure.

  As described above, according to the present invention, an SOI structure having double insulating layers can be easily formed by using a bonding process or the like. Accordingly, it is possible to select whether the silicon single crystal layer on the first insulating layer is used for device formation or the silicon single crystal layer on the second insulating layer is used for device formation as necessary. Elements having different characteristics can be formed on substrates of silicon single crystal layers having different thicknesses. Moreover, the silicon single crystal layer bases having different thicknesses are formed on the same flat surface. This contributes to the stable gate dimension control, the wiring process, and the achievement of the wiring structure. As a result, it is possible to provide a semiconductor substrate having an SOI structure, a method for manufacturing the same, and a semiconductor device that can more stably incorporate devices having different characteristics such as a high-speed application element and a high breakdown voltage application element.

The principal part block diagram of the semiconductor substrate which has SOI structure of 1st Embodiment. The principal part block diagram of the semiconductor substrate which has SOI structure of 2nd Embodiment. The 1st sectional view showing the important section of the manufacturing method of the semiconductor substrate which has SOI structure concerning a 3rd embodiment in order of a process. FIG. 4 is a second cross-sectional view following FIG. 3. FIG. 5 is a third sectional view following FIG. 4. FIG. 6 is a fourth cross-sectional view following FIG. 5. FIG. 7 is a fifth cross-sectional view following FIG. 6. FIG. 8 is a sixth cross-sectional view following FIG. 7. FIG. 9 is a seventh cross-sectional view following FIG. 8. Sectional drawing which shows the principal part of the semiconductor device which concerns on 4th Embodiment. Sectional drawing which shows the principal part of the semiconductor device which concerns on 5th Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Semiconductor substrate which has SOI structure, 100 ... Support substrate, 101, 102 ... Lamination | stacking, 11, 111, 112 ... Insulating layer, 12, 121, 122, 123 ... Silicon single crystal layer, 311, 312 ... Silicon single crystal substrate 321, 322... Porous silicon layer 41. Titanium nitride film 42. Silicon nitride film 43. Element isolation insulating film 45. Isolation region 501 502 502 MOSFET MOSFET 511 512 612 gate insulation Membrane, 521, 522, 622 ... gate electrode, 531, 532, 632 ... N ^- region, 541, 542, 642 ... sidewall (spacer), 551, 552, 652 ... N ⁺ region.

Claims (10)

A semiconductor substrate having an SOI structure in which a silicon single crystal layer for device formation is provided on an insulating layer,
A semiconductor substrate having an SOI structure, wherein the insulating layer includes a region formed between the silicon single crystal layer and the first insulating layer and the second insulating layer. A semiconductor substrate having an SOI structure in which a silicon single crystal layer for device formation is provided on an insulating layer,
The insulating layer is provided between the silicon single crystal layer and the first insulating layer and the second insulating layer, and the silicon single crystal layer on the second insulating layer substantially forms a device. A first region to be used;
A second region in which the second insulating layer is selectively removed and the silicon single crystal layer on the first insulating layer is used for substantial device formation;
Comprising
A semiconductor substrate having an SOI structure, wherein the first region and the second region are on the same planarized surface. Forming a first stack of at least a first insulating layer and a first silicon single crystal layer;
Forming a second stack of at least a second insulating layer and a second silicon single crystal layer;
Bonding the first stack and the second stack to form an SOI structure having a double layer of the first insulating layer and the second insulating layer on the supporting substrate;
A method of manufacturing a semiconductor substrate having an SOI structure. Selectively removing a partial region of the second stack to expose the first silicon single crystal layer of the first stack;
Epitaxially growing from the exposed first silicon single crystal layer and forming a third silicon single crystal layer to a thickness equal to or greater than at least the same planarized surface as the second silicon single crystal layer;
Making the silicon single crystal layer including the first silicon single crystal layer and the third silicon single crystal layer the same flat surface;
The method of manufacturing a semiconductor substrate having an SOI structure according to claim 3, further comprising: Preparing a first silicon single crystal substrate and a second silicon single crystal substrate;
A heat treatment step of forming a first insulating layer on the first silicon single crystal substrate and a heat treatment step of forming a second insulating layer on the second silicon single crystal substrate;
A first bonding step of preparing a support substrate and bonding the support substrate and the first insulating layer side of the first silicon single crystal substrate;
Thinning and planarizing the first silicon single crystal substrate to form a first silicon single crystal layer;
A second bonding step of bonding the main surface of the first silicon single crystal layer and the second insulating layer side of the second silicon single crystal substrate;
Thinning and flattening the second silicon single crystal substrate to form a second silicon single crystal layer;
A method of manufacturing a semiconductor substrate having an SOI structure. Preparing a first silicon single crystal substrate and a second silicon single crystal substrate;
A heat treatment step of forming a first insulating layer on the first silicon single crystal substrate and a heat treatment step of forming a second insulating layer on the second silicon single crystal substrate;
A first bonding step of preparing a support substrate and bonding the support substrate and the first insulating layer side of the first silicon single crystal substrate;
Thinning and planarizing the first silicon single crystal substrate to form a first silicon single crystal layer;
A second bonding step of bonding the main surface of the first silicon single crystal layer and the second insulating layer side of the second silicon single crystal substrate;
Thinning and flattening the second silicon single crystal substrate to form a second silicon single crystal layer;
Selectively removing a part of the stack composed of the second silicon single crystal layer and the second insulating layer to expose the first silicon single crystal layer;
Epitaxially growing from the exposed first silicon single crystal layer and forming a third silicon single crystal layer to a thickness equal to or greater than at least the same planarized surface as the second silicon single crystal layer;
Making the silicon single crystal layer including the first silicon single crystal layer and the third silicon single crystal layer the same flat surface;
A method of manufacturing a semiconductor substrate having an SOI structure, further comprising: A semiconductor device configured on a semiconductor substrate having an SOI structure in which a silicon single crystal layer for device formation is provided on an insulating layer,
The insulating layer is provided between the silicon single crystal layer and the first insulating layer and the second insulating layer, and the silicon single crystal layer on the second insulating layer is used for substantial device formation. A first region;
A part of the second insulating layer is removed and the silicon single crystal layer on the first insulating layer is substantially flush with the silicon single crystal layer on the adjacent second insulating layer. A second region used for typical device formation;
A first transistor element formed in the first region;
A second transistor element formed in the second region;
A semiconductor device comprising: 8. The semiconductor device according to claim 7, wherein the first transistor element includes a fully depleted MOS transistor. 9. The semiconductor device according to claim 7, wherein the second transistor element includes a partially depleted MOS transistor. 9. The semiconductor device according to claim 7, wherein the second transistor element includes a MOS transistor having a higher breakdown voltage than the first transistor element.

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