JP2007299977A - Process for fabricating semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a process for fabricating a semiconductor device in which a back gate electrode can be formed under a field effect transistor arranged on an insulator while enhancing controllability of threshold. <P>SOLUTION: A trench 31 is formed through a second semiconductor layer 12 and a first semiconductor layer 11 to expose a semiconductor substrate 1, and a support 41 for supporting the second semiconductor layer 12 is formed in the trench 31. A trench 35 is formed for exposing the first semiconductor layer 11 from under the second semiconductor layer 12 supported by the support 41. A cavity 37 is formed between the semiconductor substrate 1 and the second semiconductor layer 12 by etching the first semiconductor layer 11 through the trench 35. An insulating film 43 is then formed on the upper and lower surfaces in the cavity 37. Thereafter, functional liquid 39 is introduced into the cavity 37 and the cavity 37 is filled with a metal layer or a semiconductor layer formed of the functional liquid 39. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a technique capable of forming a back gate electrode under a field effect transistor disposed on an insulator while improving threshold controllability.

Field effect transistors formed on an SOI substrate are attracting attention because of their ease of element isolation, latch-up freeness, and low source / drain junction capacitance. In particular, since a fully depleted SOI transistor can operate at low power consumption and at high speed and can be easily driven at a low voltage, research for operating the SOI transistor in a fully depleted mode has been actively conducted. Here, as an SOI substrate, for example, as disclosed in Patent Documents 1 and 2, SIMOX (Separation by Implanted Oxyge)
n) A substrate or a bonded substrate is used.

In Patent Document 3 and Non-Patent Document 1, an SOI layer is formed on a bulk substrate, so that S
A method capable of forming an OI transistor at a low cost is disclosed. This method is called the SBSI method, and a Si / SiGe layer is formed on a Si substrate, and only the SiGe layer is selectively removed using the difference in selectivity between Si and SiGe. A cavity is formed between the Si layer. Then, by performing thermal oxidation of Si exposed in the cavity, an SiO 2 layer is embedded between the Si substrate and the Si layer, and a BOX layer is formed between the Si substrate and the Si layer.
JP 2002-299951 A Japanese Patent Application Laid-Open No. 2000-124092 JP 2005-354024 A T.A. Sakai et al. “Separation by Bonding Si Islands (SBSI) for LSI Applications”, Second International SiGe Technology and Device Meeting, Meeting Abstract, pp. 230-231, May (2004)

By the way, in order to manufacture a SIMOX substrate, it is necessary to ion-implant high concentration oxygen into a silicon wafer. In order to manufacture a bonded substrate, it is necessary to bond two silicon wafers. For this reason, the SOI transistor has a problem that the cost is increased as compared with a field effect transistor formed in a bulk semiconductor. Also,
In ion implantation and bonding, there is a large variation in the thickness of the SOI layer, and there is a problem that, when the SOI layer is thinned to produce a fully depleted SOI transistor, the variation in characteristics of the field effect transistor increases. .

On the other hand, in the methods disclosed in Patent Document 3 and Non-Patent Document 1 (that is, SBSI method), SIM
Although problems with the OX substrate and the bonded substrate can be solved, there is a problem that it is difficult to provide the SOI transistor with a back gate structure or a double gate structure. Further, in the conventional semiconductor integrated circuit, when the channel length is shortened with the miniaturization of the transistor, the rise characteristic of the drain current in the subthreshold region is deteriorated. For this reason,
In addition to hindering the low-voltage operation of the transistor, there is a problem that leakage current at the time of off increases and power consumption at the time of operation and standby increases, and it also causes a thermal breakdown of the transistor.

Furthermore, when the SOI layer in the channel region is thinned in order to obtain a steep subthreshold, variations in transistor characteristics increase. Further, when the impurity concentration of the SOI layer channel region is increased for threshold adjustment, there is a problem that carrier mobility is deteriorated and the on-state current of the transistor is reduced.
Therefore, the present invention has been made in view of such circumstances, and it is possible to form a back gate electrode under a field-effect transistor disposed on an insulator while improving threshold controllability. An object of the present invention is to provide a method for manufacturing a possible semiconductor device.

[Invention 1 and 2] In order to achieve the above object, a manufacturing method of a semiconductor device of Invention 1 includes a step of forming a first semiconductor layer on a semiconductor substrate, and a second semiconductor layer on the first semiconductor layer. Forming a first groove that penetrates the second semiconductor layer and the first semiconductor layer to expose the semiconductor substrate; and a support that supports the second semiconductor layer as the first groove. Forming a second groove exposing the first semiconductor layer from under the second semiconductor layer supported by the support, and forming the first semiconductor more than the second semiconductor layer. Forming a cavity between the semiconductor substrate and the second semiconductor layer by etching the first semiconductor layer through the second groove under a specific etching condition in which the layer is more easily etched. And the top and bottom in the cavity A step of forming an insulating film on each surface, and a step of introducing a functional liquid into the cavity where the insulating film is formed and filling the cavity with a metal layer or a semiconductor layer formed from the functional liquid. , Including.

A method for manufacturing a semiconductor device according to a second aspect of the present invention is the method for manufacturing a semiconductor device according to the first aspect, wherein, in the step of filling the cavity with the metal layer or the semiconductor layer, the functional liquid is formed in the cavity where the insulating film is formed. The metal layer or the semiconductor layer is formed by performing a heat treatment on the functional liquid introduced into the cavity and evaporating a solvent component contained in the functional liquid. Is.

According to the method for manufacturing a semiconductor device of the first and second aspects, an SOI transistor can be formed without using an SOI substrate. For this reason, while suppressing complication of the manufacturing process, S
The potential of the active region of the OI transistor can be controlled by the back gate electrode, and the rising characteristics of the drain current in the subthreshold region can be improved. In addition, an increase in parasitic capacitance of the source / drain layer can be suppressed. As a result,
It is possible to increase the on-state current of the transistor while suppressing an increase in cost.
The speed of the I transistor can be increased. In addition, it is possible to reduce the leakage current at the time of OFF while enabling the low voltage operation, and it is possible to reduce the power consumption at the time of operation and standby.

Furthermore, in this invention, the metal layer or semiconductor layer which can be used as a back gate electrode (or double gate electrode) is formed by introduce | transducing a functional liquid in a cavity part. With such a configuration, for example, a CVD method (Chemical Vapor Depo)
compared to the case where a metal layer or a semiconductor layer is formed in the cavity using an ALD method or an atomic layer deposition (ALD) method, it is easy to make the film-forming material reach deeper in the cavity. The inside of the part can be filled with a metal layer or a semiconductor layer without a gap.

[Invention 3] The method for manufacturing a semiconductor device according to Invention 3 is the method for manufacturing a semiconductor device according to Invention 1 or 2, wherein the surface of the insulating film in the cavity is formed before introducing the functional liquid into the cavity. And a step of making it lyophilic.
With such a configuration, the functional liquid is attracted to the surface of the insulating film that has been subjected to the lyophilic process, so that the functional liquid can be more easily introduced into the cavity.

[Invention 4] The method for manufacturing a semiconductor device according to Invention 4 is the method for manufacturing a semiconductor device according to any one of Inventions 1 to 3, wherein the functional liquid is introduced onto the semiconductor substrate before introducing the functional liquid into the cavity. And a step of making the surface of the uppermost layer laminated to be lyophobic.
With such a configuration, the functional liquid moves from the surface of the uppermost layer subjected to the lyophobic treatment to the surface of the insulating film subjected to the lyophilic treatment, so that the functional liquid can be further introduced into the cavity. It becomes easy.

[Invention 5] The method of manufacturing a semiconductor device of Invention 5 is the method of manufacturing a semiconductor device according to any one of Inventions 1 to 4, wherein the functional liquid is any one of the following a) to c), or a ) To c)
A liquid consisting of any combination of
a) a liquid in which metal particles or semiconductor particles are dispersed in a solvent,
b) MOD (Metal Organic Decomposition) solution,
c) Liquid higher order silane solution, a mixed solution of a silicon compound selected from cyclopentasilane and silylcyclopentasilane and an inert organic medium,
It is characterized by using.

If it is such a structure, the liquid which consists of any one of said a) -c) or arbitrary combinations of a) -c) can reach | attain in the deep part in a cavity part, or a metal layer or It can be a semiconductor layer.

Embodiments of the present invention will be described below with reference to the drawings.
FIGS. 1A to 14A are plan views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, and FIGS. 1B to 14B are FIGS. FIG. 14A shows A1-A1 ′ to A1.
Sectional views when cut along line 4-A14 ′, FIGS. 1C to 14C are shown in FIG.
It is sectional drawing when cut | disconnecting a)-FIG. 14 (a) by the B1-B1'-B14-B14 'line | wire, respectively. FIG. 15 is a cross-sectional view illustrating a configuration example of a semiconductor device.

As shown in FIGS. 1A to 1C, first, a single crystal first semiconductor layer 11 and a single crystal second semiconductor layer 12 are sequentially stacked on a single crystal semiconductor substrate 1. These first semiconductor layers 1
The first and second semiconductor layers 12 are formed by, for example, an epitaxial growth method. First semiconductor layer 11
Uses a material having an etching rate (that is, an etching rate) larger than that of the semiconductor substrate 1 and the second semiconductor layer 12. Here, the etching rate is an etching amount per unit time when the cavity 37 shown in FIGS. 6A to 6C is formed.

1A to 1C, a semiconductor substrate 1, a first semiconductor layer 11, and a second semiconductor layer 12 are used.
Examples of the material include Si, Ge, SiGe, SiC, SiSn, PbS, and GaAs.
A combination selected from InP, GaP, GaN, ZnSe, or the like can be used. For example, the material of the semiconductor substrate 1 is Si, and the material of the first semiconductor layer 11 is Si.
Ge is used, and the material of the second semiconductor layer 12 is Si. The film thicknesses of the first semiconductor layer 11 and the second semiconductor layer 12 are, for example, about 1 to 200 nm.

Next, as shown in FIGS. 1A to 1C, a base oxide film 21 is formed on the surface of the second semiconductor layer 12 by thermal oxidation of the second semiconductor layer 12. Then, an antioxidant film 23 is formed on the entire surface of the base oxide film 21 by a method such as CVD. The antioxidant film 23 is, for example, a silicon nitride film. When the antioxidant film 23 is a silicon nitride film, it can function as a stopper layer for a planarization process by CMP (Chemical Mechanical Polishing) in addition to the function of preventing the second semiconductor layer 12 from being oxidized.

Next, as shown in FIGS. 2A to 2C, the anti-oxidation film 23, the base oxide film 21, the second semiconductor layer 12, and the first semiconductor layer 11 are used by using a photolithography technique and an etching technique.
Then, a groove 31 exposing the surface of the semiconductor substrate 1 is formed. In the etching step for forming the groove 31, the etching may be stopped on the surface of the semiconductor substrate 1, or the semiconductor substrate 1 may be over-etched to form a recess in the semiconductor substrate 1. Further, the arrangement position of the groove 31 corresponds to a part of the element isolation region in the second semiconductor layer 12.

Next, as shown in FIGS. 3A to 3C, a recess 33 is formed in the inner wall of the groove 31 by etching a part of the first semiconductor layer 11 through the groove 31. When the semiconductor substrate 1 and the second semiconductor layer 12 are Si and the first semiconductor layer 11 is SiGe, for example, hydrofluoric acid (a mixed solution of hydrofluoric acid, nitric acid, and water) is used as the etchant for the first semiconductor layer 11. . Thereby, it is possible to cut the first semiconductor layer 11 while suppressing overetching of the semiconductor substrate 1 and the second semiconductor layer 12.

Next, as shown in FIGS. 4A to 4C, a support body 41 embedded in the groove 31 is formed so as to cover the entire surface of the substrate by a method such as CVD. Here, the support body 41 has a groove 3.
1 is also formed on the side walls of the first semiconductor layer 11 and the second semiconductor layer 12, and the recess 33 facing the inner wall of the groove 31 is buried. That is, the second semiconductor layer 12 is supported by the support 41.
It is supported so as to be sandwiched not only from the side but also from the top and bottom. Thereby, the support body 41 can support the second semiconductor layer 12 on the semiconductor substrate 1 when the first semiconductor layer 11 is removed.
Note that the support body 41 formed so as to cover the entire substrate suppresses the bending of the second semiconductor layer 12 and supports the second semiconductor layer 12 while maintaining flatness. As a material of the support body 41,
For example, an insulator such as a silicon oxide film is used.

Next, as shown in FIGS. 5A to 5C, the support 41, the antioxidant film 23, the base oxide film 21, the second semiconductor layer 12, and the first semiconductor layer using photolithography technology and etching technology. By patterning 11, a groove 35 exposing the surface of the semiconductor substrate 1 is formed. In the etching process for forming the groove 35, the etching may be stopped on the surface of the semiconductor substrate 1, or the semiconductor substrate 1 may be over-etched to form a recess in the semiconductor substrate 1. Further, the position of the groove 35 corresponds to a part of the element isolation region in the second semiconductor layer 12 and the direction thereof is, for example, a direction substantially orthogonal to the formation direction of the previously formed groove 31 in plan view.

Next, as shown in FIGS. 6A to 6C, the first semiconductor layer 11 is removed by etching by bringing an etching gas or an etchant into contact with the first semiconductor layer 11 through the groove 35. A cavity 37 is formed between the substrate 1 and the second semiconductor layer 12.
Here, since the support body 41 is provided in the groove 31, the second semiconductor layer 12 can be supported on the semiconductor substrate 1 even when the first semiconductor layer 11 is removed. Further, since the groove 35 is provided separately from the groove 31, it becomes possible to contact the etching gas or the etching liquid with the first semiconductor layer 11 under the second semiconductor layer 12. For this reason, it is possible to form the cavity 37 between the semiconductor substrate 1 and the second semiconductor layer 12 without impairing the quality of the second semiconductor layer 12.

When the semiconductor substrate 1 and the second semiconductor layer 12 are Si and the first semiconductor layer 11 is SiGe, for example, hydrofluoric acid is used as the etchant for the first semiconductor layer 11. Thereby, it is possible to remove the first semiconductor layer 11 while suppressing overetching of the semiconductor substrate 1 and the second semiconductor layer 12.

Next, as shown in FIGS. 7A to 7C, the semiconductor substrate 1 is thermally oxidized to form upper and lower surfaces in the cavity 37 (that is, the surface of the semiconductor substrate 1 facing the cavity 37, The back surface of the second semiconductor layer 12)
Insulating films 43 are formed respectively. In this thermal oxidation process, as shown in FIG.
5, the side surface of the second semiconductor layer 12 is exposed, so that the insulating film 43 is also formed on the side surface of the second semiconductor layer 12. The material of the insulating film 43 is a silicon oxide film when the semiconductor substrate 1 and the second semiconductor layer 12 are Si.

Next, in FIGS. 7A to 7C, the semiconductor substrate 1 is immersed in a predetermined chemical solution to form the cavity 3.
The entire substrate including the surface of the insulating film 43 in the substrate 7 is made lyophilic. Here, as the predetermined chemical solution, for example, a chemical solution consisting of any one of the following A) to D) or an arbitrary combination of A) to D) is used.
A) Hydrogen peroxide solution (H ₂ O ₂ + H ₂ O)
B) Ammonia hydrogen peroxide (NH ₄ OH + H ₂ O ₂ + H ₂ O)
C) Sulfuric acid / hydrogen peroxide (H ₂ SO ₄ + H ₂ O ₂ + H ₂ O)
D) Hydrochloric acid overwater (HCl + H ₂ O ₂ + H ₂ O)

Next, as shown in FIGS. 7B and 7C, for example, the support 41 from above the semiconductor substrate 1.
Ar or F is ion-implanted toward the surface of the substrate to make the surface of the support 41 covering the semiconductor substrate 1 lyophobic. In this ion implantation process, the depth of impurity distribution (Rp: project ran).
The implantation energy is adjusted to be low so that ge) is very close to the surface of the support 41.
Thus, the surface of the support 41 and the surface of the semiconductor substrate 1 exposed from the groove 35 (that is, the groove 35
Impurities are ion-implanted only on the bottom surface of the substrate, and the surface becomes lyophobic. Since almost no impurities reach the cavity, the cavity is not made lyophobic. The method for making the surface of the support 41 lyophobic is not limited to ion implantation, and for example, Ar plasma treatment may be used. Here, the Ar plasma treatment is a treatment that exposes the semiconductor substrate 1 to an Ar plasma atmosphere and damages the surface thereof.

Next, as shown in FIGS. 8A to 8C, the functional liquid 3 is passed through the groove 35 and into the cavity 37.
9 is introduced. Here, as the functional liquid 39, for example, a liquid composed of any one of the following a) to c) or any combination of a) to c) is used.
a) Liquid in which metal particles or semiconductor particles are dispersed in a solvent b) MOD (Metal Organic Decomposition) solution c) Silicon compound selected from liquid higher order silane solution, cyclopentasilane and silylcyclopentasilane, and inert organic medium In this embodiment, as the functional liquid 39, for example, silicon (Si) particles and phosphorus (P
) In a solvent, that is, phosphorus-doped liquid silicon is used.

Examples of a method for introducing the functional liquid 39 into the cavity 37 include spin coating and ink jet. When the functional liquid 39 is introduced by spin coating, a spin coater with a proven track record of use in resist coating processing by photolithography, SOG coating processing, or the like can be used, so that the coating processing can be easily performed. In addition, when the functional liquid 39 is introduced by inkjet, it is not necessary to apply the functional liquid 39 to the entire substrate, and if the functional liquid 39 is dropped only in the groove 35 to fill the cavity 37. Since it is good, the usage amount of the functional liquid 39 can be reduced.

In this embodiment, as shown in FIGS. 8A to 8C, the functional liquid 39 is applied to the entire substrate by, for example, spin coating. As a result, the functional liquid 39 is introduced into the cavity 37 through the groove 35, and the cavity 37 is filled with the functional liquid 39.
Next, the semiconductor substrate 1 is annealed to evaporate the solvent component contained in the functional liquid 39. Thereby, the functional liquid 39 in the cavity 37 is solidified. And FIG. 9 (a
As shown in (c) to (c), the solidified functional liquid is left in the cavity 37, and the functional liquid solidified from other regions (that is, the surface of the support 41 and the groove 35) is removed. remove. This selective removal of the solidified functional liquid is performed using, for example, a photolithography technique and an etching technique. Hereinafter, the solidified functional liquid left in the hollow portion 37 is referred to as a semiconductor layer 39 ′.

Next, as illustrated in FIGS. 10A to 10C, the support 41, the antioxidant film 23, the base oxide film 21, and the second semiconductor layer 12 are formed using, for example, a photolithography technique and an etching technique. A portion of the semiconductor layer 39 ′ is exposed from below the support 41 by selectively etching away. Then, as shown in FIGS. 11A to 11C, an insulating layer 45 is formed on the entire surface of the substrate by a method such as CVD, and a hole or groove 35 exposing a part of the semiconductor layer 39 ′ is exposed. Embed all. As a material of the insulating layer 45, for example, a silicon nitride film or the like may be used in addition to the silicon oxide film.

Next, the insulating layer covering the entire surface of the substrate is planarized by, for example, CMP, and the insulating layer 45 is removed from the antioxidant film 23. As described above, when the antioxidant film 23 is a silicon nitride film, the antioxidant film 23 functions as a stopper layer for a planarization process by CMP. Next, the antioxidant film 23 and the base oxide film 21 are removed by etching. When the antioxidant film 23 is a silicon nitride film, for example, hot phosphoric acid is used as an etchant, and the base oxide film 21 is used.
When is a silicon oxide film, for example, dilute hydrofluoric acid is used as an etchant. Thereby, as shown in FIGS. 12A to 12C, the surface of the second semiconductor layer 12 is exposed.

Next, as shown in FIGS. 13A to 13C, the surface of the second semiconductor layer 12 is thermally oxidized to form the gate insulating film 51 on the surface of the second semiconductor layer 12. Next, FIG.
And as shown to (c), the insulating layer 45 is selectively etched using a photolithographic technique and an etching technique, and the contact hole 52 to semiconductor layer 39 'is formed.
Then, for example, the functional liquid used for forming the semiconductor layer 39 ′ is formed on the entire substrate so as to fill the contact holes 52. The functional liquid is formed by, for example, spin coating. Further, after the functional liquid is applied, the semiconductor substrate 1 is annealed to solidify the functional liquid. Hereinafter, the functional liquid solidified by the annealing treatment is referred to as a conductive film.

Next, the conductive film is patterned using a photolithography technique and an etching technique. Thereby, as shown in FIGS. 14A to 14C, the gate electrode 53 connected to the semiconductor layer 39 ′ is formed. Although not shown in the drawing, the semiconductor layer 39 'and the gate electrode 53 can be formed as independent wirings. Next, using the gate electrode 53 as a mask, As, P,
Impurities such as B are ion-implanted into the second semiconductor layer 12, thereby forming LDD layers of the low-concentration impurity introduction layers disposed on both sides of the gate electrode 53 in the second semiconductor layer 12. Then, an insulating layer is formed on the second semiconductor layer 12 on which the LDD layer is formed by a method such as CVD, and the insulating layer is etched back using anisotropic etching such as RIE. Side walls 55 are formed on the side walls.

Further, impurities such as As, P, and B are ion-implanted into the second semiconductor layer 12 using the gate electrode 53 and the sidewall 55 as a mask. As a result, as shown in FIG. 15, a source layer 57 and a drain layer 58 made of high-concentration impurity introduction layers respectively disposed on the side of the sidewall 55 are formed in the second semiconductor layer 12.

Thus, according to this embodiment, an SOI transistor can be formed without using an SOI substrate. For this reason, it is possible to control the potential of the active region of the SOI transistor with the back gate electrode while suppressing the complexity of the manufacturing process, and it is possible to improve the rising characteristics of the drain current of the subthreshold region. . In addition, an increase in parasitic capacitance of the source / drain layer can be suppressed. As a result, it is possible to increase the on-state current of the transistor while suppressing an increase in cost, and to increase the speed of the SOI transistor. In addition, it is possible to reduce the leakage current at the time of OFF while enabling the low voltage operation, and it is possible to reduce the power consumption at the time of operation and standby.

Furthermore, in the present embodiment, by introducing the functional liquid 39 into the cavity 37,
A semiconductor layer 39 ′ that can be used as a back gate electrode (or a double gate electrode) is formed. With such a configuration, for example, a CVD method (Chemical Vapor)
Deposition) and ALD method (Atomic Layer Deposition)
Compared with the case where a metal layer or a semiconductor layer is formed in the cavity portion 37 using n), it is easy to make the metal layer or the semiconductor layer deposition material reach deep inside the cavity portion 37, It is possible to embed the hollow portion 37 without a gap.

That is, in this embodiment, after forming the cavity 37 on the back surface of the SOI-MOSFET, the cavity 37 is filled with a metal layer or semiconductor layer 39 ′ formed from the functional liquid 39. In particular, the inner wall of the groove 35 and the surface of the insulating film 43 in the cavity 37 are made lyophilic (higher surface energy), and the surface other than the groove 35 and the cavity 37 is made lyophobic (lower surface energy). In this state, the functional liquid 39 is introduced into the cavity 37. For this reason, the functional liquid 39 can penetrate deep into the cavity 37 in order to minimize the lyophilic surface energy of the insulating film 43 in the cavity 37, and the SOI layer (second semiconductor layer) 12 No voids or gaps are formed below the channel region. According to the present embodiment, regardless of the size ratio of the cavity portion 37, the unevenness of the inner surface of the cavity portion 37, or the size ratio between the groove 35 serving as a part of the element isolation region and the cavity portion 37,
Under the channel region of the SOI layer, a metal layer or a semiconductor layer 39 ′ serving as a back gate electrode,
It can be stably formed at a high yield.

FIG. 6 is a diagram (No. 1) illustrating a method for manufacturing a semiconductor device according to an embodiment. FIG. 6 is a diagram (part 2) illustrating the method for manufacturing the semiconductor device according to the embodiment. FIG. 3 is a diagram (part 3) illustrating the method for manufacturing the semiconductor device according to the embodiment. FIG. 4 is a diagram (part 4) illustrating the method for manufacturing the semiconductor device according to the embodiment. FIG. 5 is a diagram (No. 5) for explaining a method for manufacturing a semiconductor device according to the embodiment; FIG. 6 illustrates a method for manufacturing a semiconductor device according to the embodiment (No. 6). FIG. 7 is a diagram (No. 7) for explaining a method for manufacturing a semiconductor device according to an embodiment. FIG. 8 is a view (No. 8) illustrating the method for manufacturing the semiconductor device according to the embodiment. FIG. 9 is a diagram (No. 9) for illustrating a method for manufacturing a semiconductor device according to an embodiment; FIG. 10 is a view showing the method for manufacturing a semiconductor device according to the embodiment (No. 10). FIG. 11 is a diagram (11) illustrating the method for manufacturing the semiconductor device according to the embodiment; FIG. 12 is a view (No. 12) illustrating the method for manufacturing the semiconductor device according to the embodiment; FIG. 13 is a view showing a method for manufacturing a semiconductor device according to the embodiment (part 13); FIG. 14 is a diagram showing a method for fabricating a semiconductor device according to the embodiment (part 14); FIG. 10 illustrates a configuration example of a semiconductor device according to an embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate, 11 1st semiconductor layer, 12 2nd semiconductor layer, 21 Base oxide film, 23
Antioxidation film, 31 groove (first groove), 33 recess, 35 groove (second groove), 37 cavity,
39 functional liquid, 39 ′ semiconductor layer, 41 support (uppermost layer), 43 insulating film, 45
Insulating layer, 51 Gate insulating film, 53 Gate electrode, 55 Side wall, 57 Source layer, 58 Drain layer

Claims (5)

Forming a first semiconductor layer on a semiconductor substrate;
Forming a second semiconductor layer on the first semiconductor layer;
Forming a first groove through the second semiconductor layer and the first semiconductor layer to expose the semiconductor substrate;
Forming a support in the first groove for supporting the second semiconductor layer;
Forming a second groove exposing the first semiconductor layer from below the second semiconductor layer supported by the support;
The semiconductor substrate and the second semiconductor are etched by etching the first semiconductor layer through the second groove under a specific etching condition in which the first semiconductor layer is more easily etched than the second semiconductor layer. Forming a cavity between the layers;
Forming insulating films respectively on the upper and lower surfaces in the cavity,
A step of introducing a functional liquid into the cavity in which the insulating film is formed and filling the cavity with a metal layer or a semiconductor layer formed from the functional liquid. Production method. In the step of filling the cavity with the metal layer or the semiconductor layer,
Introducing the functional liquid into the cavity where the insulating film is formed;
The metal layer or the semiconductor layer is formed by subjecting the functional liquid introduced into the cavity to a heat treatment to evaporate a solvent component contained in the functional liquid. The manufacturing method of the semiconductor device of description. The semiconductor device according to claim 1, further comprising a step of making the surface of the insulating film in the cavity portion lyophilic before introducing the functional liquid into the cavity portion. Manufacturing method. 4. The method according to claim 1, further comprising the step of making the uppermost layer surface laminated on the semiconductor substrate lyophobic before introducing the functional liquid into the cavity. 5. The manufacturing method of the semiconductor device as described in any one. The functional liquid is a liquid comprising any one of the following a) to c), or any combination of a) to c):
a) a liquid in which metal particles or semiconductor particles are dispersed in a solvent,
b) MOD (Metal Organic Decomposition) solution,
c) Liquid higher order silane solution, a mixed solution of a silicon compound selected from cyclopentasilane and silylcyclopentasilane and an inert organic medium,
The method for manufacturing a semiconductor device according to claim 1, wherein:

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