JPH11233785A - Soimosfet and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make hot carriers generated in a channel area efficiently flow to a body contact area and, at the same time, to separate elements from each other. SOLUTION: A MOSFET constructed in an SOI(silicon on insulator) structure contains an insulating film 11; a first field oxide film 13 provided on the surface of the film 11; a first silicon area 21 containing a channel area 15, a source area 17, and a drain area 19 provided on the surface of the insulating film 11 surrounded by the oxide film 13; a second silicon area 23 which is provided on the surface of the insulating film 11 separately from the first silicon area 21 and has a body contact area 22; a third silicon area 25 provided on the surface of the insulating film 11 between the first and second silicon areas; and a second field oxide film 27 which is provided on the third silicon area 25 and separates the first and second silicon areas 21 and 22 from each other. The channel area 15 and body contact area 22 are electrically connected to each other through the third silicon area 25.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an SOI (Silicon on Insula) formed on a semiconductor layer formed on an insulating film.
The present invention relates to a MOSFET having a tor) structure, particularly a structure of an SOI MOSFET having a body contact and a method of manufacturing the same.

[0002]

2. Description of the Related Art MOS formed on a substrate having an SOI structure
In an FET, a semiconductor substrate and a transistor formation region are separated by an insulating film (SiO ₂ film). Therefore, element isolation can be easily performed, and CMOS
Latch-up phenomenon can be prevented. It is also known that the soft error rate can be further reduced.
In the SOI MOSFET, since the source and the drain are formed on the SiO ₂ film having a lower dielectric constant than the bulk substrate, the junction capacitance between the source and the drain can be reduced. Therefore, the junction capacitance of the FET is smaller than that of the bulk MOSFET.

[0003] Because of these features, SOIMOSFET
Is expected to be applied to high-speed, low-power-consumption ULSI.

However, the NMOS FE having the SOI structure
At T, of the hot carriers generated in the channel portion by the impact ionization phenomenon during operation, holes accumulate in the SOI structure. Due to the accumulation of holes, a floating substrate effect and a parasitic bipolar effect occur, which may cause a problem such as a decrease in drain withstand voltage.

[0005] In order to solve this problem, conventionally, for example, a document (W. Chen et al., Symp. On VLSI Tech. Dig. (199)
6) As described in p.
By providing a body contact, the accumulated holes are removed from the SOI structure.

SOI with body contact in literature
The structure of the MOSFET will be briefly described with reference to FIG. FIG. 17A is a diagram for explaining the structure of the SOIMOSFET, and is a plan view seen from above. FIG. 17B schematically shows a cross-sectional view of the cut surface taken along the line β-β in FIG. FIG.
(C) shows a cross section of a cut surface taken along line γ-γ in FIG. 17. Note that in the plan view of FIG. 17A, although not a cross section, it is hatched to emphasize a partial region.

A buried oxide film 101 (insulating film) of about 400 nm is formed on a silicon substrate 100, and a semiconductor layer 103 (silicon layer) is provided on the buried oxide film 101. In the semiconductor layer 103, there is a P-type channel region 105.
The gate electrode 107 is provided above the gate electrode 107 via a gate oxide film 109. Further, an N-type source region 11 is formed in a region outside one edge of the channel region 105 in the gate length direction.
1 is provided, and an N-type drain region 113 is formed in a region outside the other edge. On the other hand, regions outside the both ends in the gate width direction of the channel region 105 are covered with the field oxide film 115. Further, a field oxide film 115 is provided in an outer region which is in contact with three edges of the source region 111 and the drain region 113 other than the edge in contact with the channel region 105. The field oxide film 115 is formed on the buried oxide film 101. A thin silicon layer 1 of about 70 nm is formed between the field oxide film 115 and the buried oxide film 101.
17 are formed.

A P-type body contact region 119 is provided on buried oxide film 101. Body contact region 119 is provided at a predetermined distance from one end of channel region 105 in the gate width direction. I have. Further, body contact region 119 is provided on an extension in the gate width direction, and the surrounding regions are thin silicon layer 117 and field oxide film 1.
15 covered. Also, body contact region 11
9 and the channel region 105 are electrically connected via a thin silicon layer 117. The N-type source region 1
11 and the drain region 113 are buried oxide films 101
Since it is provided above and in contact with this, the source region 1
11 and the drain region 113 do not connect the body contact region 119 and the channel region 105.

Since channel region 105 and body contact region 119 are electrically connected via thin silicon layer 117, holes that are hot carriers generated in channel region 105 are removed from thin silicon layer 117 to body contact region 119. Flows to Thereby, accumulation of holes in the channel region 105 can be prevented.

[0010]

However, in the above-described SOIMOSFET structure, the field oxide film 1
Since the thin silicon layer 117 is present on the entire lower surface of the semiconductor device 15, the elements cannot be separated by the field oxide film 115. Therefore, if the distance between the elements is shortened in order to increase the density of the devices, there is a possibility that a leak may occur between the elements. Also, the SOIMOSFET is C
When using a MOSFET, latch-up may occur.

Further, an FET formed by miniaturizing the above-mentioned SOIMOSFET, for example, an FE having a gate of a sub-quarter μm or less in length.
At T, the length of the channel is also reduced. For this reason, the resistance of the channel in the gate width direction increases, and therefore, there arises a problem that holes generated in the channel hardly flow into the body contact region.

Therefore, the SOIMOS that allows hot carriers generated in the channel region to efficiently flow to the body contact region and isolates elements from each other.
There has been a demand for an FET and a method for manufacturing the same.

[0013]

SOIMOS of the present invention
According to the FET, the insulating film, the first field oxide film provided on the surface of the insulating film, and the channel region and the source region provided on the surface of the insulating film surrounded by the first field oxide film And a first silicon region having a body contact region and a first silicon region having a drain region, and a second silicon region having a body contact region provided on the surface of the insulating film at a distance from the first silicon region.
A silicon region, a third silicon region provided on the surface of the insulating film between the first silicon region and the second silicon region, and a first and second silicon region provided on the third silicon region. And a channel field and a body contact region are electrically connected via a third silicon region.

According to this structure, the two SOIMOSFs
ET, that is, the elements can be separated by the first field oxide film provided so as to reach the insulating film. Therefore, even if the distance between the elements is shortened, there is no possibility that a leak occurs between the elements. In addition, since the channel region and the body contact region are conductive through the third silicon region, carriers generated in the channel region can flow from the third silicon region to the body contact region during operation of the MOSFET. . Therefore,
According to the configuration of the present invention, it is possible to avoid a problem such as a decrease in drain withstand voltage due to a substrate floating effect or a parasitic bipolar effect.

[0015] Preferably, the third silicon region and the second field oxide film are provided in contact with one side of the channel region in the channel width direction.

According to this structure, the channel region and the body contact region can be made conductive through the third silicon region during the operation of the MOSFET, so that accumulation of carriers in the channel region can be prevented. . At this time, for example, a structure in which a body contact region is provided in contact with the third silicon region on one side of the channel region in the channel width direction and on an extension of the channel is provided. Good.

Preferably, the third silicon region and the second field oxide film are provided in contact with both sides of the channel region in the channel width direction.

As described above, the third silicon regions are provided in contact with both sides of the channel region in the channel width direction, and the body contact regions are formed in contact with the respective third silicon regions. During operation, carriers generated in the channel region can be extracted from both sides of the channel region to the body contact region. Therefore, accumulation of carriers in the channel region can be further prevented.

Preferably, the channel region is a region of the second conductivity type, the source region and the drain region are regions of the first conductivity type, the body contact region is a region of the second conductivity type, The silicon region is preferably a region of the second conductivity type.

When the SOIMOSFET is an NMOSFET, the first conductivity type is N-type and the second conductivity type is P-type. When the SOIMOSFET is a PMOSFET, the first conductivity type is P-type and the second conductivity type is N-type.
Type.

Further, in the SOIMOSFET of the present invention, a gate electrode formed on the channel region via a gate oxide film, sidewalls provided on both sides of the gate electrode in a gate length direction, and a source A source of a first conductivity type shallow junction formed in a first region portion below a sidewall of the region, and a second conductivity type formed in a second region portion of the source region below a shallow junction source in the source region. A first neutral region, a first conductivity type shallow junction drain formed in a first region portion below a sidewall of the drain region, and a second region portion below a shallow junction drain of the drain region. And a second neutral region of a second conductivity type formed in the first region. The first neutral region and the second neutral region are electrically connected to the third silicon region. A region other than the first and second region portions is formed as a source of the first conductivity type, a region other than the first and second region portions of the drain region is formed as a drain of the first conductivity type, and the channel region is formed as a drain. It is preferable to form the second conductive type channel region.

According to such a configuration, the second region below the shallow junction source and the second region below the shallow junction drain are formed.
Since a neutral region is formed in the region, the SOIMOS
Even if the FET is miniaturized and the channel length is shortened and the channel resistance in the gate width direction is increased, carriers generated in the channel region are allowed to flow from the neutral region to the body contact region through the third silicon region. Can be. For this reason, even if the device is miniaturized, carriers generated in the channel can efficiently flow to the body contact region.

In manufacturing the device of the SOI MOSFET of the present invention, the first field oxidation reaching the insulating film is performed by selectively oxidizing the silicon body layer formed on the insulating film while leaving the device forming region. Forming a film, thermally oxidizing a part of the element formation region, dividing the element formation region into a first silicon region and a second silicon region, and forming a silicon body layer in a part of the element formation region into a third silicon region. Forming a second field oxide film to be left as thin as above, and forming a channel region, a source region and a drain region in the first silicon region, and forming a body contact region in the second silicon region. .

According to this manufacturing method, the first element for separating the elements is used.
The field oxide film can be formed to reach the insulating film. Further, the third silicon region can be formed by leaving the silicon body layer under the second field oxide film separating the channel region and the body contact region. Therefore, elements can be separated as desired, and a passage for flowing carriers generated in the channel region to the body contact region can be secured as the third silicon region.

Preferably, the third silicon region is formed so as to be in contact with one side of the channel region in the channel width direction.

The third silicon region may be provided so as to be in contact with one side in the channel width direction of the first silicon region including the channel region, for example. With this configuration, it is not necessary to set the second silicon region to be electrically connected to the third silicon region at a position extended in the channel width direction of the channel region. Therefore, the wiring position of the gate electrode provided in the channel region can be designed with a margin.

[0027] Preferably, the third silicon region is
Two regions are preferably formed as a region in contact with one side of the channel region in the channel width direction and a region in contact with the other side of the channel region.

According to such a configuration, if two third silicon regions are formed on both sides of the channel region in the channel width direction, even if the channel resistance is increased and carriers are difficult to flow, the third silicon region is formed in the channel region. Since conduction can be made from both sides to the body contact regions that are in contact with the respective third silicon regions, more carriers can flow from the channel region.

Preferably, the silicon body layer is a layer of the second conductivity type, and the source region and the drain region are formed by implanting impurities of the first conductivity type into the first silicon region.

This allows the channel region of the first silicon region to remain at the second conductivity type, and the source region and the drain region on both sides of the channel region to be of the first conductivity type. At this time, for example, the first conductivity type is N-type, and the second conductivity type is P-type.

In the second field oxide film, a first conductivity type impurity implanted in the first silicon region is formed in the third silicon region in contact with the first silicon region when a source region and a drain region are formed later. Is formed as a film having a thickness that does not reach.

According to this structure, the second field oxide film for separating the first silicon region and the second silicon region is formed thin as described below. That is, the first conductive type impurity implanted into the first silicon region for forming the source and drain regions reaches the third silicon region therebelow from the surface side of the second field oxide film. It is formed as thin as possible. Then, the third silicon region can be made thicker by the reduced thickness, so that carriers can pass more easily, and thus, accumulation of holes in the channel region can be prevented. Note that if the first conductivity type impurity enters the third silicon region, the channel region and the body contact region may not be electrically connected.

In carrying out the manufacturing method of the present invention, a gate oxide film is formed on a channel region, a gate electrode is formed on the gate oxide film, and a shallow source and a shallow junction are formed in a source region and a drain region, respectively. Forming the respective drains by implanting impurity ions of the first conductivity type, and implanting impurity ions of the second conductivity type into the source region and the drain region with higher energy than the implantation of the first conductivity type impurity ions. By doing so, a second region is formed under the source of the shallow junction and the drain of the shallow junction.
Forming a neutral region of a conductivity type, forming sidewalls on both sides of the gate electrode in the gate length direction, and applying a first conductivity type to a shallow junction source and a shallow junction drain exposed from the sidewall. Preferably, the method includes a step of implanting impurity ions to change the shallow junction source and the shallow junction drain and the neutral region exposed from the sidewall into the source and the drain. The step of changing to a source and a drain is a step of forming a deep junction source and a deep junction drain.

According to this manufacturing method, a neutral region is formed in a region below a source having a shallow junction and a drain having a shallow junction sandwiching a channel region. In order to provide the neutral region so as to conduct to the third silicon region, the neutral region can be formed as a new passage for flowing carriers generated in the channel to the third silicon region. For this reason, even if the device is miniaturized and the channel resistance in the channel width direction is increased, carriers can efficiently flow to the body contact region.

According to another method of manufacturing an SOIMOSFET device of the present invention, a preliminary field oxide film is formed by selectively oxidizing a silicon body layer formed on an insulating film while leaving an element forming region. And performing thermal oxidation on a part of the element formation region and the preliminary field oxide film, thereby changing the preliminary field oxide film to a first field oxide film reaching the insulating film, and adding a part of the element formation region to the element formation region. A second field oxide film separating a formation region between the first silicon region and the second silicon region;
Forming a third silicon region with a silicon body layer remaining under the field oxide film, forming a channel region, a source region and a drain region in the first silicon region, and forming a body contact region in the second silicon region And forming a.

According to this structure, the preliminary field oxide film is formed by oxidizing the region of the silicon body layer which will be the first field oxide film, and thereafter, the preliminary field oxide film and the second field oxide film are formed. The oxidation treatment is performed on the region of the silicon body layer to be formed. Thereby, the first field oxide film and the second field oxide film having different thicknesses can be formed. The first field oxide film is a film that oxidizes the silicon body layer to reach the insulating film thereunder, and the second field oxide film is a third silicon film having a thickness below the silicon body layer through which the carriers can pass. It is formed to remain as a region. This third
The silicon region allows conduction between the channel region of the first silicon region and the body contact region of the second silicon region.

In carrying out this manufacturing method, preferably, the third silicon region may be formed so as to be in contact with at least one side of the channel region in the channel length direction. Area and the area that contacts the other side of the channel area,
Two may be formed.

Preferably, the silicon body layer is formed in the second
A source region and a drain region are formed by implanting impurities of the first conductivity type into the first silicon region.

In the second field oxide film, the impurity of the first conductivity type implanted into the first silicon region is formed in the third silicon region in contact with the first silicon region in the later formation of the source region and the drain region. Is formed as a film having a thickness that does not reach.

In the method of manufacturing the SOI MOSFET of the present invention, preferably, further, a gate oxide film is formed on the channel region, a gate electrode is formed on the gate oxide film, and then a source having a shallow junction is formed in the source region. Forming a drain having a shallow junction into the drain region by implanting impurity ions of the first conductivity type; and implanting impurity ions of the second conductivity type into the source region and the drain region, respectively, higher than the implantation of the first conductivity type impurity ions. Forming a neutral region of a second conductivity type in a region below a source having a shallow junction and a drain having a shallow junction, and forming sidewalls on both sides in a gate width direction of the gate electrode by implanting with energy. And the first conductivity type is applied to the source of the shallow junction and the drain of the shallow junction exposed from the sidewall. Forming a deep junction source and a deep junction drain in the shallow junction source and the shallow junction drain and the neutral region exposed from the sidewalls by implanting pure ions. Is good.

[0041]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. It should be noted that the shapes, sizes, and arrangements of the components in each drawing are only schematically shown to the extent that the invention can be understood, and thus the invention is not limited to the illustrated examples. Further, in the plan view, for easy understanding of the drawing, a part of the region other than the cross section is hatched (oblique line) to emphasize the region.

<First Embodiment> As a first embodiment, an NM having an SOI structure having a body contact region is described.
The OSFET will be described with reference to FIGS.

First, referring to FIG. 1 to FIG.
The structure of T will be described. FIG. 1 is a plan view of the SOI MOSFET according to the first embodiment as viewed from above.
FIG. 2 is a sectional view of a cut surface taken along line II-II in FIG. 1. FIG. 3 is a cross-sectional view taken along a line III-III in FIG.

An element (also referred to as a device, hereinafter the same) as an SOIMOSFET of this embodiment is formed by an insulating film 1.
1, a first field oxide film 13 provided on the surface of the insulating film 11, and a channel region 15 and a source region 17 provided on the surface of the insulating film 11 surrounded by the first field oxide film 13. A first silicon region 21 having a body contact region 22 and a second silicon region 23 provided on the surface of the insulating film 11 so as to be separated from the first silicon region 21; A third silicon region 25 provided on the surface of the insulating film 11 between the first silicon region 21 and the second silicon region 23; 23), the channel region 15 and the body contact region 22 are electrically connected via the third silicon region 25. And it has (see FIGS. 1 to 3.).

Here, the insulating film 11 is formed on the silicon substrate 1
A buried oxide film having a thickness of 100 nm is provided on the substrate 0. A gate electrode 31 is formed above the channel region 15 with a gate oxide film 29 interposed therebetween.
Further, the third silicon region 25 located under the second field oxide film 27 is formed as a layer having a thickness of 40 nm.

In this example, the third silicon region 25 and the second field oxide film 23 are provided in contact with one side of the channel region 15 in the channel width direction (indicated by a solid arrow a in FIG. 1). , A third silicon region 25 and a body contact region 22 on an extension of channel region 15.
Are formed (FIGS. 1 and 2).

The channel region 15 is a region of the second conductivity type, that is, a P-type region in this configuration example, and the source region 17 and the drain region 19 are of the first conductivity type, that is, N-type.
The area of the mold. Further, the third silicon region 25 and the body contact region 22 which are electrically connected to the channel region 15 are P-type.

In the MOSFET of this embodiment,
Of the hot carriers generated during the operation, electrons flow into the drain region 19 and holes flow into the third silicon region 25.
And flows into the body contact region 22. Also,
The first field oxide film 13 is an insulating film (buried oxide film)
11, there is no thin silicon layer under the first field oxide film 13. Therefore, source and drain regions 17 and 19, channel region 15 and body contact region 22 are separated from these regions of the adjacent element (FIGS. 2 and 3).

As described above, in this configuration example, the elements can be electrically separated from each other, and holes can flow from the channel region 15 to the body contact region 22 during the operation of the MOSFET. Therefore, holes are not accumulated in the channel region 15, and therefore, the substrate floating effect and the parasitic bipolar effect can be suppressed.

Next, a method of manufacturing the SOI MOSFET of this embodiment will be described with reference to FIGS. 4 and 5 are schematic manufacturing process diagrams of the SOI MOSFET, showing the MOSFET in a plan view from above. 6 and 7 are also manufacturing process diagrams. FIG.
FIG. 7 shows a cross section of a cut line taken along line VI-VI in FIG. 4, and FIG. 7 shows a cross section of a cut line taken along line VII-VII in FIG.

First, a first field oxide film reaching the insulating film is formed by performing selective oxidation on the silicon body layer formed on the insulating film while leaving the element formation region.

For this reason, here, the silicon substrate 10
SIMOX (Separati) comprising a 100 nm buried oxide film 11 on the silicon substrate 10 and a 140 nm P-type silicon body layer 41 on the buried oxide film 11.
om by Implamted Oxygen) First, a 30 nm SiO ₂ film 4 is formed on the silicon body layer 41 by thermal oxidation.
Form 3 Thereafter, LP-CVD is performed on the SiO ₂ film 43.
(Low Pressure-Chemical Vapor Deposition: Decompression CV
A silicon nitride film 45 is formed to a thickness of 150 nm by the method D) (FIGS. 4A and 6A). Element formation region 47 on silicon nitride film 45 (see FIG. 6B)
A resist pattern is formed at a position corresponding to the above (not shown). Thereafter, the silicon nitride film 45 in a region other than the element formation region 47 is removed by RIE (Reactive Ion Etching). After removing the resist pattern, the portion of the SiO ₂ film 43 exposed from the remaining silicon nitride film 45a is removed by wet etching using hydrofluoric acid to leave the SiO ₂ film 43a (FIG. 4 ( B) and FIG. 6 (B)). Next, using the remaining silicon nitride film 45a as a mask, the silicon body layer 41 is thermally oxidized to 400 n
An m-th first field oxide film 13 is formed. Since the first field oxide film 13 is formed as a film reaching the buried oxide film 11, the silicon body layer portion remaining as a silicon layer without being oxidized becomes the element formation region 47. The element forming region 47 is separated by the first field oxide film 13. After that, the silicon nitride film 45a is selectively removed by wet etching with phosphoric acid (FIGS. 4C and 6C).

Next, a part of the element formation region is thermally oxidized to divide the element formation region into a first silicon region and a second silicon region, and carriers can pass through a silicon body layer in a part of the element formation region. A second field oxide film is formed to be left as a third silicon region of a layer having such a thickness.

For this reason, here, a silicon nitride layer 49 is formed with a thickness of 150 nm on the element forming region 47 and the first field oxide film 13 by the LP-CVD method. Thereafter, a resist pattern in which a part of the element formation region 47 is opened is formed (not shown), and the silicon nitride layer 49 exposed from the opening of the resist is removed by RIE to form a first opening 50a. . Thereafter, the resist pattern is removed, and a portion of the SiO ₂ film 43a exposed from the first opening 50a of the remaining silicon nitride layer 49 is further removed by wet etching to form a second opening 50b (FIG. 5A). And FIG. 7 (A)). Next, a thermal oxidation process is performed on a portion of the element formation region 47 (the portion of the silicon body layer 41) exposed from the opening 50 including the first opening 50a and the second opening 50b, so that the second field oxide film 27 is formed. To form At this time, the thermal oxidation processing time is shorter than the processing time required for forming the first field oxide film 13. Due to this short thermal oxidation time, the second field oxide film 27 does not reach the buried oxide film 11, and a part of the silicon body layer 41 remains without being oxidized in the thickness direction. The thickness of the remaining silicon body layer is set to, for example, 40 nm. The remaining silicon body layer is referred to as a third silicon region 25. Further, since the second field oxide film 27 is formed, the element formation region 47 becomes the first silicon region 21 and the second silicon region 23 as regions on both sides of the oxide film 27.
And divided into Thereafter, the silicon nitride film 49 is selectively removed by wet etching with phosphoric acid, and the SiO ₂ film 43a is further removed by wet etching with hydrofluoric acid (FIGS. 5B and 7B).

In this manner, from the silicon body layer 41, the first and second silicon regions 21 and 23, the second field oxide film 27 separating them and the first
In addition, a third silicon region 25 which connects between the second silicon regions 21 and 23 and is located below the second field oxide film 27 can be formed.

In this case, the thickness of the layer of the third silicon region 25 may be such that the carriers generated in the channel region 15 can pass therethrough (about 40 nm in this example).

Next, a channel region is formed in the first silicon region,
A source region and a drain region are formed, and a body contact region is formed in the second silicon region.

Here, a gate oxide film 29 and a gate electrode 31 are sequentially formed in the first silicon region 21 to be the channel region 15 by using a normal MOSFET formation process. Thereafter, As ions are implanted into the first silicon regions 21 on both sides of the gate electrode 31 so that N
The source region 17 of N type and the drain region 19 of N type are formed. As a result, the P-type channel region 15 remains below the gate electrode 31. Also, the second silicon region 23
Then, BF ₂ is implanted to form a P-type body contact region 22. At this time, the body contact region 22
The impurity concentration of the surface made to be 1 × 10 ²⁰ cm ^-3 (Fig. 5 (C) and FIG. 7 (C)).

The SOIMOSFE formed as described above
T has a configuration in which the elements are separated by the first field oxide film 13, and furthermore, the channel region 15 and the body contact region 22 are electrically connected via the third silicon region 25.

As a result, during the operation of this device, hot carriers generated in channel region 15
No longer accumulate in the substrate, and the substrate floating effect and the parasitic bipolar effect can be suppressed. Further, even if the distance between the elements is shortened, there is no possibility that a leak occurs between the elements, so that the degree of integration of the elements can be increased. Furthermore, even when the above-described element structure is applied to an element constituting a CMOS, latch-up can be made free.

In this example, the NMOSFET has been described.
The same effect as in the case of T can be obtained. In this case, before forming the first field oxide film, an N-type impurity is introduced into the silicon main body layer by ion implantation, and the silicon main body layer is made to be N-type in advance.

<Second Embodiment> As a second embodiment, the SOIMOSFE manufactured in the first embodiment is used.
An example of manufacturing the structure of T by a different method will be described with reference to FIGS. 8 and 9 are schematic manufacturing process diagrams of the second embodiment, and FIG.
The FET is shown in a plan view from above. FIG. 9 is a cross-sectional view taken along a line IX-IX in FIG.

Hereinafter, points different from the first embodiment will be mainly described, and detailed description of the same points as those of the first embodiment will be omitted unless necessary. .

First, a preliminary field oxide film is formed by selectively oxidizing the silicon body layer formed on the insulating film while leaving the element formation region.

In this example, as in the first embodiment,
A silicon substrate 10, a buried oxide film 11 having a thickness of 100 nm provided on the silicon substrate 10, and a 140 nm thick buried oxide film provided on the buried oxide film 11.
A SIMOX substrate composed of a silicon body layer 41 of a mold type is used. A 30 nm SiO ₂ film 43 is formed on the silicon main body layer 41 in the same manner as in the first embodiment. After that, a 150-nm-thick silicon nitride film 45 is formed over the SiO ₂ film 43 (see FIGS. 4A and 6A). Next, the element formation region 4 on the silicon nitride film 45 is formed.
7 (see FIG. 6B), a resist pattern is formed. After that, the element formation region 47 is formed by RIE.
The silicon nitride film 45 in the other area is removed. After removing the resist pattern, the remaining silicon nitride film 4
The portion of the SiO ₂ film 43 exposed from 5a is removed to leave the SiO ₂ film 43a (see FIGS. 4B and 6B).

Next, in this embodiment, the silicon body layer 41 is thermally oxidized using the silicon nitride film 45a as a mask to form a preliminary field oxide film 51 of about 300 nm (FIG. 8A). And FIG.
(A)). This thermal oxidation treatment is performed in the preliminary field oxide film 5.
1 is not performed until the silicon body layer 41 is oxidized and reaches the buried oxide film 11 thereunder. Therefore, the silicon body layer 41 remains between the preliminary field oxide film 51 and the buried oxide film 11 with an appropriate thickness.

Next, in this embodiment, by performing thermal oxidation on a part of the element formation region and the spare field oxide film, the spare field oxide film is changed to the first field oxide film reaching the insulating film, and This element formation region is formed in a part of the element formation region by a first silicon region and a second silicon region.
A third silicon region is formed by the second field oxide film separated from the silicon region and the silicon body layer remaining under the second field oxide film.

For this reason, here, a resist pattern in which a part of the element forming region 47 is opened is formed on the preliminary field oxide film 51 and the silicon nitride film 45a (not shown). Subsequently, the portion of the silicon nitride film 45a exposed from the opening is removed by RIE to remove the third opening 5a.
2a is formed. Thereafter, the resist pattern is removed, and the third pattern is formed using the silicon nitride film 45a as a mask.
A portion of the SiO ₂ film 43a exposed from the opening 52a is removed by wet etching to form a fourth opening 52b (FIGS. 8B and 9B). Next, thermal oxidation is performed on the preliminary field oxide film 51 and the portion of the silicon main body layer 41 exposed from the opening portion 52 including the third and fourth openings (52a and 52b). By this thermal oxidation, the second field oxide film 27 having a thickness of about 200 nm is formed in the opening 52. This oxidation treatment is performed by removing the remaining portion of the silicon main body layer 41 below the preliminary field oxide film 51 formed earlier.
This is performed only for the time until oxidation to 1. In the thermal oxidation within this time, the second field oxide film 27 does not reach the buried oxide film 11 under the silicon body layer 41,
Under the field oxide film 27, the silicon body layer 41 remains with an appropriate thickness, for example, about 40 nm.
The remaining silicon body layer is referred to as a third silicon region 25. The element formation region 47 is divided into the first silicon region 21 and the second silicon region 23 by the second field oxide film 27. In addition, the preliminary field oxide film 51 is further oxidized by this thermal oxidation treatment to increase the film thickness to, for example, 400 nm, and
To the buried oxide film 11 below. As a result, the spare field oxide film 51 is changed to the first field oxide film 13 for element isolation. Thereafter, the silicon nitride film 45a is selectively etched by wet etching with phosphoric acid.
Then, the SiO ₂ film 43a is removed by wet etching with hydrofluoric acid (FIG. 8C and FIG. 9).
(C)). The thickness of the third silicon region 25 formed at this time may be determined in the same manner as described in the first embodiment.

Next, a channel region is formed in the first silicon region,
A source region and a drain region are formed, and a body contact region is formed in the second silicon region.

Here, in the same manner as in the first embodiment, a gate oxide film 29 and a gate electrode 31 are sequentially formed in the first silicon region 21 serving as the channel region 15 by using a normal MOSFET formation process. I do. After that, the first silicon regions 21 on both sides of the gate electrode 31 have A
By implanting s ions, an N-type source region 17 and an N-type drain region 19 are formed. As a result, the P-type channel region 15 remains below the gate electrode 31. Further, BF ₂ is implanted into the second silicon region 23 to form a P-type body contact region 22. At this time, the impurity concentration on the surface of body contact region 22 is 1 × 10
²⁰ cm ^-3 (FIG. 8 (D) and FIG.
(D)).

The SOIMOSF formed as described above
The ET has a configuration in which the elements are separated by a first field oxide film 13, and furthermore, the channel region 15 and the body contact region 22 are electrically connected via the third silicon region 25.

As a result, during the operation of this device, hot carriers generated in channel region 15
No longer accumulate in the substrate, and the substrate floating effect and the parasitic bipolar effect can be suppressed. Further, even if the distance between the elements is shortened, there is no possibility that a leak occurs between the elements, so that the degree of integration of the elements can be increased. Furthermore, even if the above-described device manufacturing method is applied to the manufacture of a device constituting a CMOS, the manufactured CMOS
Becomes latch-up free.

In this example, an NMOSFET has been described. However, as in the first embodiment, the present invention can be applied to a PMOSFET. In this case, before forming the first field oxide film, an N-type impurity is introduced into the silicon main body layer by ion implantation, and the silicon main body layer is made to be N-type in advance.

Further, the SOIMOSFE of this embodiment
If the manufacturing method of T is used, the first field oxide film and the second field oxide film having different film thicknesses can be formed using the same silicon nitride film as a mask.
The number of manufacturing steps of the OIMOSFET can be further reduced.

Third Embodiment As a third embodiment, an SOIMOSFET having a structure in which a third silicon region and a second field oxide film are provided in contact with both sides in the channel width direction of a channel region, respectively, will be described. ,
This will be described with reference to FIGS. FIG. 10 is a plan view of the SOI MOSFET according to the third embodiment as viewed from above, and FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. FIG. 12 shows a line segment XII − in FIG.
FIG. 2 is a cross-sectional view of a cut taken along XII.

Hereinafter, points different from the first and second embodiments will be described, and detailed description of the same points will be omitted.

The SOI MOSFET of this embodiment is
As in the first embodiment, an insulating film 11, a first field oxide film 13 provided on the surface of the insulating film 11,
A first silicon region 21 having a channel region 15, a source region 17, and a drain region 19 provided on the surface of the insulating film 11 surrounded by the first field oxide film 13; A second silicon region 23 having a body contact region 22 provided separately from the silicon region 21 and a second silicon region 23 provided on the surface of the insulating film 11 between the first silicon region 21 and the second silicon region 23. A third silicon region 25 and a second field oxide film 2 provided on the third silicon region 25 to separate the first and second silicon regions (21 and 23).
7, the channel region 15 and the body contact region 22 are electrically connected via the third silicon region 25 (see FIGS. 10 to 12).

Third silicon regions 25 are provided on both sides of the channel region 15 in the channel width direction (FIG. 11), and a second field oxide film 27 is formed on the third silicon region 25. (FIGS. 10 and 11). Also, second silicon regions 23 are arranged in contact with third silicon regions 25 (FIG. 1).
0). The gate electrode 3 is located above the channel region 15.
1 is provided via a gate oxide film 29 (FIG. 11).
And FIG. 12).

In this configuration example, as can be understood from FIG. 10, two second field oxide films 27 extend in the gate length direction (the direction of double-headed arrow b shown by a solid line in the figure). It is provided along the sides of the drain regions 17 and 19. One body contact region 22 is provided on an extension of the channel region 15 in the gate width direction (the direction of a double-headed arrow a indicated by a solid line in the drawing), and the other body contact region 22 is The second field oxide film 2 is spaced apart in the gate length direction.
7 is provided adjacently.

On the upper surface of the buried oxide film 11 below the second field oxide film 27, the second field oxide film 2
7, the third silicon region 25 is formed.
The silicon region 25 and the channel region 15 are in a state of being electrically connected to each other.

As a result, the hot carriers generated in the channel region 15 during the operation of the SOIMOSFET are not accumulated in the channel region 15, and the hot carriers generated in the channel region 15 are removed.
5 from both sides in the channel width direction.
Can be pulled out. Also, the third silicon region 25
May be provided in a region that is in contact with the channel region 15 and that does not allow conduction between adjacent elements.
Therefore, the body contact region 22 does not necessarily need to be formed on the extension of the channel region 15 (gate), but can be provided in another region in contact with the third silicon region 25 (see FIG. 10). This facilitates the design of the wiring of the gate electrode 31 to the channel region 25.

Further, as in the first embodiment, the first element
Since the device is separated by the field oxide film 13, there is no possibility that a leak occurs between elements even if the device is miniaturized.

Even if the channel region is miniaturized in response to the miniaturization of the device and the channel resistance in the channel width direction is increased, the carriers generated in the channel region when operating the element having the above-described configuration are not affected. Since the channel can be efficiently extracted from both sides of the channel in the channel width direction, problems such as a substrate floating effect and a decrease in drain withstand voltage due to a parasitic bipolar effect can be avoided.

The manufacture of the SOI MOSFET of this embodiment can be performed in the same manner as the method already described in the first and second embodiments.

As described above, in this embodiment, the third silicon region 25 is provided in contact with both sides of the channel region 15 in the channel width direction, and is equal to or longer than the length of the first silicon region 21. (FIG. 10). In this manufacturing method, when manufacturing the second field oxide film 27 and the third silicon region 25, which are the components of this MOSFET, a resist pattern for forming the second field oxide film 27 is formed in the element formation region 47. Are formed on the region including the photolithography technology. However, with the miniaturization of elements, the misalignment of the mask during photolithography exceeds the range of the error, and as a result, there is a possibility that the gate cannot be formed with the set gate width.
For this reason, there is a possibility that the performance of the manufactured device may be significantly reduced. According to the present invention, even if misalignment of the mask occurs during photolithography, there is no risk of changing the channel width of the channel region 15. Therefore, there is no possibility of changing the set gate width.

This point will be briefly described below. FIG. 13 is a schematic top view showing a case where the second field oxide film 27 is formed so as to be shifted in the channel width direction due to misalignment of a mask during photolithography in manufacturing the SOIMOSFET of this embodiment. FIG. FIG. 13A shows a case where a shift has occurred on the right side, and FIG. 13B shows a case where a shift has occurred on the left side. A portion surrounded by a dotted line in the drawing indicates a position where the second field oxide film 27 is originally formed. In FIGS. 13A and 13B, the second field oxide film 27 is formed shifted from the dotted line in the channel width direction. However, as in the third embodiment, the second
If the field oxide film 27 is provided, the channel width L of the channel region does not change even if a mask misalignment occurs during photolithography. Therefore, according to the present invention, a higher performance SOI MOSFET can be provided.

<Fourth Embodiment> A fourth embodiment has the same structure as the first and second embodiments, and is further provided on both sides of the gate electrode in the gate length direction. A source having an N-type shallow junction formed in a first region portion below the sidewall of the source region, and a second portion below a source having a shallow junction in the source region.
A first P-type neutral region formed in the region portion, an N-type shallow junction drain formed in the first region portion below the sidewall of the drain region, and a shallow junction drain in the drain region And a P-type second neutral region formed in a second region portion below the first region and the first neutral region and the second neutral region are electrically connected to the third silicon region. An example will be described with reference to FIG. 14 and FIG. FIG. 14 shows the SOIMOSF of this embodiment.
FIG. 15 is a plan view of the ET viewed from above, and FIG. 15 is a cross-sectional view of a cut surface taken along a line XV-XV in FIG.

Hereinafter, points different from the first and second embodiments will be described, and detailed description of the same points will be omitted.

The SOI MOSFET of this embodiment is
Similarly to the structures of the SOIMOSFETs of the first and second embodiments, the insulating film 11, the first field oxide film 13 provided on the surface of the insulating film 11, and the insulating film 11 are surrounded by the first field oxide film 13. A first silicon region 21 having a channel region 15, a source region 17, and a drain region 19 provided on the surface of the insulating film 11, and a first silicon region 21 provided on the surface of the insulating film 11 so as to be separated from the first silicon region 21. A second silicon region 23 having a body contact region 22; a third silicon region 25 provided on the surface of the insulating film 11 between the first silicon region 21 and the second silicon region 23; The first and second silicon regions (21 and 2)
3), the channel region 15 and the body contact region 22 are electrically connected via the third silicon region 25.

Further, the SOI of this embodiment
In the MOSFET, a gate electrode 31 formed on a channel region 15 via a gate oxide film 29 is formed.
And the first conductive type formed in the first region portion 55 below the sidewall 53a of the source region 17 and the sidewalls (53a and 53b) provided on both sides of the gate electrode 31 in the gate length direction. A source 55 having a shallow junction, a first neutral region 57 of a second conductivity type formed in a second region 57 below the source 55 having a shallow junction in the source region 17, and a sidewall 53 of the drain region 19.
b, formed in the first conductivity type shallow junction drain 59 formed in the first region portion 59 below, and the second region portion 61 formed in the second region portion 61 below the shallow junction drain 59 of the drain region 19. A second neutral region 61 of a conductivity type.
The first neutral region 57 and the second neutral region 61
It is electrically connected to the silicon region 25.

In the configuration example, the first conductivity type is N-type and the second conductivity type is P-type. Therefore, the first and second region portions (5
Areas other than 5 and 57) are set as N-type sources 63,
And the first and second region portions (5
Regions other than 9 and 61) are formed as N-type drains 65. Further, the channel region 15 is made to be P-type (FIGS. 14 and 15).

The source 55 of the shallow junction and the drain 59 of the shallow junction are regions usually called source / drain extensions. The P-type neutral regions (the first neutral region 57 and the second neutral region 61) formed below the shallow junction source 55 and the shallow junction drain 59 are formed in the channel region 15. It is provided for the purpose of suppressing the spread of the depletion layer, and is called a neutral region because it is a region that is not affected by an electric field during operation of the MOSFET. Since the neutral regions (57 and 61) are electrically connected to the third silicon region 25, they serve as a passage for carriers generated in the channel region 15 to flow to the body contact region 22.

During the operation of the MOSFET, a depletion layer is formed in channel region 15 under gate electrode 31. A neutral portion that is not affected by an electric field is formed below the depletion layer of the channel region 15, and hot carriers flow from the neutral portion to the third silicon region 25. When the gate length becomes shorter with miniaturization of the device, the cross-sectional area of the neutral portion in the channel region 15 becomes smaller, and the channel resistance in the gate width direction becomes higher. This makes it difficult for carriers generated in the channel region 15 to flow from the channel region 15 to the third silicon region 25, so that the efficiency of extracting carriers (here, holes) to the body contact region 22 decreases. For this reason, even if the body contact region 22 is provided, the substrate floating effect may be generated.

Therefore, as in this embodiment, a source 55 and a drain 59 having a shallow junction are formed in the source region 17 and the drain region 19, and the lower side of the source 55 and the drain 59 having the shallow junction are formed. P-type neutral region (first neutral region 57 and second neutral region 61)
Is formed, hot carriers generated in the channel region 15 are converted into a neutral portion in the channel region 15 and
Through the first neutral region 57 and the second neutral region 61,
In order to flow to the third silicon region 25, a neutral part in the channel region 15 can be substantially expanded. Therefore, there is no possibility that the channel resistance in the gate width direction becomes high even if the gate length becomes short.

Next, the SOIMOSFE of this embodiment will be described.
The method of manufacturing T will be described with reference to FIG. FIG.
6 is a main manufacturing process diagram of the SOIMOSFET of this embodiment, which is shown in a cross-sectional view corresponding to FIG.

First, in the same manner as in the first embodiment, an element forming region is formed on a 140 nm-thick silicon body layer 41 formed on an insulating film 11 (buried oxide film having a thickness of 100 nm). By performing selective oxidation while leaving 47, a first field oxide film 13 reaching the insulating film 11 is formed with a thickness of 400 nm (FIGS. 4A to 4C and FIGS. 6A to 6C). Next, a part of the element formation region 47 is thermally oxidized to divide the element formation region 47 into the first silicon region 21 and the second silicon region 23, and the silicon body layer 41 in a part of the element formation region 47. Is formed as a third silicon region 25 to have a thickness of 200 nm (FIG. 5A).
See (B) and FIGS. 7 (A)-(B). ).

Thereafter, gate oxide film 29 and gate electrode 31 are formed on channel region 15 (FIG. 16).
(A)).

Next, in the source region and the drain region,
By implanting N-type impurity ions, respectively, a source and a drain having a shallow junction are formed.

In this case, As is applied at 5 keV and 1 × 10 ¹⁵ c
By performing ion implantation under the condition of m ^−2, a source 55 and a drain 59 having a shallow junction are formed.

Next, P is added to the source region and the drain region.
By implanting the impurity ions at a higher energy than when implanting the N-type impurity ions, neutral regions of the second conductivity type are formed in the regions below the shallow junction source and drain, respectively.

Here, BF ₂ is applied to the region to be the source region 17 and the region to be the drain region 19 by 70 ke.
V, ions are implanted under the condition of 2 × 10 ¹³ cm ⁻² . As a result, P-type neutral regions (57 and 5) are formed in regions under the source 55 and the drain 59 of the shallow junction, respectively.
9) is formed (FIG. 16B).

Next, sidewalls are formed on both sides of the gate electrode in the gate length direction.

Here, TEOS (Tetra Etoxy Silan)
e: a 200 nm thick SiO ₂ film is formed by a CVD method using tetraethoxysilane), and then etched back by RIE to form sidewalls (53a and 53b) on both sides of the gate electrode 31 in the gate length direction. ) Is formed (FIG. 16C).

Next, exposed from the sidewall,
The source and drain of the shallow junction and the neutral regions (first and second neutral regions) are changed to sources and drains. This source and drain form a deep junction.

Here, As is introduced by ion implantation into the regions exposed from the side walls (53a and 53b) to be the source region 17 and the drain region 19 under the conditions of 60 keV and 5 × 10 ¹⁵ cm ^−2. do it,
A deep junction source 63 and drain 65 are formed.
Thereafter, using a rapid heating device (RTA), 1000 ° C.
A heat treatment is performed for 10 seconds at the temperature described above to activate the source 63 and the drain 65 (FIG. 16D).

Thus, the SOI of this embodiment is
MOSFET with shallow junction source 55 and drain 5
9 and a P-type neutral region (57 and 61) under which a carrier generated in the channel region 15 becomes a new path from the channel region 15 to the third silicon region 25.
Can be formed.

In this example, an NMOSFET having an SOI structure
However, the present invention may be applied to a PMOSFET. In this case, the source and drain of the shallow junction are formed by introducing a P-type impurity, and an N-type impurity is used for ion implantation for forming a neutral region thereunder.

Also, the SOIMOSFE of this embodiment
The first field oxide film and the second field oxide film of T may be formed in the same manner as in the second embodiment.

Further, the third silicon region may be provided on both sides in the channel width (gate width) direction of the channel region as in the third embodiment.

In each of the embodiments described above, the film thickness, impurity concentration, voltage, temperature, time and the like are specifically exemplified.
These numerical examples are only preferred examples for practicing the present invention, and therefore, the present invention is not limited to these numerical values.

[0111]

As is clear from the above description, according to the SOI MOSFET of the present invention, the insulating film, the first field oxide film provided on the surface of the insulating film, and the first field oxide film surrounded by the first field oxide film. A first silicon region having a channel region, a source region and a drain region provided on the surface of the formed insulating film, and a body contact region provided on the surface of the insulating film so as to be separated from the first silicon region. A second silicon region, a third silicon region provided on the surface of the insulating film between the first silicon region and the second silicon region, and a first and a second silicon region provided on the third silicon region. The second separating the two silicon regions
A field oxide film, and the channel region and the body contact region are electrically connected via the third silicon region.

According to this configuration, two SOIMOSFs
ET, that is, the elements can be separated by the first field oxide film provided so as to reach the insulating film. Therefore, even if the distance between the elements becomes short, there is no possibility that a leak occurs between these elements. In addition, since the channel region and the body contact region are electrically connected via the third silicon region, during the operation of the MOSFET,
Carriers generated in the channel region can flow from the third silicon region to the body contact region. Therefore, it is possible to avoid problems such as a reduction in drain withstand voltage due to a substrate floating effect and a parasitic bipolar effect.

[Brief description of the drawings]

FIG. 1 is a plan view schematically showing a structure of an SOI MOSFET according to a first embodiment.

FIG. 2 is an SOI MOSFET taken along line II-II in FIG.
It is a figure which shows the cut surface which cut | disconnected roughly.

FIG. 3 shows SOIMOSF along line III-III in FIG.
It is a figure which shows the cut surface which cut | disconnected ET schematically.

FIGS. 4A to 4C are schematic manufacturing process diagrams for explaining the first embodiment;

FIGS. 5A to 5C are manufacturing process diagrams following FIG. 4 for describing the first embodiment;

6 (A) to 6 (C) are cross-sectional views taken along line VI-VI in FIG. 4 and are manufacturing process diagrams.

FIGS. 7A to 7C are cross-sectional views taken along line VII-VII in FIG. 5, and are manufacturing process diagrams following FIG.

FIGS. 8A to 8D show SOI according to the second embodiment;
It is a schematic manufacturing process figure of MOSFET.

FIGS. 9A to 9D show SOI according to the second embodiment;
FIG. 9 is a schematic manufacturing process diagram of the MOSFET, and is a line segment of FIG.
It is sectional drawing of the cut surface cut | disconnected along IX-IX.

FIG. 10 is a plan view of the SOIMOSFET of the third embodiment as viewed from above.

FIG. 11 is a sectional view of a cut surface taken along line XI-XI in FIG. 10;

12 is a cross-sectional view of a cut surface taken along a line XII-XII in FIG.

FIGS. 13A and 13B are schematic plan views for explaining a third embodiment; FIGS.

FIG. 14 is a plan view of the SOIMOSFET according to the fourth embodiment as viewed from above.

FIG. 15 is a sectional view of a cut surface taken along line XV-XV in FIG. 14;

FIGS. 16 (A) to (D) show SO in the fourth embodiment;
It is a main manufacturing process diagram of an IMOSFET.

17A is a plan view of a conventional SOIMOSFET viewed from above, FIG. 17B is a cross-sectional view taken along line β-β of FIG. 17A, and FIG. , The line segment γ of (A)
It is sectional drawing cut | disconnected along-(gamma).

[Explanation of symbols]

10, 100: silicon substrate 11, 101: insulating film (buried oxide film) 13, 115: first field oxide film 15, 105: channel region 17, 111: source region 19, 113: drain region 21: first silicon region 22, 119: body contact region 23: second silicon region 25: third silicon region 27: second field oxide film 29, 109: gate oxide film 31, 107: gate electrode 41: silicon body layer 43: SiO ₂ film 43a : (Remaining) SiO ₂ film 45: silicon nitride film 45 a: (remaining) silicon nitride film 47: element formation region 49: silicon nitride layer 50: opening 50 a: first opening 50 b: second opening 51: preliminary field Oxide film 52: Opening 52a: Third opening 52b: Fourth opening 53a: Side of source region Wall 53b: Side wall of drain region 55: First region of source region (shallow junction source) 57: Second region of source region (first neutral region) 59: First region of drain region (shallow) Junction drain) 61: Second region portion of drain region (second neutral region) 63: Source 65: Drain 103: Semiconductor layer (silicon layer) 117: Thin silicon layer

Claims (17)

[Claims] An insulating film; a first field oxide film provided on a surface of the insulating film; a channel region and a source provided on a surface of the insulating film surrounded by the first field oxide film. A first silicon region having a region and a drain region; a second silicon region having a body contact region provided on the surface of the insulating film so as to be separated from the first silicon region; A third silicon region provided on the surface of the insulating film between the second silicon region and a second field oxide provided on the third silicon region and separating the first and second silicon regions; A SOI MOSFET including a film, wherein the channel region and the body contact region are electrically connected via the third silicon region. 2. The SOI MOSFET according to claim 1, wherein said third silicon region and said second field oxide film are:
An SOI MOSFET provided in contact with one side of the channel region in a channel width direction. 3. The SOI MOSFET according to claim 1, wherein said third silicon region and said second field oxide film are:
An SOIMOSFET provided in contact with both sides of the channel region in the channel width direction. 4. The S according to claim 1, wherein
In the OIMOSFET, the channel region is a region of a second conductivity type, the source region and the drain region are regions of a first conductivity type,
The body contact region is a region of the second conductivity type,
2. The SOI MOSFET according to claim 1, wherein the third silicon region is a second conductivity type region. 5. The S according to claim 1, wherein
In the OIMOSFET, further, a gate electrode formed on the channel region via a gate oxide film; sidewalls provided on both sides of the gate electrode in a gate length direction; A first conductive type shallow junction source formed in a lower first region portion; and a second conductive type first junction formed in a second region portion of the source region below the shallow junction source. A neutral region, a first conductivity type shallow junction drain formed in a first region portion of the drain region below the sidewall, and a second region below the shallow junction drain of the drain region. A second neutral region of a second conductivity type formed in a portion, wherein the first neutral region and the second neutral region are electrically connected to the third silicon region, A region of the source region other than the first and second region portions is formed as a first conductivity type source, and a region of the drain region other than the first and second region portions is formed as a first conductivity type drain. And an SOI MOSFET wherein the channel region is formed as a second conductivity type channel region. 6. In manufacturing an SOIMOSFET, a first field oxide film reaching the insulating film is formed by selectively oxidizing a silicon body layer formed on the insulating film while leaving an element formation region. And thermally oxidizing a part of the element formation region to divide the element formation region into a first silicon region and a second silicon region.
Forming a second field oxide film that leaves a silicon body layer in a part of the element formation region as a third silicon region having a thickness that allows carriers to pass through; a channel region and a source in the first silicon region; Forming a region and a drain region, and forming a body contact region in the second silicon region. 7. The method for manufacturing an SOIMOSFET according to claim 6, wherein the third silicon region is formed so as to be in contact with at least one side of the channel region in a channel width direction. Method. 8. The method for manufacturing an SOIMOSFET according to claim 6, wherein the third silicon region is in contact with one side of the channel region in a channel width direction, and is in contact with the other side of the channel region. Forming two SOIMOSFETs. 9. The method for manufacturing an SOIMOSFET according to claim 6, wherein the silicon body layer is a layer of a second conductivity type, and the source region and the drain region are of a first conductivity type with respect to the first silicon region. A method of manufacturing an SOI MOSFET, wherein the SOI MOSFET is formed by implanting impurities. 10. The SOI MOSFET according to claim 6,
In the manufacturing method, the second field oxide film may be configured such that the impurity of the first conductivity type implanted into the first silicon region is formed in the first silicon region by forming the source region and the drain region later. A method for manufacturing an SOI MOSFET, wherein the SOI MOSFET is formed as a film having a thickness that does not reach a third silicon region in contact with the SOI MOSFET. 11. The method of manufacturing an SOI MOSFET according to claim 6, wherein a gate oxide film is formed on the channel region, and a gate electrode is formed on the gate oxide film. Forming a source having a shallow junction in a source region and a drain having a shallow junction in a drain region by implanting impurity ions of a first conductivity type, respectively; By implanting at a higher energy than the implantation of the first conductivity type impurity ions, a second region is formed in a region below the source of the shallow junction and the drain of the shallow junction.
Forming a neutral region of a conductive type; forming sidewalls on both sides of the gate electrode in the gate length direction; forming a shallow junction source and shallow junction drain Changing the source and drain of the shallow junction and the drain of the shallow junction and the neutral region exposed from the sidewall into a source and a drain by implanting impurity ions of one conductivity type. SOIMOSFET manufacturing method 12. When manufacturing an SOI MOSFET, a step of selectively oxidizing a silicon body layer formed on an insulating film while leaving an element formation region to form a spare field oxide film; By performing thermal oxidation on a portion of the preliminary field oxide film and the preliminary field oxide film, the preliminary field oxide film is changed to a first field oxide film reaching the insulating film, and the element isolation region is formed in a part of the element formation region. Forming a second field oxide film separated from the first silicon region and the second silicon region, and forming a third silicon region with a silicon body layer remaining under the second field oxide film; A channel region, a source region, and a drain region are formed in one silicon region, and a body contact region is formed in the second silicon region. And a method for manufacturing an SOI MOSFET. 13. The SOIMOSFE according to claim 12,
In the method for manufacturing T, the third silicon region is formed so as to be in contact with at least one side of the channel region in the channel width direction. 14. The SOIMOSFE according to claim 12, wherein:
In the method of manufacturing T, two of the third silicon regions are formed as a region in contact with one side of the channel region in a channel width direction and a region in contact with the other side of the channel region. Manufacturing method of SOIMOSFET. 15. The SOIMOSFE according to claim 12, wherein:
In the method of manufacturing T, the silicon body layer may be a second conductivity type layer, and the source region and the drain region may be formed by implanting a first conductivity type impurity into the first silicon region. A method for manufacturing an SOI MOSFET, which is characterized by the following. 16. SOIMOSFE according to claim 12.
In the method of manufacturing T, the second field oxide film may be configured such that the impurity of the first conductivity type implanted into the first silicon region is formed in the first silicon region by forming the source region and the drain region later. Forming a film having a thickness that does not reach the third silicon region in contact with the SOI MOSFET. 17. The method for manufacturing an SOI MOSFET according to claim 12, further comprising: forming a gate oxide film on the channel region;
Forming a gate electrode on the gate oxide film, forming a source having a shallow junction in the source region and a drain having a shallow junction in the drain region by implanting impurity ions of a first conductivity type, respectively; By implanting impurity ions of the second conductivity type into the region and the drain region with higher energy than the implantation of the impurity ions of the first conductivity type, the second conductivity type impurity ions are implanted into the region below the source at the shallow junction and the drain under the shallow junction drain. 2
Forming a neutral region of a conductive type; forming sidewalls on both sides of the gate electrode in the gate length direction; forming a shallow junction source and shallow junction drain Changing the source and drain of the shallow junction and the drain of the shallow junction and the neutral region exposed from the sidewall into a source and a drain by implanting impurity ions of one conductivity type. SOIMOSFET manufacturing method