JPH1093101A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress generation of a hump to a static characteristic by providing a p-type diffusion region of higher concentration than a p-type semiconductor layer formed on the p-type semiconductor layer of a terminal part in the gate width direction of a first-channel region. SOLUTION: A p-type channel region 9a and an n-type source-drain region 12 are formed on an nMOSFET formation region, and an n-type channel region 9b and a p-type source-drain region 12b are formed in the pMOSFET formation region. An insulating film 7 is buried between the nMOSFET regions 9a, 12a and the pMOSFET regions 9b, 12b, and an insulating film 6 is formed between the pMOSFET regions 9b, 12b and the insulating film 7. On the other hand, a p<+> -type high concentration impurity region 8 is formed between the nMOSFET region 9a and the insulating layer 7, so as to allow suppression of a hamp of a static characteristic to be generated by a gate electric field concentration at the corner part of a terminal part of the channel region 9a.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a device for isolating a complementary field effect transistor formed on an insulator.

[0002]

2. Description of the Related Art Generally, a complementary field effect transistor (hereinafter referred to as SOI (Silicon On Insul
ator) -CMOS FET), as shown in FIG. 8A, an insulating film 102 is provided on a silicon substrate 101, and a semiconductor layer called an SOI layer is formed on the insulating film 102. A channel region 109a is formed in a region of the semiconductor layer where the n-channel MOSFET is formed.
And a source / drain region 112a are formed, and a channel region 109b is formed in a p-channel MOSFET formation region.
And source and drain regions 112b.

Further, gate electrodes 111 are formed in the channel regions 109a and 109b with a gate insulating film 110 interposed therebetween.

In order to separate the n-channel MOSFET and the p-channel MOSFET, a LOCOS oxide film 103 formed by selectively oxidizing the SOI layer is used.
Is used.

In order to separate these MOSFETs, as shown in FIG. 9A, a method of patterning an SOI layer by anisotropic etching and then burying a silicon oxide film 107 is used.

[0006]

However, the element isolation structure of the SOI-CMOSFET having the above structure has the following problems.

The element isolation structure by the LOCOS method as shown in FIG. 8A has a problem that it is difficult to perform a minute element isolation of 0.4 μm or less. Further, as shown in FIG. 8B, a region 120 is formed in which the thickness of the SOI layer 109a at the edge of the LOCOS oxide film 103 is extremely thin as compared with other regions. In addition, since impurity atoms such as boron introduced into the channel region of the nMOS field effect transistor have a characteristic that they are easily absorbed into the oxide film, the impurity atoms are removed at the edge portion 120 of the LOCOS oxide film 103 covered with the gate electrode 111. The concentration is lower than in other channel regions. For this reason, as the gate voltage is applied, this region is inverted earlier than the other regions, and the one that should have the static characteristics as shown in FIG. Na hump
Characteristics, and it becomes difficult to set a threshold value.

On the other hand, in an element isolation structure formed by embedding an insulating film as shown in FIG.
There is an advantage that a fine element isolation can be formed as compared with the element isolation by the S method, and the SOI film thickness does not become extremely thin unlike the edge portion 120 of the LOCOS oxide film 103. However, due to an oxide film stripping process performed after element isolation formation, the buried oxide film 107 at the end of the transistor formation region has an enlarged region 130 shown in FIG. 9B as shown in FIG. 140 is formed, and the "corner" at the end of the transistor formation region is exposed.
If a gate electrode is present on this corner, the electric field due to the voltage applied from the gate electrode will concentrate at this corner, and this area will also be inverted earlier than other areas. In this case, a problem arises that a "hump" characteristic as shown at 150 in FIG. 11 is exhibited. In addition, at the interface between the semiconductor layers 109a and 10b and the element isolation insulating film 107, a problem arises that a leak current flows between the source and the drain due to the generated interface state.

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above circumstances, and has as its object to provide a semiconductor device and a method of manufacturing the same, which can minimize the occurrence of humps in static characteristics. .

[0010]

According to a first aspect of the present invention, there is provided a semiconductor device comprising: an insulating layer formed on a substrate; a p-type semiconductor layer provided on the insulating layer; An n-type semiconductor layer provided on a material layer and insulated from the p-type semiconductor layer by an insulating film; and n-type source and drain regions formed separately from the p-type semiconductor layer. And p formed separately in the n-type semiconductor layer.
A first channel region formed in the p-type semiconductor layer between the n-type source region and the n-type drain region; a p-type source region; A second channel region formed in the n-type semiconductor layer between the p-type drain region, a first gate electrode formed on the first channel region,
A second gate electrode formed on the second channel region and a height higher than the p-type semiconductor layer formed on the p-type semiconductor layer at an end of the first channel region in a gate width direction; And a p-type diffusion region having a concentration.

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a silicon layer on an insulator layer;
Forming a mask layer on the silicon layer of the substrate; forming first and second island-shaped regions by patterning the mask layer and the silicon layer; Forming a first insulating film only on the side surface of the silicon layer in a region, and embedding a second insulating film containing p-type impurity atoms around the first and second island regions. The first heat treatment
Forming the p-type diffusion region by diffusing the p-type impurity atoms from the second insulating film to the side surface of the silicon layer in the island-like region; and forming the p-type diffusion region in the first and second island-like regions. Forming a n-channel MOSFET and a p-channel MOSFET, respectively.

A semiconductor device according to a third aspect of the present invention comprises:
An insulator layer formed on a substrate, an annular first semiconductor layer formed on the insulator layer, and the first semiconductor layer on the insulator layer inside the first semiconductor layer An island-shaped second semiconductor layer formed separately from the first semiconductor layer; a first insulating film formed on each side surface of the first semiconductor layer and the second semiconductor layer; A conductive film formed on the insulator layer in a region surrounded by a layer and the second semiconductor layer so as to bury the surrounded region, and to cover an upper surface of the conductive film; A second insulating film,
A source region and a drain region of a first conductivity type formed separately in the second semiconductor layer; and a first conductivity type formed in the second semiconductor layer between the source region and the drain region. A channel region having a different second conductivity type and a gate electrode formed on the channel region are provided.

According to a fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of:
Forming a mask layer on the silicon layer on the substrate;
Forming an annular region and an island-shaped region separated from the annular region inside the annular region by patterning the mask layer and the silicon layer;
Forming a first insulating film on a side surface of the silicon layer in the annular region and a side surface of the silicon layer in the island region; and a region surrounded by the annular region and the island region Embedding a conductor film on the insulator layer; and forming a second insulating film so as to cover the conductor film.

A semiconductor device according to a fifth aspect of the present invention comprises:
A first insulator layer formed on the substrate, an island-shaped first conductor layer formed on the first insulator layer,
An annular first semiconductor layer formed on the first conductor layer via a second insulator layer, and the second insulation layer on the first conductor layer inside the first semiconductor layer. An island-shaped second semiconductor layer formed separately from the first semiconductor layer via a material layer, a first insulating film formed on a side surface of the first conductor layer, A second insulating film formed on each side surface of the first and second semiconductor layers, and the first conductor layer in a region surrounded by the first semiconductor layer and the second semiconductor layer; A second conductor layer electrically connected to the first conductor layer and formed so as to bury the enclosed region; and a second conductor layer formed to cover an upper surface of the second conductor layer. A third insulating film, a source region and a drain region of a first conductivity type formed separately in the second semiconductor layer, The second between the serial drain region
And a second conductive type channel region different from the first conductive type formed in the semiconductor layer, and a gate electrode formed on the channel region.

According to a sixth aspect of the present invention, in a method of manufacturing a semiconductor device, a first insulator layer, a first conductor layer,
Forming a mask layer on the semiconductor layer of the substrate on which the second insulator layer and the semiconductor layer are sequentially formed; and patterning the mask layer, the semiconductor layer, and the second insulator layer to form an annular shape. Forming a region and an island-shaped region separated from the ring-shaped region inside the ring-shaped region; and forming a side surface of the semiconductor layer in the ring-shaped region and a side surface of the semiconductor layer in the island-shaped region. Forming a first insulating film, and electrically connecting to the first conductive layer on the first conductive layer in a region surrounded by the annular region and the island-shaped region. Embedding the enclosed region with a second conductor layer so as to cover the second conductor layer, and forming a second insulating film so as to cover the second conductor layer. And

In the present invention, an oxidation-resistant mask can be used as the mask layer, and can be used as a mask for selectively oxidizing the island-shaped silicon region. Further, the insulating film can be used as a mask when the insulating film is selectively left in the island-shaped region by leaving the side wall by anisotropic etching. In the above method, for example, a silicon nitride film can be used as the mask layer.

[0017]

FIG. 1 shows a first embodiment of the present invention.
This will be described with reference to FIG. This embodiment is based on SOI-CMO
1. A semiconductor device having an SFET, the structure of which is shown in FIG.
(A), (b) and (c) show. An insulator layer 2 is formed on a semiconductor substrate 1, and a plurality of island-shaped SOI regions are provided on the insulator layer 2. In this island-shaped SOI region, a p-type channel region 9a and an n-type source / drain region 12a are formed in an nMOSFET formation region, and an n-type channel region 1 is formed in a pMOSFET formation region.
2b and a p-type source / drain region 12b are formed (see FIG. 1A). And each channel region 9
a, 9b on the gate electrode 1 via a gate insulating film 10.
1 is formed.

Further, these nMOSFET regions 9a,
An insulating film 7 made of, for example, BSG (boron-doped glass) is buried between the 12a and the pMOSFET regions 9b, 12b. Then, the pMOSFET regions 9b, 1
An insulating film 6 made of, for example, SiO ₂ is provided between the insulating film 2b and the insulating film 7 (see FIGS. 1A and 1C).

On the other hand, ap ⁺ -type impurity region 8 is formed between the p-type channel region 9a in the nMOSFET region and the insulating film 7 (see FIG. 1B).

As described above, according to the semiconductor device of the present embodiment, the structure in which the insulating film 7 containing p-type impurity atoms is embedded is used for element isolation of the SOI-CMOSFET. Since the insulating film 6 containing no impurities is provided in the region where the pMOS regions 9b and 12b are in contact with each other, fine element isolation of, for example, 0.4 μm or less can be performed.

The p-type channel region 9a of the nMOS region
A high-concentration p-type impurity region is provided in a region where the gate electrode and the insulating film 7 are in contact with each other. it can.

Next, a second embodiment of the present invention will be described with reference to FIG. In this embodiment, the SOI-
FIG. 2 shows a method of manufacturing a CMOSFET.

This manufacturing method uses an SOI substrate in which an insulator layer 2 is formed on a semiconductor substrate 1 and a semiconductor layer 3 also called an SOI layer is formed on the insulator layer 2. A thermal oxide film 4 is formed on the surface of the SOI layer 3 of the SOI substrate by heat treatment, and a silicon nitride film 5 is formed on the thermal oxide film 4 (see FIG. 2A). Then, the silicon nitride film 5, the thermal oxide film 4, and the SOI layer 3 are patterned to form an island-like SOI region 3 (see FIG. 2A). Thereafter, a silicon oxide film 6 is formed on the side surface of the SOI region 3 by oxidation.

Next, only the silicon oxide film 6 formed around the SOI region 3 to be an nMOSFET formation region by a photolithography process and hydrofluoric acid solution etching is removed (see FIG. 2A).

Next, after depositing a BSG film 7 on the entire surface, the silicon nitride film layer 5 is formed by chemical / mechanical polishing (CMP) or the like.
The BSG film 7 is etched back until the surface is exposed (FIG. 2).
(B)).

Thereafter, a heat treatment is performed in a nitrogen or oxygen atmosphere, so that the SOI of the nMOSFET formation region is
Boron is diffused from the BSG film 7 around the region 3, and p ⁺
A mold diffusion region 8 is formed (see FIG. 2B). At this time, around the SOI region of the pMOSFET formation region,
Boron is not diffused from the BSG film 7 because the silicon oxide film 6 is formed. In addition, BS
The resistance of the G film to the hydrofluoric acid-based solution is improved to the same level as or higher than that of the thermal oxide film.

Next, after the silicon nitride film 5 is removed by etching, the p-type channel region 9a is formed in the SOI layer in the nMOSFET formation region by photolithography and ion implantation, and the SOI layer in the pMOSFET formation region is formed.
An n-type channel region 9b is formed in the I layer (FIG. 2C)
reference). Subsequently, the thermal oxide film 4 is removed using a hydrofluoric acid-based solution (see FIG. 2C).

Next, a gate oxide film 10 is formed by thermal oxidation, and then a film 11 of a gate electrode material made of, for example, polycrystalline silicon is deposited (see FIG. 2D).

Next, the gate electrode 11 is formed by patterning the gate electrode material film 11 and the gate oxide film 10, and nM is formed using the gate electrode 11 as a mask.
An n-type impurity (for example, arsenic) is ion-implanted into the OSFET formation region to form the source / drain region 12a.
A source / drain region 12b is formed by ion-implanting a p-type impurity (for example, boron) into the OSFET formation region (see FIG. 1A). At this time, in the p ⁺ -type diffusion layer 8 already formed around the nMOSFET region, the region other than immediately below the gate electrode 11 is inverted to the n ⁺ -type when the source / drain regions are formed. An SOI-CMOSFET having the structure shown in FIG.

It goes without saying that the SOI-CMOSFET manufactured by the manufacturing method of this embodiment also has the same effect as that of the first embodiment.

In the manufacturing method of this embodiment, the heat treatment for forming the p ⁺ -type
Since the resistance of the SG film 7 to a hydrofluoric acid-based solution is improved,
The recession of the element isolation insulating film 7 due to the hydrofluoric acid treatment peculiar to the buried element isolation method and the accompanying “going” at the end of the element isolation region can be largely suppressed.

Next, a third embodiment according to the present invention will be described with reference to FIG.
This will be described with reference to FIG. The semiconductor device according to the present embodiment has S
FIG. 3 is a plan view of the OI-CMOSFET.
FIG. 3B shows a cross section taken along a cutting line XX ′ shown in FIG. 3B.

An insulating layer 32 is formed on a semiconductor substrate 31, and a plurality of annular silicon layers 33a and 33b formed of an SOI layer are provided on the insulating layer 32.
In a region surrounded by these annular silicon layers 33a and 33b, an island-like silicon layer 33c formed from an SOI layer for forming one or more nMOSFETs is provided.
_1, and for forming a pMOSFET, silicon layer 33c ₂ island formed from the SOI layer is provided.

An insulating side wall 37 made of, for example, SiO ₂ is provided on each side surface of the ring-shaped and island-shaped silicon layers 33a, 33b, 33c ₁ and 33c ₂ .
Further, an annular silicon layer 33a and an annular silicon layer 33b
The groove between the is embedded polycrystalline silicon layer 38 with no impurity doped, p-type in the grooves between the island-shaped silicon layer 33c ₁ and the annular silicon layer 33a for forming the nMOSFET Is doped with a polycrystalline silicon layer 38a doped with
Polycrystalline silicon layer 38b which n-type impurities are doped is embedded in a groove between the island-shaped silicon layer 33c ₂ and the circular silicon layer 33b to form the. The surfaces of these polycrystalline silicon layers 38, 38a, 38b are insulating films, for example, silicon oxide films 40, 40a, 40b.
Each is covered by.

The nMO of the island-shaped silicon layer 33c ₁ is
A gate electrode 44a made of n-type polycrystalline silicon is formed in the SFET formation region via a gate insulating film 42,
An n-type source / drain region 46a is formed so as to sandwich this gate electrode 44a. On the other hand, the island pMOSFET formation region of the silicon layer 33c ₂ of formed gate electrode 44b made of p-type polycrystalline silicon through a gate insulating film 42, p-type source and drain of so as to sandwich the gate electrode 44b An area 46b is formed.

The silicon layer 38a surrounding the nMOSFET formation region is provided with a contact 49 via a silicon oxide film 40a, so that an arbitrary voltage can be applied. In addition, pMOSFET
Although not shown, the silicon layer 38b surrounding the formation region is also provided with a contact via a silicon oxide film 40b, so that an arbitrary voltage can be applied.

As described above, according to the semiconductor device of the present embodiment, the SOI region 3 where the transistor is formed
The conductive films 38a and 38b are buried around the 3c ₁ and 33c ₂ and an arbitrary voltage can be applied to these conductive films 38a and 38b. The generation of hump can be suppressed, and the leakage current generated at the interface between silicon and the insulating film at the end and bottom of the transistor formation region can be reduced.

Next, a fourth embodiment according to the present invention will be described with reference to FIG.
This will be described with reference to FIG. This embodiment is different from the S shown in FIG.
This is a method for manufacturing an OI-CMOSFET, and the manufacturing process is shown in FIG.

First, an insulator layer 32 is formed on a semiconductor substrate 31.
After sequentially forming the SOI layer 33, the surface of the SOI layer 33 is oxidized to form a SiO ₂ film 34,
An oxidation-resistant silicon nitride film 35 is deposited on the O ₂ film 34 (see FIG. 4A).

Next, the silicon nitride film 35 and the SiO 2 film are formed by photolithography and anisotropic etching such as RIE.
By patterning the _two films 34 and the SOI layer 33, an annular silicon layer 33a as shown in FIG.
33b and a plurality of island-shaped silicon layers existing in a region surrounded by the annular silicon layers 33a and 33b (see FIG. 4B).

Subsequently, the SiO ₂ film 3 is formed on the side surfaces of the SOI layers 33a, 33b, 33c divided by thermal oxidation.
7 (see FIG. 4C). Thereafter, a polycrystalline silicon film 38 is deposited on the entire surface, and the above-described annular silicon layer 33 is formed.
A groove between the a, 33b and the island-shaped silicon layer 33c is buried (see FIG. 4C).

Next, the polycrystalline silicon film deposited on the entire surface is polished and flattened using a chemical mechanical polishing (CMp) method, and then thermally oxidized to form a silicon oxide film on the surface of the polycrystalline silicon film 38. 40, 40a, and 40b are formed (see FIG. 4D).

Next, after removing the silicon nitride film 35 by using a CDE (Chemical Dry Etching) method or the like, the nMOSFET formation region in the island-like silicon layer 33c is formed by using a photolithography technique and an ion implantation method. the diffusion layer 33c ₁ of p-type formed by implanting boron,
The pMOSFET formation region selectively formed diffusion layer 33c ₂ of n-type by implanting phosphorus (FIG. 4
(E)). When these diffusion layers 33c ₁ and 33c ₂ are formed, boron is introduced into the polycrystalline silicon film 38 embedded in the region surrounded by the annular silicon layer 33a, so that the p-type polycrystalline silicon film 38a is formed. The polycrystalline silicon film 38 buried in the region surrounded by the annular silicon layer 33b is converted into an n-type polycrystalline silicon film 38b by introducing phosphorus (FIG. 4).
(E)).

Next, after removing the SiO ₂ film 34 by isotropic etching, a gate oxide film 42 is formed on the surfaces of the silicon layers 33c ₁ and 33c ₂ by thermal oxidation again. Deposit a film (not shown). Then, an n-type impurity is introduced into the polycrystalline silicon film on the nMOSFET formation region and a p-type impurity is introduced into the polycrystalline silicon film on the pMOSFET formation region using photolithography and ion implantation, and patterning is performed. , Gate electrode 46a and gate electrode 46
b is formed (see FIG. 1A). Subsequently, arsenic is ion-implanted into the nMOSFET formation region and boron is ion-implanted into the pMOSFET formation region by using these gate electrodes 46a and 46b as masks, so that the n-type source / drain regions 4 are formed.
6a and p-type source / drain regions 46b are formed (see FIG. 1A).

It goes without saying that the semiconductor device manufactured by the manufacturing method of this embodiment also has the same effect as that of the third embodiment.

Next, a fifth embodiment of the present invention will be described with reference to FIG. The semiconductor device according to this embodiment has an SOI
FIG. 5B shows a plan view of a −CMOSFET, and FIG. 5A shows a cross section taken along a cutting line YY ′ shown in FIG. 5B.

On a semiconductor substrate 51, an island-shaped n-type polycrystalline silicon layer 53a and an island-shaped p-type polycrystalline silicon layer 53b are formed via an insulating film 52. A silicon oxide film 66 is provided on the side surfaces of these polycrystalline silicon layers 53a and 53b. On these polycrystalline silicon layers 53a and 53b, annular silicon layers (hereinafter also referred to as SOI layers) 55a and 55b are formed via an insulating film 54. This is the region surrounded by the annular SOI layer 55a 1 or more silicon layer 55c ₁ island for forming the nMOSFET is provided an annular SOI layer 55
silicon layer 55c ₂ island for forming one or more pMOSFET is provided in a region surrounded by b. These annular SOI layer 55a, a silicon oxide film 64 on each side of 55b and the polycrystalline silicon layer 55c ₁ of the island, 55c ₂ are provided.

Then, the annular SOI layer 55a and the annular SOI
Between the I layer 55b, bottom polysilicon film 68 which impurities are not doped is embedded in a groove the surface of the insulating film 52, the island-shaped silicon layer 55c ₁ and the annular for forming the nMOSFET SOI The groove between the layer 55a and p
Polycrystalline silicon layer 68a that type impurities are doped is embedded, the grooves between the island-shaped silicon layer 55c ₂ and the circular SOI layer 55b for forming a pMOSFET n-type impurities are doped A polycrystalline silicon layer 68b is embedded.

These polycrystalline silicon layers 68, 68a,
68b is covered with silicon oxide films 70, 70a, 70b. Further on the silicon layer 55c ₁ of the nMOSFET formation region is a gate electrode 74a is formed of polycrystalline silicon of the n-type through the gate insulating film 72, the gate insulating film 72 is formed on the silicon layer 55c ₂ of the pMOSFET formation region A gate electrode 74b made of p-type polycrystalline silicon is formed therebetween. And the SOI layer 55c ₁ on both sides of the gate electrode 74a n-type source and drain regions 76a are formed, p-type source and drain regions 76b in the SOI layer 55c ₂ on both sides of the gate electrode 74b is formed .

A contact 79 is provided on the silicon layer 68a surrounding the nMOSFET formation region via a silicon oxide film 70a, so that an arbitrary voltage can be applied. Since this applied voltage is transmitted to the conductive film 53a via the silicon layer 68a, an arbitrary voltage can be applied to the side and bottom surfaces of the nMOSFET.

Although not shown, the silicon layer 68b surrounding the pMOSFET formation region is also provided with a contact via a silicon oxide film 70b, so that an arbitrary voltage can be applied. Since the applied voltage is transmitted to the conductive film 53b via the silicon layer 68b, an arbitrary voltage can be applied to the side and bottom surfaces of the pMOSFET.

As described above, according to the semiconductor device of the present embodiment, it is possible to apply an arbitrary voltage to the side surface and the bottom surface of the transistor region, and to suppress "hump" caused by the end of the transistor region. And the leakage current due to the interface between the silicon and the insulating film at the end and bottom of the transistor formation region can be reduced.

Next, a sixth embodiment according to the present invention will be described with reference to FIG.
This will be described with reference to FIG. This embodiment is a method for manufacturing the SOI-cMOSFET shown in FIG. 5, and FIGS. 6 and 7 show the manufacturing steps.

First, the semiconductor substrate 51 and the silicon substrate 5
5 is bonded to a substrate on which a silicon oxide film 54, a polycrystalline silicon film 53, and a silicon oxide film 52 are formed, and the silicon substrate 55 is polished or the like to a silicon layer (SOI layer) 55 of about several hundred nm. (See FIG. 6A).

Next, after a thermal oxide film 57 is formed on the silicon layer 55, a silicon nitride film 58 is deposited on the thermal oxide film 57 (see FIG. 6B).

Subsequently, the silicon nitride film 58, the silicon oxide film 57, the SOI layer 55, and the silicon oxide film 54 are patterned by using a photolithography technique and anisotropic etching such as RIE, so that the annular SOI layer 5 is formed.
5a, 55b and these annular SOI layers 55a, 55
This is divided into a plurality of island-shaped SOI layers 55c surrounded by b (see FIG. 6C). At this time, the SOI layer 55a and the SOI
A groove 60a is formed between the SOI layer 55b and the layer 55b.
a between the SOI layer 55c and the SOI layer 55c
A groove 60b is formed between the OI layers 55c.
(C)).

Next, after forming a resist pattern 62 made of a photoresist having an opening on the groove 60a,
By using anisotropic etching, the annular SOI layers 55a and 55a
The trench 60a formed between the trenches 5b is etched again, and the polycrystalline silicon film 53 existing at the bottom of the trench 60a is patterned to be divided into island-like polycrystalline silicon layers 53a and 53b (see FIG. 6D). ).

Next, after removing the resist pattern 62,
Polycrystalline silicon film 5 exposed in trenches 60a and 60b
3 and the SOI layers 55a, 55b, 55c are etched using an isotropic etching method.
The side surfaces of the layers 55a, 55b, 55c and the side surfaces of the polycrystalline silicon layers 53a, 53b are retracted from the grooves 60a, 60b, but the polycrystalline silicon layers 53a, 53b existing at the bottom in the grooves 60b remain (FIG. e)).

By performing the thermal oxidation treatment, the SOI layer 5
After silicon oxide films 64 and 66 are formed on the exposed side surfaces of 5a, 55b and 55c, and on the exposed side surfaces and upper surface of polycrystalline silicon layers 53a and 53b, grooves are formed by anisotropic etching. The silicon oxide film formed on the bottom of 60b is removed (see FIG. 7A). Subsequently, a polycrystalline silicon film 68 is deposited on the entire surface (see FIG. 7A).

Next, the polycrystalline silicon film 68 is polished and flattened by using the CMp method, and then a thermal oxidation process is performed so that the silicon oxide film 7 is formed on the surface of the polycrystalline silicon film 68.
0, 70a, and 70b are formed (see FIG. 7B).

Next, after the silicon nitride film 58 is removed by the CDE method or the like, the nMOS of the island-like silicon layer 55c is removed by the photolithography technique and the ion implantation method.
Impurities of the p-type in the FET region, selectively forming a p-type diffusion layer 55c ₁ implanted example boron, pMOS
The FET forming region are selectively formed n-type impurity, for example, a diffusion layer 55c ₂ of the n-type implantation of phosphorus (Figure 7
(C)). When forming the diffusion layers 55c ₁ and 55c ₂ , a p-type impurity is introduced into the polycrystalline silicon layer 68 buried in a region surrounded by the annular silicon layer 55a to form a p-type polycrystalline silicon layer. 68a, an n-type impurity layer is introduced into the polycrystalline silicon layer 68 embedded in the region surrounded by the annular silicon layer 55b to be converted into an n-type polycrystalline silicon layer 68b into a conductive film ( FIG.
(C)). Note that no impurity is introduced into the polycrystalline silicon film 68 embedded in the groove 60a.

Next, after removing the silicon oxide film 57 using isotropic etching, a thermal oxidation process is performed to form a gate oxide film 72 on the surfaces of the SOI layers 55c ₁ and 55c _2.
Is formed (see FIG. 5A). Subsequently, after a polycrystalline silicon film is deposited on the entire surface, impurities are selectively introduced into the polycrystalline silicon film by using a photolithography technique and an ion implantation method, and the nMOSFET formation region is formed by patterning the polycrystalline silicon film. A gate electrode 74a made of n-type polycrystalline silicon, and a gate electrode 7 made of p-type polycrystalline silicon in a pMOSFET formation region.
4b is formed (see FIG. 5A). Thereafter, arsenic is ion-implanted using the gate electrode 74a as a mask by photolithography, thereby forming the gate electrode 74a.
The gate electrode 74b with the sides of the n-type SOI layer 55c ₁ source and drain regions 76a is selectively formed
The p-type source and drain regions 76b is selectively formed on the SOI layer 55c ₂ on both sides of the gate electrode 74b by implanting boron with a mask (FIGS. 5 (a)
reference).

As described above, it goes without saying that the semiconductor device manufactured by the manufacturing method of the present embodiment also has the same effect as the semiconductor device of the fifth embodiment shown in FIG.

[0064]

As described above, according to the present invention, the occurrence of humps in static characteristics can be suppressed as much as possible.

[Brief description of the drawings]

FIG. 1 is a sectional view showing the configuration of a first embodiment of the present invention.

FIG. 2 is a sectional view of a manufacturing process according to a second embodiment of the present invention.

FIG. 3 is a configuration diagram showing a configuration of a third embodiment of the present invention.

FIG. 4 is a sectional view showing a manufacturing process according to a fourth embodiment of the present invention.

FIG. 5 is a configuration diagram showing a configuration of a fifth embodiment of the present invention.

FIG. 6 is a sectional view showing a manufacturing process according to a sixth embodiment of the present invention.

FIG. 7 is a sectional view showing a manufacturing process according to a sixth embodiment of the present invention.

FIG. 8 is a cross-sectional view illustrating a configuration of a conventional SOI-CMOSFET.

FIG. 9 is a cross-sectional view showing the configuration of another conventional SOI-CMOSFET.

FIG. 10 is a graph showing static characteristics of a MOSFET.

FIG. 11 is a graph showing static characteristics of a conventional SOI-CMOSFET.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Insulator layer 3 SOI layer 4 Thermal oxide film 5 Silicon nitride film 6 Silicon oxide film 7 BSG film 8 P ⁺ type diffusion region 9a, 9b Channel region 10 Gate insulating film 11 Polycrystalline silicon film (gate electrode) 12a, 12b Source / drain region 31 Semiconductor substrate 32 Insulator layer 33 SOI layer 33a, 33b, 33c SOI layer 34 Silicon oxide film 35 Silicon nitride film 37 Silicon oxide film 38 Polycrystalline silicon film 38a P-type polycrystalline silicon layer 38b n Type polycrystalline silicon layers 40, 40a, 40b silicon oxide films 42 gate oxide films 44a, 44b gate electrodes 46a, 46b source / drain regions 49 contacts 51 semiconductor substrate 52 insulating films 53a, 53b polycrystalline silicon layers 54 insulating films 55a, 55b , 55c ₁ , 55c ₂ SO I layer 57 Thermal oxide film 58 Silicon nitride film 60a, 60b Groove 62 Resist pattern 64 Silicon oxide film 66 Silicon oxide film 68 Polycrystalline silicon film 70, 70a, 70b Silicon oxide film 72 Gate insulating film 74a, 74b Gate electrode 76a, 76b Source / drain region 79 Contact 101 Semiconductor substrate 102 Insulator layer 103 Device isolation region 107 Device isolation insulating film 109a, 109b Channel region 110 Gate insulating film 111 Gate electrode 112a, 112b Source / drain region 120, 130, 140 Channel region end

Claims (6)

[Claims] An insulating layer formed on the substrate; a p-type semiconductor layer provided on the insulating layer; and an insulating layer provided on the insulating layer and insulated from the p-type semiconductor layer. An n-type semiconductor layer that is insulated and separated by a film; an n-type source region and a drain region that are formed separately from the p-type semiconductor layer; and a p-type semiconductor that is formed separately from the n-type semiconductor layer. A source region and a drain region of a type, a first channel region formed in the p-type semiconductor layer between the source region of the n-type and the drain region of the n-type, A second channel region formed in the n-type semiconductor layer between the p-type drain region; a first gate electrode formed on the first channel region; and a second channel A second gate electrode formed on the region; Wherein p end of the gate width direction of the first channel region
A p-type diffusion region having a higher concentration than the p-type semiconductor layer formed in the p-type semiconductor layer. 2. An SO having a silicon layer formed on an insulator layer.
Forming a mask layer on the silicon layer of the I-substrate; forming first and second island-shaped regions by patterning the mask layer and the silicon layer; Forming a first insulating film only on the side surface of the silicon layer in the region, and embedding a second insulating film containing p-type impurity atoms around the first and second island regions. Forming a p-type diffusion region by performing a heat treatment to diffuse the p-type impurity atoms from the second insulating film to a side surface of the silicon layer in the first island-like region; Forming a n-channel and a p-channel MOSFET in the first and second island regions, respectively. 3. An insulator layer formed on a substrate, an annular first semiconductor layer formed on the insulator layer, and an insulator layer on the insulator layer inside the first semiconductor layer. First
An island-shaped second semiconductor layer formed separately from the first semiconductor layer; a first insulating film formed on a side surface of each of the first semiconductor layer and the second semiconductor layer; A conductor film formed on the insulator layer in a region surrounded by the first semiconductor layer and the second semiconductor layer so as to bury the enclosed region; and covering an upper surface of the conductor film. A second insulating film formed as described above; a first conductivity type source region and a drain region separately formed in the second semiconductor layer; and a second conductive film between the source region and the drain region. A semiconductor device comprising: a channel region of a second conductivity type different from the first conductivity type formed in the semiconductor layer; and a gate electrode formed on the channel region. 4. An SO having a silicon layer formed on an insulator layer
Forming a mask layer on the silicon layer on the I-substrate; and forming an annular region by patterning the mask layer and the silicon layer and an island-like region separated from the annular region inside the annular region. Forming a region, forming a first insulating film on each of a side surface of the silicon layer in the ring-shaped region and a side surface of the silicon layer in the island-shaped region, and forming the ring-shaped region and the island-shaped region. Embedding a conductive film on the insulator layer in a region surrounded by the region; and forming a second insulating film so as to cover the conductive film. Semiconductor device manufacturing method. 5. A first insulator layer formed on a substrate, an island-shaped first conductor layer formed on the first insulator layer, and on the first conductor layer. An annular first semiconductor layer formed via a second insulator layer on the first conductor layer inside the first semiconductor layer via the second insulator layer An island-shaped second semiconductor layer formed separately from the first semiconductor layer; a first insulating film formed on a side surface of the first conductor layer; A second insulating film formed on each side surface of the semiconductor layer; and a first conductive layer formed on the first conductor layer in a region surrounded by the first semiconductor layer and the second semiconductor layer. A second conductor layer electrically connected to the body layer and formed so as to bury the enclosed region; and a second conductor layer formed to cover the upper surface of the second conductor layer. A third insulating film; a first conductive type source region and a drain region formed separately from the second semiconductor layer; and a second conductive layer formed between the source region and the drain region. A channel region of a second conductivity type different from the first conductivity type, and a gate electrode formed on the channel region. 6. A step of forming a mask layer on a semiconductor layer of a substrate on which a first insulator layer, a first conductor layer, a second insulator layer, and a semiconductor layer are sequentially formed. Forming a ring-shaped region and an island-shaped region separated from the ring-shaped region inside the ring-shaped region by patterning the mask layer, the semiconductor layer, and a second insulator layer; Forming a first insulating film on each of a side surface of the semiconductor layer in an annular region and a side surface of the semiconductor layer in the island region; and forming a first insulating film on a region surrounded by the annular region and the island region. Embedding the enclosed region with a second conductor layer on the first conductor layer so as to be electrically connected to the first conductor layer; Forming a second insulating film so as to cover it. The method of manufacturing a semiconductor device to be.