KR890004969B1 - Semiconductor device manufacturing method - Google Patents

Abstract

The semiconductor has a microbridge and oxidized, nitrated insulator and microbridge layers forming multi-layered stuctures. The manufacturing method comprises (1) forming at least one insulation layer of a certain shape on a substrate ; (2) forming a continuous semiconductor layer on said substrate and first insulation layer ; (3) forming an island region by lithography on said semiconducting layer and first insulation layer ; (4) forming a microbridge by eliminating one side of semiconducting layer ; (5) forming the second insulation layer on the surface of the microbridge.

Description

Manufacturing Method of Semiconductor Device

1 (a)-1 (e) are sectional drawing and a perspective view which show the process in 1st Example of this invention.

2 (a) to 2 (e) are cross-sectional views and perspective views showing the process in the second embodiment of the present invention.

3 (a) to 3 (b) are sectional views showing the process in the third embodiment of the present invention.

4 (a) to 4 (o) are a sectional view and a perspective view showing a process in a fourth embodiment of the present invention.

4 (p) to 4 (q) are sectional views and a perspective view showing a process in a fifth embodiment of the present invention.

5 (a) to 5 (f) are sectional views and perspective views showing a process in a sixth embodiment of the present invention.

6 is a cross-sectional view showing a semiconductor device in accordance with an eighth embodiment of the present invention.

7 is a cross-sectional view showing a semiconductor device in accordance with a ninth embodiment of the present invention.

8A is a cross-sectional view showing a conventional multilayer integrated circuit.

8 (b) is a cross-sectional view showing a conventional joint gate CMOS.

9 is a conceptual diagram illustrating a joint gate CMOS.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, in particular, having a good interface characteristic such that a laminated structure with a semiconductor insulator can be used as a channel region and a gate insulating film of an LSI MOSFET. A method for manufacturing a semiconductor device capable of forming an SOI structure.

The development of electronic calculators and communication devices is rapid, and in recent years, attempts have been made to realize more advanced functions by assembling a large number of electronic calculators into a network using a communication network. It became. There is a strong sense of the opening of the information age. Therefore, the development of these devices is now a request of the times, and the basic components are very demanding for the high speed and the high integration of large scale integrated circuits (LSI). Until now, the main means for meeting this demand has been the miniaturization of devices. However, in the future, it is considered that a stacked integrated circuit or a new structure transistor using a silicon on insulator (SOI) structure will be the main role. One example of these devices is shown in FIGS. 8 (a) and 8 (b).

FIG. 8 (a) is a cross-sectional view of a stacked integrated circuit, and FIG. 8 (b) is IEEE Electron Devices Letters, Vo1. By J.F.Gibbons and K.F.Lee. EDL-1, No.6 (joint gate CMOS, one of the new structure transistors presented by the paper "One-Gate-Wide CMOS Inverter on Laser-Recrystallized Polysilicon" described in June, 1980 (pp117-118) One-gate-wide CMOS inverters are all based on MOS type field effect transistors (MOSFETs) formed in Si layer 6 on the insulating film 5. In FIG. The portion enclosed by the dashed lines is the MOSFET, and in the joint gate CMOS, as shown in the conceptual diagram of FIG. 9, two upper and lower MOSFETs share one gate electrode 1. ) MOSFET (CMOS).

Conventional SOI structure formation techniques include a method of forming single crystal Si on an insulating film or an insulating substrate, and a method of forming an insulator layer in the single crystal Si substrate. As an example of electrons, polycrystalline Si deposited on an insulating film, such as SiO ₂ , is crystallized by laser annealing, electron beam annealing, strip heater annealing, or the like. There is a technology to make up.

As the latter example, a technique of forming a damage layer in a substrate by proton implantation and selectively oxidizing the damage layer that is easy to oxidize, or by Si ion implantation by oxygen ion implantation during the like techniques to form a SiO ₂ layer. At present, these techniques enable the formation of a good crystalline SOI capable of forming a MOSFET. However, the SOI formed by any method has poor electrical characteristics at the interface between the Si layer 6 and the insulating film 5. Therefore, when the MOSFET is formed as shown in FIG. 8 (a), the interface 32 between the insulating film 5 and the Si layer 6 formed thereon becomes a path for leakage current between the source 2 and the drain 3, and the performance of the device is very unsatisfactory. It becomes one. Therefore, in order to avoid this problem, a method of introducing impurities into the interface 32 by ion implantation to form a stopper is devised, so that a good result can be obtained.

However, when the bottom insulating film 5 such as the MOSFET of the upper layer of the joint gate CMOS shown in FIG. 8 (b) is used as the thin gate insulating film 4 having a thickness of 5 to 100 nm, the bottom insulating film 5 and the Si layer 6 formed thereon and Since the channel is formed at the interface 33 of, the above problem becomes more serious, the method does not become satisfactory, and the problem has been solved.

In FIGS. 8A, 8B, and 9, reference numeral 1 denotes a gate electrode, 2 a source region, 3 a drain region, 4 a gate insulating film, 5 a bottom insulating film, and 6 The Si layer, 7 is an Si substrate, and 32 and 33 are interfaces between the bottom insulating film and the Si layer.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned difficulties of the prior art and to provide a method for producing a semiconductor device having an SOI structure having a good interface property between the insulating film and the semiconductor layer to the extent that the bottom insulating film can be used as the gate insulating film.

In order to achieve the above object, a method of manufacturing a semiconductor device of the present invention is a bridge-type connecting bar or one-side suported bar (hereinafter referred to as a semiconductor). Microbridges are formed, and then oxidized or nitrided, whereby the microbridges form an insulating film on at least an upper or lower tight portion to form a multilayered structure of a semiconductor and an insulator. Each process has to do. Moreover, the manufacturing method of the semiconductor device of this invention is a process of (i) forming at least 1st 1st insulating film of a predetermined shape on a board | substrate, (ii) forming a continuous semiconductor film on said board | substrate and on a said 1st insulating film. And (i) at least one predetermined shape comprising a semiconductor film continuously present on the substrate and on the first insulating film, and the first insulating film under the semiconductor film. A step of forming by chromatography, (i) removing at least the semiconductor film side of the first insulating film in the island-like region, and forming a microbridge that becomes the semiconductor film, and (iii) exposing the microbridge. It has a process of forming a 2nd insulating film on the surface.

In the manufacturing method of the semiconductor device of the present invention, when the MOSFET is to be manufactured well, (i) after the completion of the step (i), (i) the MOSFET having the second insulating film as the gate insulating film is the microbridge. What is necessary is just to add the process to form in the inside.

The substrate may be any substrate generally used in a semiconductor device, and is not particularly limited. However, the substrate is required to be a semiconductor substrate when forming an active element such as a substrate MOSFET.

As the second insulating film in the above step, an underlayer film prepared by an oxide forming process such as thermal oxidation or plasma oxidation, or a nitride film prepared by a nitride forming process such as nitriding can be used.

After the said process (iii) is completed, a multilayer microbridge can be formed by repeating the process of providing a 1st insulating film on the said microbridge, and said process (ii)-(iv) at least once.

In the case of using a semiconductor substrate, (i) forming at least one first insulating film of a predetermined shape on the semiconductor substrate, (ii) a semiconductor film continuously present on the semiconductor substrate and on the first insulating film; And lithography forming at least one island-shaped region of a predetermined shape to be the first insulating film under the semiconductor film. (I) Source regions and drains on the semiconductor substrate and the semiconductor film, respectively, by ion implantation. Forming a region, (i) removing the first insulating film in the island-like region to form a microbridge, and further forming a second insulating film on the exposed surface of the microbridge, and (iii) the Forming a gate electrode in a gap portion under the microbridge, by a method of manufacturing a semiconductor device having a MOSFETs can be provided on both sides, and the MOSFETs in this case are self-aligned with each other. In this case, after the step (i) is completed, (i) the step of removing the portion in contact with the source region of the semiconductor substrate to the microbridge, to form a joint gate COMS structure. There is a number.

In any of the above cases, the semiconductor constituting the micro bridge is preferably a single crystal semiconductor for forming an element, and in particular, single crystal Si is common. In addition, the dimension of a microbridge may be determined by the element provided in the microbridge, and what is necessary is just to refer to a general MOS, when providing a MOS. In addition, the height of the microbridge is not particularly limited, but when the gate electrode is provided in the gap below the microbridge, it is preferably 10 µm or less. This is because if it exceeds this, deposition of the gate electrode tends to be difficult.

Thus, for example, silicon (Si) and oxygen (O) are chemically good in phase, and both chemical reactions, that is, oxidation of the Si substrate, in particular, a place where O penetrates into the substrate by diffusion and meets Si. By the oxidation of the structure which forms a Si-O bond at, an SiO ₂ layer / Si structure with extremely good interfacial properties is formed. In other words, (1) There is solid Si without damage at first and oxidizes it to form SiO ₂ film.

② At this point, two points supplied with O by diffusion are conditions for making Si / SiO ₂ system with good interfacial properties. In view of the conventional SOI technology from this point of view, since the method of forming the Si layer on the insulating film does not satisfy? In the original, the method of forming the SiO ₂ layer in the Si substrate introduces O by ion implantation. Not satisfying. Therefore, it is difficult to form a good interface.

The present invention can be said to have been considered as a method of satisfying the conditions of ① and ② according to the above-described consideration of silicon.

Example 1

This embodiment is an example in which a MOSFET is fabricated in a Si layer on an insulator.

As shown in FIG. 1 (a), a SiO ₂ film 8 having a thickness of 7000 kPa was formed on the single crystal Si substrate 7 by CVD (Chemical Vaper Deposition) method, and using a conventional photolithograyhy technique. This was separated into oblong islands. At this time, another insulating film such as Si ₃ N ₄ may be used instead of the Sio ₂ film. In this case, the insulating film has a very high etching rate for the semiconductor film deposited thereon in the following step and may be other than Sio ₂ and Si ₃ N ₄ . In addition, the shape of the island may be circular, square, rectangular, or other suitable shape. A polycrystalline Si film is deposited to a thickness of 3500 kPa by the CVD method, and thereafter, a laser beam is scanned. This single crystallized to obtain a single crystal Si film 9. That is, the SOI structure is formed by the SOI shape technique using the conventional laser annealing. In this case, any conventional SOI technology such as SOI technology by strip heater annealing or SOI technology using solid phase growth of Si may be used. In this embodiment, the entire semiconductor film is single crystallized, but at least the device region is single crystallized and may be polycrystalline. Next, the SOI region was separated into several island regions as shown in Fig. 1 (b) by dipping a photomask and anisotropic dry etching. (Two examples are shown in the drawing.) Next, selective etching of the SiO ₂ film 8 was performed to form a micro bridge 30 of Si as shown in FIG. 1 (c). Here to carry out thermal oxidation in of dry oxygen, and 1000 degrees C, covering the surface with a high quality SiO ₂ film 48 having a thickness of 450Å, and then, the SiO ₂ film 48 on the micro-bridge 30 using a conventional process A MOSFET used for the gate oxide film 4 was produced by a known method. In FIG. 1 (d), a cross-sectional view of the result is shown. Instead of thermal oxidation, plasma oxidation or the like may be used, and this may be replaced with another insulating film such as Si ₃ N ₄ instead of SiO ₂ . Subsequently, when polycrystalline Si is embedded in the gap 31 below the microbridge 30 by a combination of CVD and etching, as shown in FIG. 1 (e), not only the gate electrode 1 in the upper layer but also the gate electrode in the lower layer. 1 is formed.

In FIGS. 1 (d) and 1 (e), reference numerals 2 and 3 denote source and drain regions, respectively.

Example 2

In this embodiment, a MOSFET is fabricated on a Si substrate, and a microbridge is formed of Si thereon to form a MOSFET on the bridge to form a stacked integrated circuit.

First, as shown in FIG. 2, a MOSFET including gate electrode 1, source region 2, drain region 3, and gate insulating film 4 was formed on a Si substrate 7 using a normal process. The SiO ₂ film 8 was deposited to a thickness of about 1.3 mu m by CVD, and then patterned into a rectangle in the same manner as in Example 1 by a known photolithography technique, and on top of that, single crystal Si was deposited by CVD. The film was deposited with a thickness of 3500 GPa, and the deposited Si was single crystallized by scanning with a laser beam to obtain a single crystal Si film 9. In this case, it is not limited to the SOI technology using the laser beam, the SOI technology using the electron beam, the SOI technology using the solid phase growth, and the expectation. Predetermined portions of the rectangular SOI region were now scraped off by etching using a mask to form an island-like region in the shape shown in FIG. 2 (b). However, at this time, the surrounding is satisfied so as to satisfy the condition of d> w / 2 (see also the second (b), d is the thickness of the SiO ₂ film 8 remaining in the shaved region, and w is the width of the uncut SOI region). Specifically, w = 0.8 m and d = 0.8 m. Next, by etching 0.5 mu m of the SiO ₂ film 8 by the well-known isotropic selective etching, a part of the SiO ₂ 8 immediately below the Si film 9 in the SOI structure was removed, and the result shown in FIG. As such, micro bridge 30 of Si was formed. At this time, since the etching depth of the SiO ₂ film 8 does not reach the gate oxide film of the MOSFET on the Si substrate 7, the FET is not damaged. Since d> w / 2, such etching was performed.

Next, as in Example 1, as shown in FIG. 2 (d), a thin SiO ₂ film 48 having a thickness of 450 Å was formed by thermal oxidation, and the SiO ₂ film 48 was then gate oxide film 4. As a MOSFET, a MOSFET was fabricated on a microbridge using a conventional process. It is similar to Example 1 that you may use plasma oxidation and others for oxidizing.

Thereafter, the gap under the micro bridge was filled with SiO ₂ 8 by low pressure CVD, and the entire surface of the substrate was covered with SiO ₂ film 28. Thereafter, although not shown, a multilayer integrated circuit was completed by forming a through hole and forming a wiring using A1. In this embodiment, a semiconductor layer having a different conductivity type is formed in the upper and lower layers, and the CMOS inverter is electrically connected between both gates and one of the high-concentration impurity layers of the MOSFET under one of the high-concentration impurity layers of the upper MOSFET. (inverter) was formed. The connection between the highly concentrated non-gifted regions of the upper and lower layers may also be formed by forming both impurity layers so as to overlap each other in the drain region 3 as shown in FIG. 2 (e) without using wiring. Not to mention. In FIG. 2 (e), the illustration of the SiO ₂ film 48 is omitted.

Example 3

In the process shown in Example 2, the structure shown in Fig. 2E was formed. Thereafter, using a photomask, leaving only the SiO ₂ film 28 of the above micro-bridge, and etching the SiO ₂ film 28 (claim 3 (a) also). Next, as shown in FIG. 3 (b), by using a known selective epitaxial growth method, the single crystal Si film 25 was deposited to the height of the microbridge and planarized only on the region where Si was exposed. If single crystal Si is deposited to the height of the SiO ₂ film 28, a substantially flat structure can be obtained. Then, using the process shown in Example 2, a microbridge was again formed, a MOSFET was formed in the layer, and the structure shown in FIG. 3 (b) was formed. Although not shown in the SiO ₂ film 38 provided on the surface, through holes were formed to perform wiring to complete the three-layer integrated circuit. In this embodiment, however, polycrystalline Si having a high impurity concentration was used instead of the A1 wiring.

The 3 (a) help claim 3 (b) in Fig., Numeral other than 25, and displays the same part help claim 2 (a) degrees to claim 2 (e), also SiO ₂ film 48 is omitted is shown .

Example 4

This embodiment is an example in which a joint gate CMOS is made using the present invention. At this time, both the upper and lower layers of the source drain region were formed by self-aligning the gate electrode.

As shown in FIG. 4 (a), an n-type conductive single crystal Si substrate 7 is prepared, and boron ion implantation 11 using a mask 10 as a photoresist is performed thereon, whereby P ⁺ type Zone 2 was formed. This region finally becomes the source region of the lower MOSFET. Next, as shown in FIG. 4 (b), by using a conventional SOI technique using the same laser annealing as in Example 1, the SOI structure was formed so as to overlap with the above P ⁺ type region. At this time, it is the same as that of Example 1 which may transfer another SOI technique. In addition, boron ions were implanted into the deposited single crystal Si film 9 to obtain a P-type conductivity type. 8 is a SiO ₂ film. Subsequently, the SOI region was separated into several islands as shown in FIG. 1 (b) of the first embodiment by applying a mask to the etching. Next, a Si ₃ N ₄ film 14 was deposited on the surface of the substrate by a CVD method, etched using a mask, and formed into a shape as shown in FIG. 4 (c). Only dogs are shown). The Si ₃ N ₄ film 14 serves as a mask for ion implantation for forming a source and a drain, and is used for positioning the gate electrode. That is, first, boron was injected to the acceleration energy of 500 KeV and 200 KeV, and P ⁺ type regions 2 and 3 were formed as shown in FIG. 4 (d). Before the formation of the SOI structure placed to form on the substrate in advance overlap the P ⁺ type region P ⁺ type region 2 as the source region 2 of the lower MOSFET of the joint gate CMOS, yet P ⁺ type region of one is the drain of the lower MOSFET The area 3 is used. Subsequently, phosphorus ions were implanted therein with an acceleration energy of 200 KeV, and n ⁺ -type conductive regions 12 and 13 were formed in the deposited Si film 9 as shown in FIG. 4 (e). As the source region 12 of the MOSFET formed in the upper layer by the n ⁺ type region 12 in contact with the lower source region 2, the n ⁺ type region 13 in contact with the drain region 3 in the lower layer is used as the drain region 13 in the upper layer. Next, as shown in FIG. 4 (f), the photoresist 10 was applied to the surface of the substrate, and the mask 10 was formed as shown in the figure by squeezing a pattern using a photolithography technique. Selective etching of the Si ₃ N ₄ film was performed thereon to remove the Si ₃ N ₄ film around the SOI island, and then the resist 10 was removed to obtain the form shown in FIG. 4 (g).

By the way, when a sample is exposed in a plasma, the surface of a sample is obtained by the boundary area called a sheath. In sheaths, since positive ions are accelerated toward the sample, when plasma etching is performed in a region where the gas pressure is low enough that the average free stroke of the ions becomes equal to or greater than the thickness of the sheath, it is perpendicular to the object surface. The etching proceeds only in the phosphorus direction. Using this property, the SiO ₂ film 8, which is the sample, is selectively etched, leaving behind the shaded portion of the Si ₃ N ₄ film 14, as shown in FIG. 4 (h), and the SiO ₂ film 8 is cut to Si. Micro bridges are formed. The remaining SiO ₂ film 8 is a dummy gate 17. Next, the Si ₃ N ₄ film 14 was removed by selective etching, and then, as shown in FIG. 4 (i), the sample surface was thermally oxidized in the same manner as in Example 1 to form a SiO ₂ film 48. Covered with

Next, as shown in FIG. 4 (j), when the Si ₃ N ₄ films 44 and 16 are deposited by the CVD method, and then anisotropic etching 15 is performed, the amount of Si ₃ N charged under the micro bridge is shown. ₄ film 16 is removed, and the Si ₃ N ₄ film 44 is removed. Subsequently, the selective etching of the SiO ₂ film is performed to remove the SiO ₂ film 17 under the micro bridge. Then, by thermal oxidation in the same manner as described above, as shown in Fig. 4 (k), a SiO ₂ film having a thickness of 250 GPa was formed on the bottom surface of the microbridge and the substrate surface immediately below it. This is the gate oxide film 4 of this joint gate CMOS. Thereafter, in the previous step shown in FIG. 4 (j), the Si ₃ N ₄ film 16 was deposited and anisotropically etched under the microbridge, and deposited by CVD followed by anisotropic etching. As shown in Fig. 4 (k), the polycrystalline Si film 1 having a high impurity concentration was filled under the micro bridge. This is the gate electrode 1 of the joint gate CMOS.

With the above, the main part of the device was completed.

Then, processing is performed to enable electrical connection to the gate electrodes 1 and the sources 12 and 2 of the upper and lower layers, respectively. First, as shown in FIG. 4 (l), photoresist 18 is applied to the surface of the sample. Using photolithography technology, the photoresist in the region enclosed by the dashed-dotted line in FIG. 4 (l) is removed, and etching of the sample surface is performed until the gate electrode 1 embedded under the micro bridge is exposed. Do it. After that, when the resist 18 is removed, the sample has a shape shown in Fig. 4 (m) and Fig. 4 (n). As can be seen from the top view of Fig. 4 (n), the gate electrode 1 is exposed in a large shape. This is because, as shown in Fig. 4 (h), the mask 14 at the time of forming the dummy gate had such a shape.

Since wiring is carried out in this large phase region, the contact resistance can be reduced. However, it goes without saying that the shape of the gate electrode 1 does not need to be formed in such a large shape that the end of the gate electrode 1 has a problem even if the contact resistance of the gate is somewhat large. Since the mask of the dummy gate is also a mask for ion implantation for forming the source and the drain, the shape of the source drain tip also naturally matches the shape of the gate electrode. In this process, the exposure of a part of the gate electrode 1 and the separation of the source 12 of the upper MOSFET and the source 2 of the lower MOSFET are completed. Finally, as shown in FIG. 4 (o), the SiO ₂ film 28 is deposited by a bias sputter method, the contact hole is opened by etching using a mask, and the wiring is made using A1. This completes the joint gate CMOS. It goes without saying that the joint gate CMOS in which the conductivity type shown in this embodiment is replaced with n and p can be made in the same process.

In Fig. 4 (o), reference numeral 19 is a gate electrode terminal, 20 is a source electrode terminal of the upper MOSFET, and 21 is a source electrode terminal of the lower MOSFET.

Example 5

This embodiment is a simplified type of Example 4. In other words, when it is necessary to suppress the parasitic capacitance between the source and the drain and the gate with a very small amount, the device of the fourth embodiment is necessary. On the other hand, when this is not a problem, the device of the present embodiment Become valid.

By the same method as the process described in Example 4, the structure shown in FIG. 4 (e) was formed. Next, the Si ₃ N ₄ film 14 was taken out by the selective etching method similar to Example 4, and then, the SiO ₂ film 8 was removed using another selective etching method. By thermally oxidizing this, a 250 막 SiO ₂ film 28 was formed on the sample surface. Next, the polycrystalline Si film 22 having a high impurity concentration was removed by the low pressure CVD method on the substrate surface, on the micro bridge, and under the micro bridge. Here, in Example 4, similarly to Fig. 4 (l) and Fig. 4 (m), the diagram of the resist, partial removal thereof, and etching using the resist as a mask are performed to obtain the source MOSFET. 12 and source 2 of the lower MOSFET were separated (FIG. 4 (q)). Thereafter, similarly to the SiO ₂ film 28 of FIG. 4 (o) in Example 4, the sample is covered with a passivation film, a contact hole is opened therein, and wiring is performed next to the joint gate CMOS. Is completed. It goes without saying that in this embodiment, the conductive CMOS can be made into the same process by replacing the n and p joints.

Example 6

In the process shown in Example 4, the ion implantation 11 shown in FIG. 4 (a) is omitted, and the conductivity type of the deposited Si film 9 is selected in the same manner as the conductivity type of the substrate 7, and the ion for source drain formation is selected. A MOSFET capable of simultaneously driving the upper and lower channels by one gate 1 by omitting the step of separating the source regions 12 and 2 in the upper and lower layers by selecting ions which form the same conductivity type for implantation. Made. This is equivalent to doubling the channel width without increasing the parasitic capacitance of the source drain as compared to the conventional MOSFET, thereby obtaining a transconductance gm of twice the value.

Example 7

In this embodiment, one of the MOSFETs of the novel structure described above is made using the present invention.

By the same method as the process described in Example 1, the structure shown in FIG. 1 (c) is formed, and the ion-implanted Si film 9 has the same conductivity type as that of the substrate 7 by thermal implantation, which is thermally oxidized. Was covered with an oxide film 48 having a thickness of 250 GPa. Next, a polycrystalline Si film 22 having a high impurity concentration was deposited by CVD method, and a photomask 10 was formed thereon as shown in FIG. 5 (a). By anisotropic etching here, the polycrystalline Si film 2 was left only under the mask, 10, and under the micro bridge. Next, by anisotropic etching using the sheath potential used to form the dummy gate of Example 4, the shaded portion of the mask 10 is removed as shown in FIG. The polycrystalline Si film 22 was removed. Subsequently, the mask 10 is removed, and as shown in FIG. 5 (c) and FIG. 5 (d), a 500 kV oxide film 48 is formed on the surface of Si by thermal oxidation, and the polycrystalline Si film 22 is masked. The source 2 and the drain 3 were formed in the micro bridge by ion implantation. In the case where the parasitic capacitance between the source 2, the drain 3 and the gate electrode 1 is not a problem, a conventional anisotropic etching may be used instead of the etching using a sheath electric field. In this case, all of the polycrystalline Si films 22 under the microbridge remain, and the completed form of the device is as shown in Figs. 5 (e) and 5 (f). In this embodiment, thermal oxidation is used, but instead, plasma oxidation, magnetic field microwave plasma CVD, or the like may be used.

In Figs. 5A to 5F, reference numeral 4 denotes a gate insulating film, 9 denotes a single crystal Si film, 19 denotes a gate electrode terminal, 23 denotes a source electrode terminal, and 24 denotes a drain electrode terminal.

Example 8

In the process of Example 7, before the ion implantation for forming the source 2 and the drain 3 in the microbridge, the ions which become of the same conductivity type as the source 2 and the drain 3 of the microbridge can reach the substrate 7. The process of implanting with high acceleration energy was inserted and the MOSFET of the structure shown in FIG. 6 was formed. With this arrangement, the transmission conductance gm could be three times or more in this embodiment.

In FIG. 6, each code | symbol shows the part same as FIG. 5 (a)-5 (f).

Example 9

In the process of Example 7, instead of the process of making the conductivity type of the deposited Si film 9 the same as the substrate 7 by ion implantation, ions are selected by injecting the conductivity type of the deposited film 9 inversely to the conductivity type of the substrate 7. The process is carried out, and before the ion implantation to form the source 12 and the drain 13 in the microbridge, the ion of the conductivity type opposite to that of the source 12 and the drain 13 of the microbridge can be selected to reach the substrate 7. After inserting the implantation step with a high acceleration energy, and forming the sources 2, 12 drains 3 and 13, a part of the source region 12 of the deposited Si 9 is removed by etching using a mask and formed on the substrate 7 By inserting the process of separating the source 2, a MOSFET of the type shown in FIG. This is a joint gate CMOS in which the upper MOSFET is the MOSFET described in the seventh embodiment.

In Fig. 7, reference numeral 1 denotes a gate electrode, 19 a gate electrode terminal, 20 a source electrode terminal of an upper MOSFET, 21 a source electrode terminal of a lower MOSFET, and 22 a polycrystalline Si film.

As mentioned above, although some Example was described, among them, Example 1 (FIG. 1 (d)), Example 2 (FIG. 2 (d)), Example 7 (FIG. 5 (d)), Example In FIG. 8 (FIG. 6) and Example 9 (FIG. 7), an air layer is used as the interlayer insulation between the upper MOSFET and the lower MOSFET or the substrate 7, but other insulators such as SiO ₂ , Si ₃ , and N ₄ are used. Not to mention that may charge. However, the lower the dielectric constant of the interlayer insulating film, the better. Therefore, a vacuum having the smallest dielectric constant is preferred, and nitrogen or air corresponding thereto is preferable. In the above embodiment, when the small intestine was mounted, a method of sealing with dry nitrogen was taken.

In the above embodiment, a device having a two-layer or three-layer structure of the deposited Si layer and the Si substrate is made. However, if the method described in the above embodiment is used by stacking several steps of the microbridge thereon, the device having four or more layers is provided. Not to mention that you can make it. It goes without saying that in the second embodiment and the multi-stage device, elements other than MOSFETs, for example, capacitors and the like, can be made of a microbridge or a substrate.

In the above embodiment, the interface state density between the Si film on the insulator and the insulator was very small, about 2X10 ^-10 cm ^-2 . As a result, even if a channel stopper is not formed here, the leakage current between the Si film and the source drain of the MOSFET formed on the Si film can be reduced to the same or less than that of the MOSFET made on the Si substrate.

You may use all well-known etching techniques for the various etching used by the said Example.

As described above, according to the present invention, the interface characteristics between the bottom insulating film and the semiconductor layer formed on the insulating film can be greatly improved. As a result, the leakage current between the source and drain of the MOSFET can be prevented even without a channel stopper formed at the interface, and the basic process of the MOSFET using the bottom insulating film as the gate insulating film can be established. In addition, as described above, according to the present invention, it is not necessary to form a chanel stopper, so that the chanel stopper manufacturing process is not necessary, and a MOSFET having a high joint gate CMOS and a high transfer conductance can be easily obtained.

Claims (8)

(Iii) forming at least one first insulating film 8 of a predetermined shape on the substrate; (ii) forming a continuous semiconductor film 9 on the substrate and on the first insulating film; (Iv) lithographically forming at least one island-shaped island region formed of a semiconductor film continuously present on the substrate and on the first insulating film and the first insulating film under the semiconductor film; Iii) removing at least the semiconductor side of the first insulating film in the island-like region to form a microbridge 30 serving as the semiconductor film, and (iii) on the exposed surface of the microbridge. A method of manufacturing a semiconductor device having a step of forming a second insulating film (48). And (iii) forming a MOSFET in the micro bridges (30), wherein the second insulating film (48) is a gate insulating film (4). The manufacturing method of the semiconductor device of Claim 1 whose said board | substrate is a Si semiconductor substrate. The manufacturing method of the semiconductor device of Claim 2 which is the said board | substrate Si semiconductor substrate. The manufacturing method of the semiconductor device of Claim 3 which has a MOSFET element in the surface part of the said semiconductor substrate. The manufacturing method of the semiconductor device of Claim 4 which has a MOSFET element in the surface part of the said semiconductor substrate. After the step (iii) is completed, the step of providing a first insulating film on the microbridge and the steps (ii) to (iii) are repeated at least once to form a multilayer microbridge. A method for manufacturing a semiconductor device according to claim 2. (Iii) forming at least one first insulating film 8 of a predetermined shape on the semiconductor substrate, (ii) forming a continuous semiconductor film 9 on the semiconductor substrate and on the first insulating film; And (iii) lithographically forming at least one island-like island in a predetermined shape, the semiconductor film being continuously on the semiconductor substrate and on the first insulating film, and the first insulating film beneath the semiconductor film. And (i) forming a source region and a drain region in the semiconductor substrate and the semiconductor film, respectively, by (i) ion implantation 11, and (iii) removing the first insulating film in the island-like region and removing the microbridges. Forming a second insulating film 48 on the exposed surface of the microbridge; and (i) a gate electrode at a gap below the microbridge. A method of manufacturing a semiconductor device having a step of forming a film.

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