JP3273989B2 - Method of manufacturing MIS transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a MIS transistor.

[0002]

2. Description of the Related Art The technology for forming a MOS transistor is as follows.
For example, 'A POLYSILICON TRANSISTOR TECHNOLOGY FOR LA
RGE CAPACITY SRAMs' (IEDM 90 tech. Digest pp469-4
72).

A typical conventional structure of such a MOS transistor will be described with reference to FIGS.

First, as shown in FIG. 4A, an insulating film 12 made of a silicon oxide film having a thickness of several hundred nm is formed on a semiconductor silicon substrate 11 by a thermal oxidation method or a CVD method. Then, a semiconductor silicon thin film 13 made of CVD polysilicon, amorphous silicon, or the like is formed on the insulating film 12.

Next, as shown in FIG. 4B, a gate insulating film 14 is formed by thermally oxidizing the surface of the semiconductor silicon thin film 13. Then, this gate insulating film 1
4, an impurity of the first conductivity type is ion-implanted into the semiconductor silicon thin film 13.

Then, as shown in FIG. 4C, a gate electrode 15 is formed by patterning a tungsten polycide film or a polysilicon film doped with phosphorus at a high concentration on the gate insulating film 14.

Next, as shown in FIG. 4D, ions of the second conductivity type are ion-implanted into the semiconductor silicon thin film 13 using the gate electrode 15 as a mask, and the gate electrode 15 The source / drain diffusion layers 16 are formed on both sides of the.

[0008]

However, in the conventional MOS transistor 18 manufactured as described above, the source / drain diffusion layer 16 and the channel region 17 between them are formed as shown in FIG. It was formed planarly in the same semiconductor silicon thin film 13.

For this reason, when the element is miniaturized to shorten the gate length of the MOS transistor 18, there is a problem that a short channel effect occurs.

It is an object of the present invention to provide a method of manufacturing a MIS transistor which can secure a sufficient channel length even when the element is miniaturized and does not generate a short channel effect.

[0011]

In order to solve the above-mentioned problems, a method of manufacturing an MIS transistor according to the present invention comprises the steps of locally forming a groove in a surface portion of a semiconductor substrate of a first conductivity type; Forming a surface region isolating insulator layer by embedding the semiconductor substrate with an insulator; forming a first insulating film on the surface of the semiconductor substrate; and forming the semiconductor substrate on both sides of the surface region isolating insulator layer. Forming an impurity diffusion layer of the second conductivity type on the surface portion of the semiconductor device; forming an opening in the first insulating film on the impurity diffusion layer of the second conductivity type; After forming the thin film, patterning the thin film, leaving the semiconductor thin film only in the region from the top of the surface region isolation insulator layer to the opening of the first insulating film on both sides thereof, Second insulation on the entire surface including the side Forming a, and a step of forming a gate electrode so as to cover the semiconductor thin film through the second insulating film.

Preferably, the present invention further comprises a step of forming a first conductivity type high concentration impurity diffusion layer in the semiconductor substrate at an inner surface portion of the groove.

In the present invention, preferably, the method further includes the step of taking out the electrode of the semiconductor thin film.

Preferably, in the present invention, the semiconductor thin film is formed of a polycrystalline silicon film or an amorphous silicon film deposited by a CVD method.

In the present invention, it is preferable that the second oxide film or the silicon nitride film is deposited by a CVD method.
Is formed.

In the present invention, preferably, the second insulating film is formed by thermal oxidation or thermal nitridation.

[0017]

In the MIS transistor manufactured by the method of the present invention, the impurity diffusion layer of the second conductivity type forming the source / drain region is formed on the semiconductor substrate, and the channel is formed by:
It is formed along the surface of the semiconductor thin film formed on the semiconductor substrate via the insulating layer for surface area separation. Therefore,
The channel length can be increased even in the thickness direction of the semiconductor thin film, and a sufficient channel length can be secured even when the element is miniaturized in the width direction.

In the present invention, the introduction of the second conductivity type impurity into the semiconductor substrate may be performed before or after the formation of the first insulating film on the semiconductor substrate.

[0019]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention; FIG.

FIG. 1 shows an MO according to a first embodiment of the present invention.
2 shows a configuration of an S transistor.

In this embodiment, the surface region of the semiconductor silicon substrate 41 containing the impurity of the first conductivity type is separated by the buried oxide layer 43, and both sides of the buried oxide layer 43 have the second conductivity type. Source / drain diffusion layers 42, which are impurity diffusion layers, are respectively formed. Then, a silicon oxide film 45 is formed on the surface of the semiconductor silicon substrate 41, and openings 44 are respectively formed in the silicon oxide film 45 above the source / drain diffusion layers 42. Then, a semiconductor silicon thin film 46 is formed so as to connect the source / drain diffusion layers 42 on both sides to each other across the central silicon oxide film 45. The semiconductor silicon thin film 46 is configured to be in contact with the source / drain diffusion layer 42 at a part of the opening 44 formed in the silicon oxide film 45. A gate insulating film 47 is formed on the entire surface including the side surface of the semiconductor silicon thin film 46. The gate insulating film 47 can be composed of a silicon oxide film or a silicon nitride film. The gate electrode 4 covers the side and top surfaces of the semiconductor silicon thin film 46 via the gate insulating film 47.
8 are formed.

In the transistor of this embodiment, a channel 49 serving as a current path is shown by a broken line in FIG. At this time,
In the semiconductor silicon thin film 46, electrodes are taken out at other portions, and the potential is fixed.

In manufacturing the transistor of this embodiment, first, a buried oxide layer 43 is formed in a semiconductor silicon substrate 41 by ion implantation of oxygen or the like. Note that a groove may be formed in the semiconductor silicon substrate 41, and the groove may be filled with, for example, silicon oxide to form the buried oxide layer 43. Next, a silicon oxide film 45 is formed on the entire surface by a thermal oxidation method or a CVD method. Then, ions of the second conductivity type are ion-implanted through the silicon oxide film 45 to form the source / drain diffusion layers 42, respectively. Thereafter, the silicon oxide film 4 is formed by photolithography.
5, an opening 44 is formed, and then a semiconductor silicon thin film containing a first conductivity type impurity is formed on the entire surface. And
This semiconductor silicon thin film is patterned and left in a shape as shown in FIG. At this time, the semiconductor silicon thin film 46
Make contact with the source / drain diffusion layers 42 at a part of the opening 44 formed in the silicon oxide film 45, respectively. The reason for this is that if the semiconductor silicon thin film 46 is brought into contact with the source / drain diffusion layer 42 in the entire opening 44 of the silicon oxide film 45, a gate offset is generated by the thickness of the silicon oxide film 45. Next, the patterned semiconductor silicon thin film 4
6, a gate insulating film 47 is formed on the entire surface including, for example, the CV.
Formed by Method D. Then, after depositing a gate electrode material on the entire surface, this is patterned to form a gate electrode 4.
8 is formed.

Next, a MOS transistor according to a second embodiment of the present invention will be described.
The transistor will be described with reference to FIGS.

First, as shown in FIG. 2A, the LOCOS method and ion implantation of impurities of the first conductivity type are performed on the semiconductor silicon substrate 21 of the first conductivity type, so that
A silicon oxide film 22 having a thickness of about 600 nm is locally formed on the surface of the silicon substrate 21, and a first conductivity type high concentration impurity diffusion, which is a kind of channel stopper, is formed in the silicon substrate 21 under the silicon oxide film 22. Layer 23
To form

Next, as shown in FIG. 2B, the semiconductor silicon substrate 21 is thermally oxidized to a thickness of 30 to 100 nm.
A silicon oxide film 24 is formed on the surface of the substrate. Next, the semiconductor silicon substrate 2 on both sides of the silicon oxide film 22
First, a second dose of about 1 × 10 ¹⁵ to 10 ¹⁶ cm ⁻² is used.
The conductive impurity 25 is ion-implanted and the silicon oxide film 2
Source / drain diffusion layers 26 are respectively formed in the surface regions of the semiconductor silicon substrate 21 on both sides of the substrate 2. The ion implantation of the impurity 25 of the second conductivity type may be performed before forming the silicon oxide film 24.

Next, as shown in FIG.
An opening 27 for partially exposing the drain diffusion layer 26 is formed.
It is formed on the silicon oxide film 24 by photolithography and etching.

Next, as shown in FIG. 2D, a semiconductor silicon thin film 28 having a thickness of several hundreds nm made of polysilicon or amorphous silicon deposited by the CVD method is formed on the entire surface. The semiconductor silicon thin film 28 has 1
The impurity 31 of the first conductivity type is ion-implanted at a dose of about × 10 ¹¹ to 10 ¹³ cm ⁻² .

Next, as shown in FIG. 2E, the semiconductor silicon thin film 2 is formed by photolithography and etching.
8 from the top of the silicon oxide film 22 to the source /
The pattern is formed so as to extend over the drain diffusion layer 26 and to come into contact with the source / drain diffusion layer 26 at a part of the opening 27. Thereafter, a silicon oxide film or a silicon nitride film is formed as the gate insulating film 32 by a CVD method or thermal oxidation or thermal nitridation.

Next, as shown in FIG. 2F, a gate electrode 33 that covers the semiconductor silicon thin film 28 with a gate insulating film 32 therebetween is formed of a polysilicon film or the like.

Thereafter, although not shown, an interlayer insulating film is formed, and an electrode is taken out of the semiconductor silicon thin film 28 with a polysilicon film or an amorphous silicon film deposited by the CVD method.

In the thin film transistor 34 of this embodiment manufactured as described above, the entire portion near the surface of the semiconductor silicon thin film 28 becomes a channel region. That is, in the thin film transistor 34 of this embodiment, the semiconductor silicon thin film 2
8 is covered with the gate insulating film 32 and the gate electrode 33, so that a channel 35 is formed in the entire portion near the surface of the semiconductor silicon thin film 28 as shown by the broken line in FIG. The thickness of the silicon thin film 28 also contributes to the channel length.

Therefore, from the viewpoint of obtaining stable characteristics independent of the fine processing dimensions, the semiconductor silicon thin film 28
The thicker the film, the better. However, as the film thickness increases, the workability deteriorates. Therefore, in the above-described embodiment, several hundred nm was selected as the film thickness of the semiconductor silicon thin film 28.

A semiconductor silicon thin film 28 is formed through the entire opening 27 formed in the silicon oxide
When the gate electrode 33 is configured to be in contact with the drain diffusion layer 26, the gate electrode 33 is offset by the thickness of the silicon oxide film 24 with respect to the semiconductor silicon thin film 28 as a channel region. Therefore, as clearly shown in FIGS. 2E and 2F, the semiconductor silicon thin film 28 is brought into contact with the source / drain diffusion layer 26 at a part of the opening 27.

Next, the MOS transistor according to the third embodiment of the present invention will be described.
The transistor will be described with reference to FIGS.

First, as shown in FIG. 3A, a photoresist 52 is patterned on a semiconductor silicon substrate 51 of the first conductivity type, and a groove 53 is formed in the semiconductor silicon substrate 51 by etching using the photoresist 52 as a mask. Form.

Thereafter, oblique ion implantation is performed on the groove 53 with the photoresist 52 remaining, and a high concentration impurity of the first conductivity type, which is a kind of channel stopper, is introduced into the semiconductor silicon substrate 51 on the inner surface of the groove 53. A diffusion layer 54 is formed.

Next, as shown in FIG. 3B, after removing the photoresist 52, for example, silicon oxide is buried in the trench 53 to form a buried oxide layer 55. Thereafter, a silicon oxide film 56 is formed on the entire surface by a thermal oxidation method or a CVD method. Then, a second conductivity type impurity is ion-implanted through the silicon oxide film 56 to form source / drain diffusion layers 57, respectively. The ion implantation of the second conductivity type impurity may be performed before the silicon oxide film 56 is formed.

Next, as shown in FIG.
An opening 58 that partially exposes the drain diffusion layer 57
The silicon oxide film 56 is formed by photolithography and etching. Thereafter, a semiconductor silicon thin film 59 made of polysilicon or amorphous silicon deposited by the CVD method is formed on the entire surface. Then, a first conductivity type impurity is ion-implanted into the semiconductor silicon thin film 59.

Then, by photolithography and etching, the semiconductor silicon thin film 59 is connected to the source / drain diffusion layers 57 on both sides across the central silicon oxide film 56, and the opening 58 formed in the silicon oxide film 56 is formed. The pattern is processed so as to partially contact the source / drain diffusion layer 57. Next, a silicon oxide film or a silicon nitride film is formed as a gate insulating film 60 on the entire surface including the entire surface of the patterned semiconductor silicon thin film 59 by a CVD method or thermal oxidation or thermal nitridation.

Next, as shown in FIG. 3E, a gate electrode material is deposited on the entire surface and then patterned to form a gate electrode 61.

Thereafter, although not shown, an interlayer insulating film is formed, and an electrode is taken out of the semiconductor silicon thin film 59 with a polysilicon film or an amorphous silicon film deposited by the CVD method.

Also in the transistor of this embodiment manufactured as described above, the entire portion near the surface of the semiconductor silicon thin film 59 becomes a channel region. That is, in the transistor of this embodiment, not only the upper surface but also the side surface of the semiconductor silicon thin film 59 is covered with the gate insulating film 60 and the gate electrode 61, and as shown by the broken line in FIG. A channel 62 is formed in the entire portion near the surface of 59, and the thickness of the semiconductor silicon thin film 59 also contributes to the channel length.

Also in this embodiment, the silicon oxide film 5
When the semiconductor silicon thin film 59 is configured to be in contact with the source / drain diffusion layer 57 through the entire opening 58 formed in the semiconductor silicon thin film 5 serving as a channel region,
9, the gate electrode 61 is offset by the thickness of the silicon oxide film 56. Therefore, FIG.
And (e), the semiconductor silicon thin film 59 is partially formed in the source / drain diffusion layer 57 at a part of the opening 58.
Contact.

[0045]

In the MIS transistor manufactured by the method of the present invention, not only the planar length of the semiconductor thin film but also its thickness contributes to the channel length. Therefore, it is possible to obtain an MIS transistor having stable characteristics that does not depend on a planar fine processing dimension.

Moreover, technically, the film thickness control can be performed more precisely than the planar dimension control of the semiconductor thin film by photolithography. Therefore, according to the method of the present invention, the channel length can be reduced. Precise control can be performed, and thereby stable characteristics can be obtained.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing the configuration of a MOS transistor according to a first embodiment of the present invention.

FIG. 2 is a schematic sectional view showing a method for manufacturing a MOS transistor according to a second embodiment of the present invention.

FIG. 3 is a schematic sectional view illustrating a method for manufacturing a MOS transistor according to a third embodiment of the present invention.

FIG. 4 is a schematic cross-sectional view showing a conventional method for manufacturing a MOS transistor.

[Explanation of symbols]

 Reference Signs List 21 semiconductor silicon substrate 22 silicon oxide film 23 high-concentration impurity diffusion layer (channel stopper) 24 silicon oxide film 26 source / drain diffusion layer 27 opening 28 semiconductor silicon thin film 32 gate insulating film 33 gate electrode 35 channel 41 semiconductor silicon substrate 42 source / Drain diffusion layer 43 buried oxide layer 44 opening 45 silicon oxide film 46 semiconductor silicon thin film 47 gate insulating film 48 gate electrode 49 channel 51 semiconductor silicon substrate 53 groove 54 high concentration impurity diffusion layer (channel stopper) 55 buried oxide layer 56 silicon Oxide film 57 Source / drain diffusion layer 58 Opening 59 Semiconductor silicon thin film 60 Gate insulating film 61 Gate electrode 62 Channel

Claims (6)

(57) [Claims] A step of locally forming a groove in a surface portion of a semiconductor substrate of a first conductivity type; a step of forming an insulator layer for surface region isolation by burying an insulator in the groove; Forming a first insulating film on the surface of the semiconductor substrate; forming a second conductivity type impurity diffusion layer on each of surface portions of the semiconductor substrate on both sides of the surface region isolation insulator layer; Forming an opening in each of the first insulating films on the two-conductivity-type impurity diffusion layer; forming a semiconductor thin film on the entire surface; patterning the semiconductor thin film; Leaving the semiconductor thin film only in a region reaching the opening of the first insulating film on both sides thereof; forming a second insulating film on the entire surface including side surfaces of the semiconductor thin film; Through the gate to cover the semiconductor thin film Method for producing a MIS transistor, characterized in that a step of forming a pole. 2. The method according to claim 1, further comprising the step of forming a first-conductivity-type high-concentration impurity diffusion layer in the semiconductor substrate at an inner surface portion of the trench. 3. The MIS according to claim 1, further comprising a step of taking out an electrode of the semiconductor thin film.
A method for manufacturing a transistor. 4. The method for manufacturing a MIS transistor according to claim 1, wherein said semiconductor thin film is formed of a polycrystalline silicon film or an amorphous silicon film deposited by a CVD method. . 5. The method according to claim 1, wherein the second insulating film is formed of a silicon oxide film or a silicon nitride film deposited by a CVD method. . 6. The method of manufacturing an MIS transistor according to claim 1, wherein said second insulating film is formed by thermal oxidation or thermal nitridation.