JP3295188B2 - Manufacturing method of SOI structure MOS transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an SOI (Silicon On In)
sulator or Semiconductor On Insulator) MOS transistor formed on a substrate (in the present invention, "SOI
It is referred to as a “structure MOS transistor”. )).

[0002]

2. Description of the Related Art FIG. 2 shows a conventional MOS having an SOI structure.
A method for manufacturing a transistor will be described.

[0003] The manufacturing method will be described first.
As shown in FIG. 1A, an insulating film 22 having a thickness of, for example, several hundred nm is formed on a semiconductor silicon substrate 21 by thermal oxidation of silicon or deposition of a silicon oxide film by CVD.

Next, a semiconductor silicon layer 23 is formed on the insulating film 22 using a semiconductor material such as CVD polysilicon or amorphous silicon.

Next, as shown in FIG. 2B, the gate insulating film 24 is formed by thermally oxidizing the semiconductor silicon layer 23. Then, for example, N-type impurities are ion-implanted into the semiconductor silicon layer 23 through the gate insulating film 24.

Next, as shown in FIG. 2 (c), tungsten polycide or polysilicon doped with a high concentration of phosphorus is deposited on the gate insulating film 24 and is patterned, so that the gate length becomes w. Of the gate electrode 25 is formed.

Next, as shown in FIG. 2D, using the gate electrode 25 as a mask, for example, a P-type impurity is ion-implanted into the semiconductor silicon layer 23 through the gate insulating film 24 to thereby form the source / drain region 26. To form

A technique similar to that described above is described in, for example, "A POLYSILICON TRANSISTOR TECHNOLOGY FOR LARGE
CAPACITY SRAMs "(IEDM 90, pp.469-472).

[0009]

The above-mentioned conventional SOI
In a structured MOS transistor, as shown, the source / drain region and the channel region are in the same semiconductor silicon layer, and the channel length between the source and the drain is determined by the gate length. Therefore, when the gate length is shortened in a miniaturized MOS device, there is a problem that a short channel effect occurs.

An object of the present invention is to provide a method of manufacturing an SOI-structure MOS transistor having a stable electric characteristic whose channel length does not depend on the precision of microfabrication while avoiding a short channel effect caused by miniaturization of a MOS device. To provide.

[0011]

In order to solve the above-mentioned problems, a method of manufacturing a MOS transistor having an SOI structure according to the present invention comprises the steps of: forming a semiconductor layer of a first conductivity type on an insulating substrate; Patterning a conductive type semiconductor layer to form a pair of first conductive type semiconductor layers facing each other at a predetermined gap; and sidewalls of the pair of first conductive type semiconductor layers in the gap. Forming a side wall spacer made of an insulator on the substrate;
Forming a semiconductor layer of the second conductivity type in a region extending from the upper surface of the semiconductor layer of the conductivity type across the gap;
Forming a dielectric thin film on the conductive semiconductor layer and the second conductive semiconductor layer; and forming a gate electrode on the dielectric thin film in a region facing the second conductive semiconductor layer. And

In a preferred aspect of the present invention, the semiconductor layer of the first conductivity type and the semiconductor layer of the second conductivity type are formed of polycrystalline silicon or amorphous silicon, respectively.

In another preferred aspect of the present invention, the semiconductor layer of the first conductivity type is formed of titanium polycide or tungsten polycide.

In a further preferred aspect of the present invention, the gate electrode is formed of polycrystalline silicon or tungsten polycide.

In a further preferred aspect of the present invention, the dielectric thin film is formed of silicon oxide, silicon nitride, or a composite film thereof.

In a further preferred aspect of the present invention, the dielectric thin film is formed by thermal oxidation or thermal nitridation of the semiconductor layer of the first conductivity type and the semiconductor layer of the second conductivity type.

[0017]

The SOI structure MO manufactured by the method of the present invention.
In the S-transistor, the source / source formed by a pair of first conductivity type semiconductor layers facing each other with a predetermined gap therebetween.
Since the semiconductor layer of the second conductivity type formed on the drain region becomes a channel region, both the side surface portion and the upper surface portion of the channel region contribute to the channel length of the MOS transistor.

Therefore, the channel length of the conventional SOI structure MOS transistor is determined only by the length (gate length) of the upper surface portion of the channel region. However, in the SOI MOS transistor manufactured according to the present invention, the side surface of the channel region is also used as the channel length. An SOI structure MOS transistor having electrical characteristics can be provided.

[0019]

An embodiment of the present invention will be described below with reference to FIG.

First, as shown in FIG. 1A, an insulating film 2 is formed on a semiconductor silicon substrate 1 by thermal oxidation of silicon or deposition of a silicon oxide film by CVD. This insulating film 2 is formed with a thickness of, for example, several hundred nm.

Next, titanium polycide, tungsten polycide, polysilicon or the like is deposited on the insulating film 2 by a CVD method, a sputtering method, or the like to a thickness of 100 to 200 nm, and the first semiconductor silicon layer 3 is formed. Form.

Since the first semiconductor silicon layer 3 becomes a source / drain region of a MOS transistor, for example, a P-type impurity is introduced at a high concentration by ion implantation or diffusion. When tungsten polycide is used for the first semiconductor silicon layer 3, for example, the upper layer of tungsten polycide is made of polysilicon and the lower layer is made of tungsten silicide in order to obtain a semiconductor-semiconductor junction with a channel region to be formed later. Formed.

Next, as shown in FIG. 1B, the first semiconductor silicon layer 3 is separated by patterning by photolithography and etching techniques, and a pair of source / drain regions 4 opposed to each other with a predetermined gap therebetween. To form

Next, sidewall spacers 5 are formed on the side surfaces of the source / drain regions 4 using an insulator such as silicon oxide or silicon nitride.

Next, as shown in FIG. 1C, a second semiconductor silicon layer is formed on the semiconductor silicon substrate 1 using a semiconductor material such as CVD polysilicon or amorphous silicon, and ion implantation or a diffusion method is used. Thereby, for example, an N-type impurity is introduced at a low concentration.

Next, a channel region 6 is formed by patterning the second semiconductor silicon layer by photolithography and etching techniques.

Here, the thickness h of the second semiconductor silicon layer
Is the length of the side surface portion of the channel region 6 and is a part of the channel length. Therefore, the channel length becomes longer as the thickness h of the second semiconductor silicon layer is larger, so that a transistor having stable electric characteristics regardless of the precision of microfabrication can be provided. However, in the present embodiment, the thickness h of the second semiconductor silicon layer is set to several hundred nm in consideration of the balance with workability.

The channel region 6 is formed so as to overlap with the source / drain region 4 so that the bottom portions at both ends of the channel region 6 are electrically connected to the respective upper surfaces of the source / drain regions 4. .

Next, as shown in FIG.
The gate insulating film 7 is formed by thermal oxidation of a semiconductor silicon layer forming the drain region 4 and the channel region 6 or deposition of a silicon oxide film on the source / drain region 4 and the channel region 6 by CVD. Note that the gate insulating film may be formed by thermal nitridation of each semiconductor silicon layer or deposition of a silicon nitride film by CVD. Further, the gate insulating film may be formed by an ONO film.

Next, as shown in FIG. 1E, tungsten polycide or polysilicon doped with phosphorus at a high concentration is deposited on the entire surface so as to cover the upper surface and side surfaces of the channel region 6. The gate electrode 8 is formed by patterning.

The SO of the present embodiment formed as described above
In the I-structure MOS transistor, as shown in FIG. 1E, the opposing surfaces of the source / drain regions 4 facing each other are closed by sidewall spacers 5 made of an insulator, and the source / drain regions 4 and the channel The region 6 is in contact only with the upper surface of the source / drain region 4. Since the channel of the MOS transistor is formed along the portion near the surface of the channel region 6 facing the gate electrode 8, not only the horizontal length but also the vertical length of the channel region 6 contributes to the channel length. Therefore, the channel length can be made larger than the planar width of the channel region 6, and a sufficient channel length can be ensured even for a fine MOS device.

The semiconductor silicon substrate 1 used in this embodiment is a pedestal for maintaining mechanical strength. When an insulator substrate is used instead of the semiconductor silicon substrate 1, the formation of the insulating film 2 is necessary. Absent. Further, in this embodiment, an example in which the semiconductor silicon substrate 1 is used as a starting material has been described. However, even when the insulating substrate is used as a starting material, the manufacturing method described below can be applied.

[0033]

According to the method of manufacturing an SOI structure MOS transistor of the present invention, a short channel effect caused by miniaturization of a MOS device can be avoided, and stable electrical characteristics independent of fine processing accuracy in a photolithography step or the like can be avoided. Can be realized.

Further, since the channel length of the MOS transistor can be controlled by the film thickness of the channel region, it can be controlled more precisely than the fine processing accuracy.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view showing a method of manufacturing a MOS transistor according to an embodiment of the present invention in the order of steps.

FIG. 2 is a longitudinal sectional view showing a conventional method for manufacturing a MOS transistor in the order of steps.

[Description of Signs] 1 Semiconductor silicon substrate 2 Insulating film 3 First semiconductor silicon layer 4 Source / drain region 5 Sidewall spacer 6 Channel region 7 Gate insulating film 8 Gate electrode

────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-61-204976 (JP, A) JP-A-1-165127 (JP, A) JP-A-5-206166 (JP, A) JP-A-6-206 209109 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 29/786 H01L 21/336

Claims (6)

(57) [Claims] A step of forming a semiconductor layer of a first conductivity type on an insulating substrate; and a step of patterning the semiconductor layer of the first conductivity type to form a pair of first conductivity types facing each other at a predetermined gap. A step of forming a semiconductor layer of; a step of forming a sidewall spacer made of an insulator on a side wall within the gap between the pair of first conductive type semiconductor layers; Forming a second conductivity type semiconductor layer in a region extending from the upper surface across the gap; and forming a dielectric thin film on the pair of the first conductivity type semiconductor layer and the second conductivity type semiconductor layer. And a step of forming a gate electrode on the dielectric thin film in a region facing the semiconductor layer of the second conductivity type. 2. The semiconductor layer of the first conductivity type and the second conductive layer.
2. The semiconductor device according to claim 1, wherein the conductive semiconductor layer is formed of polycrystalline silicon or amorphous silicon.
Manufacturing method of OI structure MOS transistor. 3. The method according to claim 1, wherein the semiconductor layer of the first conductivity type is formed of titanium polycide or tungsten polycide. 4. The method according to claim 1, wherein said gate electrode is formed of polycrystalline silicon or tungsten polycide. 5. The SOI structure MO according to claim 1, wherein the dielectric thin film is formed of silicon oxide, silicon nitride, or a composite film thereof.
A method for manufacturing an S transistor. 6. The SOI according to claim 5, wherein the dielectric thin film is formed by thermal oxidation or thermal nitridation of the semiconductor layer of the first conductivity type and the semiconductor layer of the second conductivity type.
Manufacturing method of structured MOS transistor.