JPH04109630A - Manufacture of mos type semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the dispersion of the characteristics of a MOS transistor by forming a channel region in a section adjacent to the sidewall of a gate electrode. CONSTITUTION:Gate electrodes 3 are shaped onto insulating substrates 1, 2, a gate insulating film 4 and a semiconductor film 6 are formed successively so as to cover the gate electrodes 3 and the insulating films 1, 2, and the ions of an impurity for determining the conductivity type of a channel region and impurity concentration are implanted to the surfaces of the insulating substrates 1, 2 from the inclined direction. Masks 7 are formed to the sidewalls of the recessed section of the semiconductor film 6, and ions of an impurity for shaping a source region and a drain region 8, 9 are implanted to the surfaces of the insulating substrates 1, 2 from the inclined direction by using the masks 7. Consequently, since the channel regions are formed to sections adjacent to the sidewalls of the gate electrodes 3, effective channel length is determined by the height of the gate electrodes 3. Accordingly, effective channel length can be determined with high accuracy, thus reducing the dispersion of the characteristics of a MOS transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a MOS type semiconductor device, and is suitable for application to, for example, manufacturing MO3LSI.

[Conventional technology]

FIG. 2 shows a conventional method for manufacturing a MOS type semiconductor device.

In this conventional method of manufacturing a MOS type semiconductor device,
As shown in FIG. 2A, first, a field insulating film 102 is formed on the surface of a silicon substrate 1010 by the LOCO3 method to perform element isolation, and then a thermal oxidation method is applied to the surface of the channel region surrounded by this field insulating film 102. A gate insulating film 103 is formed by the following steps. Next, this gate insulating film 10
Impurity ions for threshold voltage adjustment are ion-implanted into the silicon substrate 101 through 3.

Next, a polycrystalline silicon film is formed on the entire surface by CVD, and after doping the polycrystalline silicon film with impurities to lower its resistance, the polycrystalline silicon film is patterned into a predetermined shape by etching.

As a result, as shown in FIG. 2B, the gate electrode 10
4 is formed. Note that this gate electrode 104 can also be formed of, for example, a polycide film (a composite film in which a high melting point metal silicide film is stacked on a polycrystalline silicon film doped with impurities). Next, this gate electrode 10
4 and the field insulating film 102 as masks, impurities of a conductivity type opposite to that of the silicon substrate 101 are ion-implanted at a high concentration into the silicon substrate 101, thereby forming the source region 105 and the gate electrode 104 in a self-aligned manner with respect to the gate electrode 104. A drain region 106 is formed. These gate electrodes 104
, the source region 105 and the drain region 106
S) A transistor is formed.

[Problem to be solved by the invention]

In the above-described conventional method for manufacturing a MOS type semiconductor device, the gate electrode 10 is formed by patterning by etching.
4, the variation in gate length is large. For this reason, the effective channel length, which determines the performance of MOS) transistors, varies widely, and therefore MO3I-
There was a large variation in transistor characteristics.

Furthermore, since the integration density of this MOS type semiconductor device is determined by the dimensions of the field insulating film 1020 and the gate length, it has been difficult to achieve high integration and density.

Furthermore, the element isolation in this MOS type semiconductor device is
Since this is done by forming the field insulating film 102 using the OCO3 method, this field insulating film 102
There is a problem in that the threshold voltage of the MOS transistor becomes high due to a narrow channel effect caused by the formation of a bird's beak at the end of the MOS transistor.

Therefore, an object of the present invention is to reduce the variation in the effective channel length of MO3I-transistors.
) An object of the present invention is to provide a method for manufacturing a MOS type semiconductor device that can reduce variations in characteristics of transistors.

Another object of the present invention is to provide a method for manufacturing a MOS type semiconductor device that can achieve high integration and high density.

Still another object of the present invention is to provide a method for manufacturing a MOS type semiconductor device that can prevent narrow channel effects.

[Means to solve the problem]

In order to solve the above problems, a method for manufacturing a MOS type semiconductor device according to the present invention includes the steps of forming a gate electrode on an insulating substrate, and forming a gate insulating film and a semiconductor film so as to cover the gate electrode and the insulating substrate. a step of ion-implanting an impurity for determining the conductivity type and impurity concentration of a channel region into the semiconductor film from a direction inclined with respect to the surface of the insulating substrate; and a side wall of the recess of the semiconductor film. and a step of ion-implanting impurities for forming a source region and a drain region into the semiconductor film from a direction oblique to the surface of the insulating substrate using the mask.

[Effect]

According to the method for manufacturing a MOS type semiconductor device of the present invention configured as described above, the channel region of the MOS transistor is formed by the portion of the semiconductor film adjacent to the side wall of the gate electrode, so that the effective channel of the MOS transistor is The length can be determined by the height of the gate electrode, that is, the thickness of the conductor film for forming the gate electrode. Therefore, it is possible to determine the effective channel length with a precision that is, for example, about 10 times higher than in the past.
Variations in characteristics of S transistors can be reduced.

Moreover, this MOS type semiconductor device is a so-called So 1
(Silicon on Insulator) structure, element isolation can be performed without forming a field insulating film by the LOCO3 method as in the conventional method. Moreover, in this MOS type semiconductor device, MO
The 3I-transistor has a vertical structure instead of a planar structure like the conventional one. As a result, the area occupied by each MOS transistor can be reduced compared to the conventional method.
Therefore, it is possible to achieve high integration and high density of the MO3 type semiconductor device.

Furthermore, since there is no need to form a field insulating film using the LOCO3 method for element isolation, a bird's beak is not formed at the edge of this field insulating film, and therefore, the narrow channel effect caused by this bird's beak is prevented. can do.

[Example] The present invention will be described below with reference to the drawings.

1A to 1F show a method of manufacturing an MO3 type semiconductor device according to an embodiment of the present invention.

In this embodiment, as shown in FIG. 1A, first,
An insulating film 2 is formed on a silicon substrate 1.

Here, the conductivity type of this silicon substrate 1 may be P type or N type. Further, in order to reduce parasitic capacitance, it is desirable that the insulation M2 has a sufficiently large film thickness and a small dielectric constant. Specifically, the insulating film 2 is formed by a thermal oxidation method or a CVD method, and has a thickness of, for example, 0.
A silicon dioxide film with a thickness of about 5 to 10 am is formed.

Next, a film thickness of, for example, 0.3 is applied to the entire surface by, for example, the CVD method.
After forming a polycrystalline silicon film with a thickness of ~1.0 μm and implanting impurities such as phosphorus, arsenic, or boron into this polycrystalline silicon film at a dose of, for example, about 10”/cd to lower the resistance, This polycrystalline silicon film is patterned by etching to form a gate electrode 3.

Note that this gate electrode 3 can also be formed, for example, by a polycide film (a composite film in which a high-melting point metal silicide film is layered on a polycrystalline silicon film doped with impurities), and in this case, the above-mentioned method may be used. After forming a high melting point metal silicide film such as a tungsten silicide film on a polycrystalline silicon film doped with impurities by sputtering or CVD, the high melting point metal silicide film and the polycrystalline silicon film are buttered. The gate electrode 3 is thereby formed.

Next, as shown in FIG. 1B, a gate insulating film 4 such as a silicon dioxide film or a silicon nitride film having a thickness of approximately 0.01 to 0.05 μm is formed over the entire surface by, for example, the CVD method. Thereafter, a polycrystalline or amorphous silicon film 5 having a thickness of, for example, about 0.02 to 0.05 μm is formed over the entire surface by, for example, the CVD method.

Next, this silicon film 5 is recrystallized by a recrystallization method using, for example, laser beam irradiation to form a single crystal silicon WA6 as shown in FIG. 1C. This single crystal silicon film 6 is used as a channel region.

Next, as shown by the arrow in the first diagram, p-type or n-type impurities are ion-implanted at a low concentration into the entire surface of this single-crystal silicon film 6 to determine the conductivity type and impurity concentration of the channel region. . In this case, since a recess is formed in the single crystal silicon film 6 due to the step caused by the gate electrode 3, the ion implantation is performed so that the impurity ions are also implanted into the side walls and bottom of the recess. The step is performed from a direction inclined, for example, at a maximum of about 45 degrees with respect to the substrate surface. The dose of this ion implantation is, for example, lXl0
”~I x 10'3/cj.

Next, a film thickness of, for example, 0.2 is applied to the entire surface by, for example, the CVD method.
After forming a silicon dioxide film of approximately 1.0 μm, this silicon dioxide film is subjected to, for example, reactive ion etching (
Anisotropic etching is performed in a direction perpendicular to the substrate surface using the RIE method. As a result, as shown in FIG. 1E, a mask 7 made of this silicon dioxide film is formed in the shape of a sidewall spacer on the side wall of the recessed portion of the single crystal silicon film 6.

Thereafter, using this mask 7, impurities for forming source and drain regions are ion-implanted into the single crystal silicon film 6 at a high concentration from a direction inclined at a maximum of 45 degrees with respect to the substrate surface. Semiconductor regions 8 and 9 are formed to be used as regions or drain regions. Then, the gate electrode 3 and these semiconductor regions 8 and 9
A MO5I-transistor is formed.

Specifically, in the case of an n-channel MO3) transistor, n-type impurities such as arsenic and phosphorus are added to
For example, n-type semiconductor regions 8 and 9 are formed by ion implantation at a dose of about ~lXl0''/d,
In the case of a P-channel MOS transistor, a p-type impurity such as boron is added, for example, from I x 10'' to I x 1
For example, P" type semiconductor regions 8 and 9 are formed by ion implantation at a dose of about 0"/cd.

In this case, since the ion implantation is performed in a direction oblique to the substrate surface, it is possible to prevent the semiconductor regions 8 and 9 used as the source or drain regions from being offset from the gate electrode 3. can.

Next, after removing the mask 7 by etching, as shown in FIG. 1F, the portions of the single crystal silicon film 6 between the adjacent gate electrodes 3 are removed by etching to isolate the transistors.

After this, for example, the film thickness by CVD method is 0.3 to 1.
．． Formation of an interlayer insulating film of approximately 0 μm, formation of contact holes in this insulating film between the eyebrows, formation of metal wiring by patterning an aluminum film formed by sputtering, formation of a passivation film, etc. are performed to achieve the desired purpose. Complete the MOS type semiconductor device.

As described above, according to this embodiment, the gate is formed by the single crystal silicon film 6 in the portion adjacent to the side wall of the pole 3 (MOS).
Since the channel region of the transistor is formed, the effective channel length of this MOS transistor can be determined by the height of the gate electrode 3, that is, the thickness of the conductive film for forming the gate electrode 3. Therefore, the effective channel length can be determined with high accuracy of submicron or less, and variations in the characteristics of this MOS transistor can be reduced.

Further, since this MOS type semiconductor device has a Sol structure, there is no need to form a field insulating film by the Locos method as in the conventional method in order to perform element isolation. Moreover, the MOS transistor in this MOS type semiconductor device is
The channel region is formed by forming a gate insulating film 4 on the side wall of the gate electrode 3.
Since it has a vertical structure in which the semiconductor region 8 used as a source region or drain region is formed on the gate electrode 3, it requires only one MOS transistor, compared to a conventional planar structure MOS transistor. The area occupied by each hit can be reduced, and M
High integration and high density of OS type semiconductor devices can be achieved.

Furthermore, since it is not necessary to form a field insulating film by the LOCO5 method to perform element isolation as described above, it is possible to prevent the narrow channel effect caused by bird's beaks formed at the ends of this field insulating film. . Furthermore, there is no need to take into account pattern conversion differences caused by the formation of bird's beaks at the ends of the field insulating film.

Although the present invention has been specifically described above with reference to one embodiment, the present invention is not limited to the above-mentioned embodiment, and the above-mentioned embodiment is not limited to various effective modifications based on the technical idea of the present invention. is possible.

For example, when forming semiconductor regions 8 and 9 used as source regions or drain regions by ion implantation,
With the single crystal silicon film 6 on the top surface and sidewalls of one gate electrode 3 shown in FIG. and 9 are formed, and after this resist pattern is removed, p-type impurity is ionized while the single crystal silicon film 6 on the upper surface and sidewall portions of the other gate electrode 3 is covered with the newly formed resist pattern. By forming P type semiconductor regions 8 and 9 by implantation, it is possible to form an n-channel MOS transistor and a P-channel MOS transistor adjacent to each other, thereby forming a CMOS. Is possible.

Further, in the above embodiment, an insulating substrate in which an insulating film 2 is formed on a silicon substrate 1 is used, but it is also possible to use various insulating substrates other than this.

Further, the gate electrode 3 is not only made of a polycrystalline silicon film or a polycide film (for example, it can also be formed of a high melting point metal film such as a tungsten film).

〔Effect of the invention〕

Since the present invention is configured as explained above, the MO
S) Variations in transistor characteristics can be reduced, high integration and density can be achieved, and narrow channel effects can be prevented.

[Brief explanation of drawings]

1A to 1F are cross-sectional views showing the manufacturing method of an MO3 type semiconductor device according to an embodiment of the present invention in the order of steps, and FIG. 2A
and FIG. 2B are cross-sectional views showing a conventional method for manufacturing an MO3 type semiconductor device in the order of steps. In addition, in the symbols used in the drawings, 1-----1.Silicon substrate 2.---m-Insulating film 3.----Gate electrode 4--Gate insulating film 5-. ---Silicon film 6---Single crystal silicon film 8.9 ---One semiconductor region. The first drawing

Claims (1)

[Claims] A step of forming a gate electrode on an insulating substrate, a step of sequentially forming a gate insulating film and a semiconductor film so as to cover the gate electrode and the insulating substrate, and a step of forming a gate electrode on the surface of the insulating substrate. a step of ion-implanting an impurity for determining the conductivity type and impurity concentration of the channel region into the semiconductor film from an inclined direction; a step of forming a mask on the sidewall of the recess of the semiconductor film; A method for manufacturing a MOS type semiconductor device, comprising the step of ion-implanting impurities for forming a source region and a drain region into the semiconductor film from a direction inclined with respect to a surface of an insulating substrate.