JP3413990B2 - Manufacturing method of stacked diffusion layer type MIS semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION This invention relates to a stacked diffusion layer type M.
The present invention relates to a method for manufacturing an IS semiconductor device.

[0002]

10 to 16 are sectional views showing an example of a method of manufacturing a conventional stacked diffusion layer type MIS semiconductor device in the order of steps.

According to this conventional method of manufacturing a stacked diffusion layer type MIS semiconductor device, as shown in FIG.
After selectively oxidizing the surface of the semiconductor substrate 101 to form a selective oxide film (field insulating film) 102 for element isolation, the semiconductor substrate 1 is stacked with an impurity-doped semiconductor layer. An offset layer 104 made of an insulating film that also functions as a diffusion layer 103 and an interlayer insulating film is sequentially formed.

Next, as shown in FIG. 11, after forming a resist pattern 105 having a predetermined shape on the offset layer 104, the offset layer 104 and the stacked diffusion layer 103 are selectively etched by using the resist pattern 105 as a mask. . Here, this etching is performed with a slight overetching so that the stacked diffusion layer 103 is completely etched in the thickness direction thereof. Reference numeral 106 indicates a recess formed in the portion where the gate electrode is to be formed by this etching.

Next, after removing the resist pattern 105, an insulating film 107 for forming a sidewall spacer is formed on the entire surface by a CVD method, as shown in FIG.

Next, as shown in FIG. 13, the side wall spacer forming insulating film 107 is etched in a direction perpendicular to the substrate surface by a reactive ion etching (RIE) method to form a side wall spacer on the side surface of the recess 106. 108 is formed. Here, (width of recess 106) -2 ×
(Width of sidewall spacer 108) corresponds to the gate length.

Next, as shown in FIG. 14, impurities 10 are formed in the semiconductor substrate 1 from a direction substantially perpendicular to the surface of the semiconductor substrate 1 by using the stacked diffusion layer 103, the offset layer 104 and the sidewall spacers 108 as a mask.
By performing the ion implantation of No. 9, the impurity concentration of the surface portion of the semiconductor substrate 1 excluding the portion covered by the sidewall spacers 108 in the concave portion 106 is set to a value such that a desired threshold voltage V _th can be obtained. .

Next, as shown in FIG. 15, a gate insulating film 110 is formed by thermally oxidizing the surface portion of the semiconductor substrate 1 excluding the portion covered by the sidewall spacers 108 in the concave portion 106, and then the gate insulating film 110 is formed. Insulation film 1
A gate electrode 111 is formed on 10. Next, heat treatment is performed to diffuse the impurities in the stacked diffusion layer 103 into the semiconductor substrate 101 to form the source region 112 and the drain region 113. These gate electrodes 11
1, the source region 112 and the drain region 113 form a MIS transistor. After that, the interlayer insulating film 114 is formed on the entire surface.

When the MIS transistor is an n-channel MIS transistor, the semiconductor substrate 10
1 is, for example, p-type, and the source region 112 and the drain region 113 are, for example, n ⁺ -type, and the impurities in the stacked diffusion layer 103 at this time are n-type impurities. Also, the above M
When the IS transistor is a p-channel MIS transistor, the semiconductor substrate 101 is, for example, n-type, the source region 112 and the drain region 113 are, for example, p ⁺ -type, and the impurities in the stacked diffusion layer 103 at this time are p-type impurities. Is.

Next, as shown in FIG. 16, the interlayer insulating film 1
14 and a predetermined portion of the offset layer 104 are sequentially removed by etching to remove the contact holes 115, 11
After forming 6, the contact holes 115, 1
Wiring 1 connected to stacked diffusion layer 103 through 16
17 and 118 are formed. As described above, the intended stacked diffusion layer type MIS semiconductor device is manufactured.

[0011]

However, the stacked diffusion layer type MI manufactured by the above-described conventional manufacturing method.
In the S semiconductor device, the implantation region of the impurity 109 formed by the ion implantation for adjusting the V _{th of the} MIS transistor is formed in the same manner for the MIS transistor having any gate length. 11) Individual MISs caused by variations in gate length due to variations in dimensions and variations in processing when forming the sidewall spacers 108 (FIG. 13).
The variation in V _th between transistors becomes a problem. In particular, in the case of variations in which the gate length is shortened, V _th is reduced due to the short channel effect, which increases the leakage current at the time of turning off and the power consumption accompanying it, or the data retention characteristics of various memory circuits. There was a problem of causing deterioration.

Therefore, an object of the present invention is to provide a threshold voltage V due to variations in the gate length of MIS transistors.
_A stacked diffusion layer type MIS capable of preventing a decrease in _th , facilitating lowering of power consumption due to reduction of leakage current at the time of off and ensuring of operating characteristics in various memory circuits, and improvement of manufacturing yield. It is to provide a method for manufacturing a semiconductor device.

[0013]

In order to achieve the above object, the present invention provides a stacked diffusion layer (3) and an offset layer (4) covering the stacked diffusion layer (3) on a semiconductor substrate (1). A step of sequentially forming, a step of removing at least a portion of the stacked diffusion layer (3) and the offset layer (4) where the gate electrode (12) is to be formed to form a recess (6), and a recess (6) Forming a sidewall spacer (8) on the side surface of the semiconductor substrate (1) and using the stacked diffusion layer (3), the offset layer (4), and the sidewall spacer (8) as a mask in the MI substrate.
Step of performing ion implantation for adjusting the threshold voltage of the S-transistor, and forming a gate insulating film (11) on the semiconductor substrate (1) excluding the portion covered with the sidewall spacer (8) in the recess (6) And a step of forming a gate electrode (12) on the gate insulating film (11), and impurities in the stacked diffusion layer (3) are diffused into the semiconductor substrate (1) to form a source region (13) and a drain. Area (1
4) Stacked diffusion layer type MIS having a step of forming
In a method of manufacturing a semiconductor device, ion implantation for adjusting a threshold voltage is performed from a direction substantially perpendicular to a surface of a semiconductor substrate (1) using a first impurity for increasing a threshold voltage. Ion implantation and semiconductor substrate (1)
Second ion implantation using a second impurity for lowering the threshold voltage, which is performed from a direction forming an angle greater than 0 degree with respect to the surface normal. .

In the present invention, in the first ion implantation and the second ion implantation, the distance between one end of the first impurity implantation region and one end of the second impurity implantation region is δ,
The threshold voltage of the first impurity and second impurity implanted regions is V _thL , the threshold voltage of the first impurity implanted region is V _thH, and the gate length L of the MIS transistor is ΔL.
When the effect of the lowering of the threshold voltage due to the short channel effect that occurs when it is shortened by −K · ΔL is expressed, the impurity distribution of the first impurity and the second impurity is K = −2δ (V _thH − V _thL ) / L (L-ΔL) is satisfied.

In the present invention, the first impurity and the second impurity have different conductivity types from each other. For example, when the first impurity is a p-type impurity, the second impurity is an n-type impurity. Is.

[0016]

According to the method of manufacturing the stacked diffusion layer type MIS semiconductor device of the present invention configured as described above, the ion implantation for adjusting the threshold voltage is substantially perpendicular to the surface of the semiconductor substrate (1). First ion implantation using a first impurity for increasing the threshold voltage and a direction forming an angle of at least greater than 0 degree with respect to a normal line of the surface of the semiconductor substrate (1). Since the second ion implantation using the second impurity for lowering the threshold voltage is applied, a uniform threshold voltage independent of the gate length of the MIS transistor can be obtained for the following reason.

That is, now, as shown in FIG. 1, let us consider a state immediately before ion implantation for adjusting a threshold voltage in manufacturing a stacked diffusion layer type MIS semiconductor device. In FIG. 1, reference numeral 51 is a semiconductor substrate, 52 is a stacked diffusion layer, 53 is an offset layer, 54 is a recess, and 55 is a sidewall spacer. With respect to the structure shown in FIG. 1, the threshold voltage V _th is first increased from the direction substantially perpendicular to the surface of the semiconductor substrate 51 by using the stacked diffusion layer 52, the offset layer 53 and the sidewall spacer 55 as a mask. First ion implantation using the first impurity 56 is performed. Next, using the stacked diffusion layer 52, the offset layer 53, and the sidewall spacers 54 as a mask, at least 0 with respect to the normal to the surface of the semiconductor substrate 51.
Direction that forms an angle larger than the degree, that is, the semiconductor substrate 5
Second ion implantation using the second impurity 57 that lowers V _th is performed from the direction inclined with respect to the normal line to the surface of No. 1.

At this time, in the region of the surface portion of the semiconductor substrate 1 excluding the portion covered by the sidewall spacer 55, into which both the first impurity 56 and the second impurity 57 are implanted, a low V _th value ( An impurity distribution having V _thL ) is formed. In addition, the sidewall spacer 5
In the region where only the first impurity 56 is implanted due to the shadow effect due to the oblique ion implantation in the surface portion of the semiconductor substrate 1 excluding the portion covered by 5, the high threshold voltage V _th (V _thH An impurity distribution with is formed.

The _Vth of the MIS transistor having the above-described impurity distribution is expressed by _Vth = _VthL + ( _VthH - _VthL ) _.multidot. ( _2.delta./L ) (1). Here, L is the gate length, and δ is the distance between one end of the implantation region of the first impurity 56 and one end of the implantation region of the second impurity 57.

In order to obtain a homogeneous V _th which is not dependent on the gate _{length, V th (L-ΔL)} -V th (L) = -K · ΔL + (2δ (V thH -V thL) / L (L- ΔL)) · ΔL≡0 (2) Here, −K · ΔL represents the effect of V _th reduction due to the short channel effect that occurs when the gate length L becomes shorter.

From the equation (2), K = −2δ (V _thH −V _thL ) by selecting the conditions of the first ion implantation and the second ion implantation (dose amount, implantation energy, inclination angle of oblique ion implantation, etc.). ) / L (L-ΔL) (3) By adjusting the above-mentioned impurity distribution, it can be seen that a uniform V _th independent of the gate length L can be obtained.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. In all the drawings of the embodiments, the same or corresponding parts are designated by the same reference numerals. 2 to 9 are stacked diffusion layer type MISs according to an embodiment of the present invention.
FIG. 7 is a cross-sectional view showing the method of manufacturing the semiconductor device in the order of steps.

Stacked diffusion layer type MIS according to this embodiment
According to the method of manufacturing a semiconductor device, as shown in FIG. 2, first, the surface of a semiconductor substrate 1 such as a silicon substrate is selectively oxidized by, for example, the LOCOS method to form a selective oxide film made of, for example, a silicon dioxide film. After the (field insulating film) 2 is formed and the elements are separated from each other, a stacked diffusion layer 3 and an interlayer insulating film, which are semiconductor layers such as a polycrystalline silicon layer doped with impurities, are formed on the semiconductor substrate 1. The offset layer 4 made of an insulating film that also functions is sequentially formed. Here, the semiconductor layer such as a polycrystalline silicon layer, which is doped with impurities and which constitutes the stacked diffusion layer 3, is doped with impurities by, for example, ion implantation or diffusion after forming the semiconductor layer by the CVD method. It is formed by doping or by doping impurities when the semiconductor layer is formed by the CVD method.

Next, as shown in FIG. 3, the offset layer 4
After forming a resist pattern 5 having a predetermined shape on the upper surface, the offset layer 4 and the stacked diffusion layer 3 are selectively etched using the resist pattern 5 as a mask. Here, this etching is performed with a slight overetching so that the stacked diffusion layers 3 are completely etched in the thickness direction. Reference numeral 6 indicates a recess formed in the portion where the gate electrode is to be formed by this etching.

Next, after removing the resist pattern 5,
As shown in FIG. 4, the sidewall spacer forming insulating film 7 is formed on the entire surface by, eg, CVD.

Next, as shown in FIG. 5, the sidewall spacer forming insulating film 7 is etched in the direction perpendicular to the substrate surface by, eg, RIE to form sidewall spacers 8 on the side surfaces of the recesses 6. Here, (recess 6
2 × (width of the sidewall spacer 8) corresponds to the gate length. The steps up to this point are the same as the steps shown in FIGS. 10 to 13 in the manufacturing method of the conventional stacked diffusion layer type MIS semiconductor device described above.

Next, as shown in FIG. 6, the stacked diffusion layer 3, the offset layer 4 and the sidewall spacers 8 are used as masks in the semiconductor substrate 1 from a direction substantially perpendicular to the surface of the semiconductor substrate 1 in the direction V _th. The first ion implantation is performed using the impurity 9 that sets the value high. Where impurities 9
Specifically, for example, when the semiconductor substrate 1 is a silicon substrate, boron (B) is used, for example.

Next, as shown in FIG. 7, the stacked diffusion layer 3, the offset layer 4 and the side wall spacers 8 are used as a mask to form an oblique angle greater than 0 degree with respect to the normal line of the surface of the semiconductor substrate 1. The second ion implantation is performed using the impurity 10 that sets V _th low in the direction. In the second ion implantation, that is, the oblique ion implantation, the recess 6 is formed due to the step formed by the stacked diffusion layer 3, the offset layer 4, and the sidewall spacer 8.
In the surface portion of the semiconductor substrate 1 excluding the portion covered by the side wall spacers 8 in, the region for implanting the impurity 10 is formed narrower than the region for implanting the impurity 9 by the first ion implantation. Here, as the impurities 10, specifically, when the semiconductor substrate 1 is a silicon substrate, for example, arsenic (As) or phosphorus (P) is used.

The first ion implantation using the impurity 9 and the second ion implantation using the impurity 10 are performed in the recess 6
Under the condition that an impurity distribution satisfying the condition of the formula (3) is formed on the surface portion of the semiconductor substrate 1 except the portion covered by the sidewall spacer 8 (dose amount, implantation energy, inclination angle of oblique ion implantation, etc.). To do.

Next, as shown in FIG. 8, the surface portion of the semiconductor substrate 1 excluding the portion covered by the sidewall spacer 8 in the recess 6 is thermally oxidized to form a gate insulating film 11 such as a silicon dioxide film. After forming
A gate electrode 12 made of, for example, a polycrystalline silicon layer doped with impurities is formed on the gate insulating film 11.
Next, heat treatment is performed to diffuse the impurities in the stacked diffusion layer 3 into the semiconductor substrate 1 to form the source region 13 and the drain region 14. These gate electrodes 1
2. Source region 13 and drain region 14 cause MI
An S transistor is formed. After that, the interlayer insulating film 15 is formed on the entire surface.

When the MIS transistor is an n-channel MIS transistor, the semiconductor substrate 1 is, for example, p-type, and the source region 13 and the drain region 14 are, for example, n ⁺ -type. In the stacked diffusion layer 3 at this time. Is an n-type impurity (for example, P or As when the semiconductor substrate 1 is a silicon substrate, for example). When the MIS transistor is a p-channel MIS transistor, the semiconductor substrate 1 is, for example, n-type, the source region 13 and the drain region 14 are, for example, p ⁺ type, and the impurities in the stacked diffusion layer 3 at this time are It is a p-type impurity (for example, B when the semiconductor substrate 1 is, for example, a silicon substrate).

Next, as shown in FIG. 9, the interlayer insulating film 15 is formed.
Then, predetermined portions of the offset layer 4 are sequentially removed by etching to form the contact holes 16 and 17, and then the wirings 18 and 119 connected to the stacked diffusion layer 3 through the contact holes 16 and 17 are formed. As described above, the intended stacked diffusion layer type MIS semiconductor device is manufactured.

As described above, according to this embodiment, V _th
As the ion implantation for adjustment, the first ion implantation using the impurity 9 for increasing V _th from a direction substantially perpendicular to the surface of the semiconductor substrate 1 and the impurity 1 for lowering V _th are performed.
By performing the second ion implantation in an oblique direction with respect to the normal line of the surface of the semiconductor substrate 1 using 0, under the condition that the impurity distribution satisfying the expression (3) is formed,
It is possible to obtain a uniform V _th that does not depend on the gate length.
This prevents a decrease in V _th due to variations in gate length, facilitates lower power consumption due to reduced leakage current at the time of OFF, and secures operating characteristics in various memory circuits. The manufacturing yield of the device can be significantly improved.

Although one embodiment of the present invention has been specifically described above, the present invention is not limited to the above embodiment, and various modifications can be made based on the technical idea of the present invention. .

For example, in the above-described embodiment, after the first ion implantation is performed from a direction substantially perpendicular to the surface of the semiconductor substrate 1, it is oblique from the normal to the surface of the semiconductor substrate 1. The second ion implantation is performed, but the second
The first ion implantation may be performed after the ion implantation of.

[0036]

As described above, according to the present invention,
The ion implantation for adjusting the threshold voltage is performed from a direction substantially perpendicular to the surface of the semiconductor substrate. The first ion implantation using the first impurity for increasing the threshold voltage and the surface of the semiconductor substrate are performed. Due to the second ion implantation using the second impurity for lowering the threshold voltage, which is performed from a direction that forms an angle of at least greater than 0 degree with respect to the normal line, variation in the gate length of the MIS transistor may occur. It is possible to prevent the threshold voltage V _th from lowering, thereby facilitating the reduction of power consumption due to the reduction of the leakage current at the time of off and the securing of the operating characteristics in various memory circuits, and the manufacture of the stacked diffusion layer type MIS semiconductor device. The yield can be improved.

[Brief description of drawings]

FIG. 1 is a schematic diagram for explaining the principle of the present invention.

FIG. 2 is a stacked diffusion layer type M according to an embodiment of the present invention.
FIG. 9 is a cross-sectional view for explaining the method for manufacturing the IS semiconductor device.

FIG. 3 is a stacked diffusion layer type M according to an embodiment of the present invention.
FIG. 9 is a cross-sectional view for explaining the method for manufacturing the IS semiconductor device.

FIG. 4 is a stacked diffusion layer type M according to an embodiment of the present invention.
FIG. 9 is a cross-sectional view for explaining the method for manufacturing the IS semiconductor device.

FIG. 5 is a stacked diffusion layer type M according to an embodiment of the present invention.
FIG. 9 is a cross-sectional view for explaining the method for manufacturing the IS semiconductor device.

FIG. 6 is a stacked diffusion layer type M according to an embodiment of the present invention.
FIG. 9 is a cross-sectional view for explaining the method for manufacturing the IS semiconductor device.

FIG. 7 is a stacked diffusion layer type M according to an embodiment of the present invention.
FIG. 9 is a cross-sectional view for explaining the method for manufacturing the IS semiconductor device.

FIG. 8 is a stacked diffusion layer type M according to an embodiment of the present invention.
FIG. 9 is a cross-sectional view for explaining the method for manufacturing the IS semiconductor device.

FIG. 9 is a stacked diffusion layer type M according to an embodiment of the present invention.
FIG. 9 is a cross-sectional view for explaining the method for manufacturing the IS semiconductor device.

FIG. 10 is a cross-sectional view for explaining a method of manufacturing a conventional stacked diffusion layer type MIS semiconductor device.

FIG. 11 is a cross-sectional view for explaining a method of manufacturing a conventional stacked diffusion layer type MIS semiconductor device.

FIG. 12 is a cross-sectional view for explaining the method of manufacturing the conventional stacked diffusion layer type MIS semiconductor device.

FIG. 13 is a cross-sectional view for explaining the method of manufacturing the conventional stacked diffusion layer type MIS semiconductor device.

FIG. 14 is a cross-sectional view for explaining the method of manufacturing the conventional stacked diffusion layer type MIS semiconductor device.

FIG. 15 is a cross-sectional view for explaining the method of manufacturing the conventional stacked diffusion layer type MIS semiconductor device.

FIG. 16 is a cross-sectional view for explaining the method of manufacturing the conventional stacked diffusion layer type MIS semiconductor device.

[Explanation of symbols]

1 Semiconductor substrate 3 Stacked diffusion layer 4 Offset layer 8 Sidewall spacer 9,10 impurities 11 Gate insulating film 12 Gate electrode 13 Source area 14 drain region

Claims (2)

(57) [Claims] 1. A step of sequentially forming a stacked diffusion layer and an offset layer covering the stacked diffusion layer on a semiconductor substrate, and removing at least a portion of the stacked diffusion layer and the offset layer where a gate electrode is to be formed. Forming a concave portion, forming a sidewall spacer on a side surface of the concave portion, and using the stacked diffusion layer, the offset layer and the sidewall spacer as a mask, a threshold voltage of a MIS transistor in the semiconductor substrate. A step of performing ion implantation for adjustment, a step of forming a gate insulating film on the semiconductor substrate except a portion of the recess covered with the sidewall spacers, and a step of forming a gate electrode on the gate insulating film. The impurities in the stacked diffusion layer are diffused into the semiconductor substrate to A step of forming a source region and a drain region, wherein the ion implantation for adjusting the threshold voltage is performed from a direction substantially perpendicular to the surface of the semiconductor substrate. The first ion implantation using the first impurity for increasing the threshold voltage performed and the threshold voltage performed from a direction forming an angle of at least greater than 0 degree with respect to the normal to the surface of the semiconductor substrate. A method of manufacturing a stacked diffusion layer type MIS semiconductor device, which comprises a second ion implantation using a second impurity that lowers the impurity concentration. 2. The distance between the one end of the first impurity implantation region and the one end of the second impurity implantation region is δ, and the distance between the first impurity implantation region and the second impurity implantation region is δ. the threshold voltage V _thL, the first threshold voltage of the implantation region of impurity and V _thH, the gate length L of the MIS transistor of reduction in the threshold voltage due to the short channel effect that occurs when the shortened by ΔL When the effect is expressed by −K · ΔL, the above condition is satisfied under the condition that the impurity distribution of the first impurity and the second impurity satisfies K = −2δ (V _thH −V _thL ) / L (L−ΔL). The first ion implantation and the second ion implantation are performed.
A method for manufacturing the stacked diffusion layer type MIS semiconductor device described.