JPH0529624A - Thin film transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To increase an ON current with an OFF current kept at a low level by making a gate insulating film of a thin film transistor(TFT) thick in the vicinity of a drain, and making the film thin in the other region. CONSTITUTION:A silicon oxide film 2 is formed on a silicon substrate 1. A polycrystalline silicon film is deposited on the film 2, and boron ions are implanted. The gate electrode of a thin film transistor(TFT) is formed by selective etching. A part of the silicon oxide film is made to remain at the upper surface of the gate electrode 3 on the side of the TFT, and first gate insulating film 4 is formed. Then, a silicon oxide film is deposited on the surface containing the gate electrode 3 and the gate insulating film 4, and second gate insulating film 5 is formed. Thereafter, a polycrystalline silicon film 6 wherein phosphorus is introduced for the channel of the TFT is deposited on the gate insulating film 5. With a photoresist mask film on the gate electrode 3 as a mask, ions are implanted into the polycrystalline silicon film 6, and a source region 7 and a drain region 8 are formed.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a thin film transistor (Th
In Film Transistor), and particularly to a thin film transistor used as a load element of a static RAM.

[0002]

2. Description of the Related Art As shown in FIG. 3, a conventional thin film transistor (hereinafter referred to as TFT) has a silicon oxide film 2 having a thickness of 50 to 100 nm formed on a silicon 1 by a CVD method, and the silicon oxide film 2 is formed on the silicon oxide film 2. Then, the gate electrode 3 having a thickness of 100 to 150 nm is selectively formed. Next, the gate electrode 3
A silicon oxide film on the surface including
The gate insulating film 5 is formed by depositing it to a thickness of 0 nm. Next, a polycrystalline silicon film 6 is deposited to a thickness of 20 to 40 nm on the gate insulating film 5 by a CVD method to form the gate electrode 3
Boron ions are selectively ion-implanted into a desired region of the polycrystalline silicon film 6 using a photoresist film (not shown) formed by patterning as a mask to form a source region 7 and a drain region 8 of the TFT. .

After that, an interlayer insulating film, a metal film for wiring, etc. are formed to form a TFT.

[0004]

This conventional TFT is
When used as a load of SRAM, it is required to reduce off current and increase on current as much as possible. For example, Technical Report of IEICE, Vol. 89,
No. 67, pp. 1 to 6 (SDM89-19), it is effective to make the gate insulating film thin in order to increase the on-current, while to reduce the off-current. Although it is effective to increase the thickness of the gate insulating film for alleviating the electric field at the drain end, there is a problem that these contradictory characteristics cannot be satisfied at the same time.

[0005]

A TFT of the present invention comprises a gate electrode provided on an insulating film provided on a semiconductor substrate, a gate insulating film provided on a surface including the gate electrode, and the gate electrode. In a thin film transistor having a semiconductor film provided on the gate insulating film in a region including at least an upper surface, and a source and drain region provided in the semiconductor film, the gate insulation on a drain region side of a channel region on the upper surface of the gate electrode It is configured by forming the film thicker than the source region side.

A method of manufacturing a TFT according to the present invention comprises a step of depositing a polycrystalline silicon film containing impurities on an insulating film provided on a semiconductor substrate and patterning the same to form a gate electrode, and a surface including the gate electrode. Forming a first gate insulating film on the gate electrode and patterning the first gate insulating film to leave the first gate insulating film only in a region including one end of the upper surface of the gate electrode and a side surface adjacent to the one end, and the first gate insulating film. Forming a second gate insulating film on the surface including the film and the exposed gate electrode; depositing and patterning a polycrystalline silicon film on the second gate insulating film; Selectively introducing impurities into the first and second gate insulating films to form a drain region on the stacked region and an opposing source region on only the second gate insulating film. Nde constructed.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described with reference to the drawings.

FIGS. 1A and 1B are cross-sectional views of a semiconductor chip shown in the order of steps for explaining the first embodiment of the present invention.

First, as shown in FIG. 1A, a silicon oxide film 2 having a thickness of 50 to 100 nm is formed on a silicon substrate 1 by a CVD method, and a polycrystalline silicon film is formed on the silicon oxide film 2. It is deposited to a thickness of 100 to 150 nm, boron is ion-implanted, and selectively etched to form the gate electrode 3 of the TFT. Next, a 30 nm-thickness silicon oxide film is deposited on the surface including the gate electrode 3 by the CVD method and then patterned to leave a part of the silicon oxide film on the upper surface of the gate electrode 3 on the drain side of the TFT, and the first oxide film The gate insulating film 4 is formed.

Next, as shown in FIG. 1B, a silicon oxide film having a thickness of 20 nm is deposited on the surface including the gate electrode 3 and the gate insulating film 4 by the CVD method to form the second gate insulating film 5. Form. Next, a TFT is formed on the gate insulating film 5.
The polycrystalline silicon film 6 into which phosphorus is introduced for the channel portion of is deposited to a thickness of 20 to 40 nm and patterned on the gate electrode 3 using a photoresist film (not shown) provided as a mask to form the polycrystalline silicon. Boron is ion-implanted into the film 6 to form a source region 7 and a drain region 8 of the TFT. After that, an interlayer insulating film, a metal film for wiring, etc. are formed and TF
Configure T.

2 (a) and 2 (b) are sectional views of the semiconductor chip in the order of steps for explaining the second embodiment of the present invention.

As shown in FIG. 2A, the silicon oxide film 2 is provided on the silicon substrate 1 and the gate electrode 3 is formed on the silicon oxide film 2 in the same process as in the first embodiment. Then, the surface including the gate electrode 3 is formed by the CVD method.
After depositing a silicon oxide film having a thickness of 0 to 60 nm, the gate insulating film 5a is formed by wet etching to remove the gate electrode 3 from the silicon oxide film on the upper surface except for the drain side by a thickness of 20 to 30 nm. . In this case, the gate insulating film can be formed at once by the CVD method, so that the process is simplified as compared with the first embodiment.

Next, as shown in FIG. 2B, after the polycrystalline silicon film 6 is formed on the gate insulating film 5a, boron is selectively ion-implanted into the polycrystalline silicon film 6 to form the source regions 7 and The drain region 8 is formed. Here, the edge of the drain region 8 is 0.2 to 0.2 mm from the edge of the gate electrode 3.
It is also possible to employ an offset structure separated by 0.3 μm. In this case, the off current can be further reduced as compared with the first embodiment.

[0014]

As described above, the present invention increases the on-current while keeping the off-current low by making the gate insulating film of the TFT thick near the drain and thin in the other regions. You can

[Brief description of drawings]

FIG. 1 is a sectional view of a first embodiment of the present invention.

2A to 2D are sectional views of a semiconductor chip, which are shown in the order of steps for explaining a second embodiment of the present invention.

FIG. 3 is a sectional view of a semiconductor chip showing an example of a conventional thin film transistor.

[Explanation of symbols]

1 Silicon substrate 2 Silicon oxide film 3 Gate electrode 4,5,5a Gate insulating film 6 Polycrystalline silicon film 7 Source area 8 drain region

Claims (2)

[Claims] 1. A gate electrode provided on an insulating film provided on a semiconductor substrate, a gate insulating film provided on a surface including the gate electrode, and the gate insulating in a region including at least an upper surface of the gate electrode. In a thin film transistor having a semiconductor film provided on a film and source and drain regions provided on the semiconductor film, the thickness of the gate insulating film on the drain region side of the channel region on the upper surface of the gate electrode is thicker than that on the source region side. A thin film transistor, which is formed. 2. A step of depositing and patterning a polycrystalline silicon film containing an impurity on an insulating film provided on a semiconductor substrate to form a gate electrode, and a first gate insulating film on a surface including the gate electrode. Forming and patterning, and leaving the first gate insulating film only in a region including one end of the upper surface of the gate electrode and a side surface adjacent to the upper surface, and the first gate insulating film and the exposed gate electrode. A step of forming a second gate insulating film on the surface including, and depositing and patterning a polycrystalline silicon film on the second gate insulating film and selectively introducing impurities into the polycrystalline silicon film. And forming a drain region on the stacked region of the first and second gate insulating films and a source region on the opposite region of only the second gate insulating film. Method of manufacturing a register.