JP2000040817A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce occupied areas of a subcontact region and a source region in a transistor. SOLUTION: A subcontact region 109 is formed on a recessed part of a semiconductor substrate and is separated from a source region 108 by using a side wall spacer 106 formed on a step-difference on the semiconductor substrate. It is preferable that the depth of the recessed part of the substrate is greater than that of an impurity diffusion layer of a source. Thereby diffusion of impurities from the subcontact region to the source region can be prevented, and an occupied area of the subcontact region in a transistor can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a source region of a transistor and a sub-contact region having a substrate potential are adjacent to each other, and the source region and the sub-contact region have a common potential, and a method of manufacturing the same.

[0002]

2. Description of the Related Art A conventional semiconductor device will be described with reference to a layout diagram shown in FIG. In FIG. 3, reference numeral 301 denotes a field (active) region of a transistor, 302 denotes a gate electrode, 303 denotes an impurity diffusion layer of the first conductivity type serving as a source and a drain of the transistor, and 304 denotes connection to a well (semiconductor substrate) of the transistor. 305 is a contact hole, 306 is a drain wiring of a transistor, 30
Reference numeral 7 denotes a common wiring of a source and a sub contact of the transistor, and reference numeral 308 denotes a gate wiring of the transistor.

In order to reduce the area of the transistor, a sub-contact is formed adjacent to the source region of the transistor, and the source and the sub-contact have a common potential.
A margin 309 between the gate electrode 302 and the sub-contact region 304 or a margin 310 of the contact hole with respect to the sub-contact region is required, and it is necessary to consider only the alignment margin of the contact hole with respect to the gate electrode. Thus, the area of the source region of the transistor is increased.

FIG. 4 is a sectional view taken along the line AA 'of FIG. In FIG. 4, reference numeral 401 denotes a semiconductor substrate on which a well of the second conductivity type is formed, 402 denotes an element isolation insulating film, 403 denotes a gate insulating film, 404 denotes a gate electrode, 405 denotes a sidewall spacer, and 406 denotes a high concentration of the first conductivity type. A drain region formed by impurities, a source region 407 formed by high-concentration impurities of the first conductivity type, and a gate region 408 formed by a second conductivity type high-concentration impurity layer for connection with a well (semiconductor substrate). 409 is an interlayer insulating film, and 410 is a metal wiring layer.

[0005]

However, in a semiconductor device using the conventional technique, a sub-contact is formed adjacent to the source region of the transistor in order to reduce the area of the transistor. The gate electrode and the sub-contact region are used to prevent the transistor from being affected by impurity diffusion from the conduction-type sub-contact region to the first conduction-type source region (VTH shift, increase in off-leakage, decrease in on-current, etc.). A margin between them or a contact hole with respect to the sub-contact region is required. As a result, the area of the source region of the transistor is increased.

The diffusion of impurities from the sub-contact region of the second conductivity type to the source region of the first conductivity type is remarkably observed when a refractory metal silicide layer is formed on the impurity diffusion layer. This is a phenomenon caused by rapid diffusion of impurities in the refractory metal silicide layer.

The present invention has been made in order to solve such a problem. It is an object of the present invention to provide a semiconductor device in which a source region of a transistor is adjacent to a sub-contact region having a substrate potential, and the source region and the sub-region are adjacent to each other. An object of the present invention is to provide a semiconductor device and a method for manufacturing the same, which can reduce the area occupied by a sub-contact region and the area occupied by a source region in a transistor whose contact region has a common potential.

[0008]

According to a semiconductor device and a method of manufacturing the same of the present invention, a source region of a transistor and a subcontact region having a substrate potential are adjacent to each other, and the source region and the subcontact region have a common potential. In a semiconductor device, a sub-contact region of a transistor is formed in a concave portion of a semiconductor substrate.

Alternatively, in a semiconductor device in which a source region of a transistor and a sub-contact region having a substrate potential are adjacent to each other and the source region and the sub-contact region have a common potential, the depth of the concave portion of the semiconductor substrate is
It is characterized by being larger than the depth of the impurity diffusion layer of the source.

Alternatively, in a semiconductor device in which a source region of a transistor and a sub-contact region having a substrate potential are adjacent to each other and the source region and the sub-contact region are at a common potential, a recess of the semiconductor substrate and a surface of the semiconductor substrate may be formed. Is characterized in that a sidewall space is formed in the step portion.

Alternatively, in a semiconductor device in which a source region of a transistor and a sub-contact region having a substrate potential are adjacent to each other and the source region and the sub-contact region have a common potential, a refractory metal silicide may be formed on the semiconductor substrate. It is characterized in that a layer is formed.

Alternatively, in a method of manufacturing a semiconductor device in which a source region of a transistor and a sub-contact region having a substrate potential are adjacent to each other and the source region and the sub-contact region have a common potential, the sub-contact is formed by photolithography and etching. A step of removing the semiconductor substrate in a region to be formed, and a step of simultaneously forming a sidewall spacer on a side wall spacer and a gate electrode side wall of a step portion between the region to be a sub contact and the semiconductor substrate. .

[0013]

According to the above structure of the present invention, since the sub-contact region and the source region are separated by the step on the semiconductor substrate and the side wall spacer formed of the insulating film at the step, the second conductive region is formed. Diffusion of impurities from the sub-contact region of the mold to the source region of the first conductivity type can be prevented.

Therefore, the allowance between the gate electrode and the sub-contact region or the allowance of the contact hole with respect to the source region can be reduced. As a result, the source region of the transistor and the sub-contact region having the substrate potential are adjacent to each other. In a transistor in which the source region and the sub-contact region have a common potential, the occupied area of the sub-contact region and the occupied area of the source region can be reduced.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A typical embodiment of the present invention will be described below with reference to the sectional view shown in FIG.

In FIG. 1, reference numeral 101 denotes a semiconductor substrate on which a well of the second conductivity type is formed, 102 denotes an element isolation insulating film, 103 denotes a gate insulating film, 104 denotes a gate electrode, and 105 denotes a side wall spacer formed of an insulating film. , 106 are sidewall spacers formed of an insulating film at a step portion on the semiconductor substrate, 107 is a drain region formed of the first conductivity type high-concentration impurity, and 108 is a source formed of the first conductivity type high-concentration impurity. A region 109 is a sub-contact region of the second conductivity type, 110 is an interlayer insulating film, and 111 is a metal wiring layer. The second conductive type sub-contact region 109 is formed in a recess of the semiconductor substrate, and the first conductive type source region 108 and the second conductive type sub-contact region 109 are formed by the side wall spacer 106.
Are separated by The depth (step on the semiconductor substrate) 112 of the concave region of the semiconductor substrate is larger than the depth 113 of the source region of the first conductivity type.

By using the above structure, the second conductive type sub-contact region 109 and the first conductive type source region 108 are completely separated from each other. Impurity diffusion to the first conductivity type source region can be prevented.

Even if a refractory metal silicide layer is formed in a self-aligned manner on the surface of the diffusion layer of the semiconductor device, the refractory metal silicide layer on the source region and the refractory metal silicide layer on the sub-contact region are formed by the sidewall spacers 106. Since the refractory metal silicide layer can be separated, impurity diffusion caused by the refractory metal silicide can be prevented.

Next, one embodiment of the manufacturing method of the present invention is shown in FIG.
This will be described with reference to the process cross-sectional views shown in FIGS.

First, after an element isolation insulating film 202 is formed on the semiconductor substrate 201 on which the second conductivity type well is formed by using the LOCOS method or the like, a gate insulating film 203 is formed by thermal oxidation or the like. Next, chemical vapor deposition of polycrystalline silicon or the like (C
VD), and a gate electrode 204 is formed by patterning using photolithography and etching. FIG. 2A shows this state.

Next, the photoresist 205 is left in a region other than the sub-contact region 206 for making connection to the well (semiconductor substrate) of the transistor by photolithography, and the gate insulating film and the semiconductor substrate are removed by etching. As a method of etching the gate insulating film, wet etching using hydrofluoric acid is used, and as a method of etching the semiconductor substrate, a degree of vacuum of about 0.1 torr, CH
Dry etching of anisotropic RIE using F3 and CF4 is mentioned. FIG. 2B shows this state.

Next, a sidewall spacer 207 for separating the gate electrode from the semiconductor substrate, and a sidewall spacer 208 at the step portion between the sub-contact region 206 and the surface of the semiconductor substrate are formed by forming an oxide film by a CVD method and forming an oxide film. It is formed in a self-aligned manner by isotropic whole surface etching. Then, the first conductivity type impurity diffusion layer regions serving as the source and the drain are patterned by photolithography, and the first conductivity type drain region 209 and the first conductivity type source region 210 are formed by ion implantation. The source and drain regions are a photoresist,
It is formed in a self-aligned manner by the gate electrode, the sidewall spacer, and the element isolation insulating film.

Next, the photoresist is left in a region other than the sub-contact region for connection with the well (semiconductor substrate) of the transistor by photolithography, and the second conductivity type sub-contact region 21 is formed by ion implantation.
Form one. The sub-contact region is formed in a self-aligned manner by a photoresist, a sidewall spacer, and an element isolation insulating film. FIG. 2C shows this state.

When a high melting point metal silicide layer is formed after the removal of the photoresist, a high melting point metal such as titanium is formed on the entire surface by a sputtering method or the like. next,
After performing lamp annealing at a temperature of 700 ° C. to 800 ° C. for several tens of seconds, only the high melting point metal on the insulating film is selectively removed by an etching solution formed by ammonia, hydrogen peroxide solution and water. A refractory metal silicide is formed only on a semiconductor substrate.

Then, by forming the interlayer insulating film and the metal wiring as usual, it is possible to obtain the structure shown in the sectional view of FIG.

By using the above manufacturing method, the second conductive type sub-contact region 211 and the first conductive type source region 210 are completely separated from each other. Impurity diffusion into the first conductivity type source region can be prevented.

Even if a refractory metal silicide layer is formed in a self-aligned manner on the surface of the diffusion layer of the semiconductor device, the sub-contact region 206 and the side wall spacer 208 at the stepped portion on the semiconductor substrate can be used to form a semiconductor device on the source region. Since the high melting point metal silicide layer and the high melting point metal silicide layer on the sub-contact region can be separated from each other, diffusion of impurities due to the high melting point metal silicide can be prevented.

Therefore, in the transistor in which the source region of the transistor and the sub-contact region having the substrate potential are adjacent to each other and the source region and the sub-contact region have a common potential, the area occupied by the sub-contact region can be reduced. it can.

[0029]

According to the structure of the present invention, since the sub-contact region and the source region are separated by the step on the semiconductor substrate and the side wall spacer formed of the insulating film at the step, the second conductive layer is formed. Diffusion of impurities from the sub-contact region of the mold to the source region of the first conductivity type can be prevented.

Therefore, the allowance between the gate electrode and the sub-contact region or the allowance for the contact hole with respect to the source region can be reduced. As a result, the source region of the transistor and the sub-contact region having the substrate potential are adjacent to each other. In a transistor in which the source region and the sub-contact region have a common potential, it is possible to provide a semiconductor device and a method of manufacturing the same, which can reduce the area occupied by the sub-contact region.

[Brief description of the drawings]

FIG. 1 is a diagram showing one embodiment of a semiconductor device of the present invention.

FIG. 2 is a process sectional view showing one embodiment of the semiconductor device of the present invention.

FIG. 3 is a layout diagram showing a conventional semiconductor device.

FIG. 4 is a diagram showing a conventional semiconductor device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 101 Semiconductor substrate 102 Element isolation insulating film 103 Gate insulating film 104 Gate electrode 105 Side wall spacer 106 Side wall spacer 107 Drain 108 Source 109 Subcontact 110 Interlayer insulating film 111 Metal wiring layer 112 Step on semiconductor substrate 113 Source diffusion layer Depth 201 Semiconductor substrate 202 Element isolation insulating film 203 Gate insulating film 204 Gate electrode 205 Photoresist 206 Subcontact region 207 Sidewall spacer 208 Sidewall spacer 209 Drain 210 Source 211 Subcontact 301 Field (active) 302 Gate electrode 303 Source, Drain 304 Sub contact 305 Contact hole 306 Drain wiring 307 Source, sub contact Common wiring 308 gate wiring 309 alignment allowance between the sub-contact and the gate electrode 310 alignment allowance between the sub-contact and the contact hole of the sub-contact 401 semiconductor substrate 402 element isolation insulating film 403 gate insulating film 404 gate electrode 405 sidewall spacer 406 Drain 407 Source 408 Subcontact 409 Interlayer insulating film 410 Metal wiring layer

Claims (5)

[Claims] In a semiconductor device in which a source region of a transistor and a sub-contact region having a substrate potential are adjacent to each other and the source region and the sub-contact region are at a common potential, the sub-contact region of the transistor is formed of a semiconductor substrate. A semiconductor device formed in a recess. 2. The semiconductor device according to claim 1, wherein a depth of the concave portion of the substrate is larger than a depth of the impurity diffusion layer of the source. 3. The semiconductor device according to claim 1, wherein a sidewall space is formed at a step between the concave portion of the substrate and a surface of the semiconductor substrate. 4. The semiconductor device according to claim 3, wherein a refractory metal silicide layer is formed on the substrate. 5. A method for manufacturing a semiconductor device in which a source region of a transistor and a sub-contact region having a substrate potential are adjacent to each other and the source region and the sub-contact region have a common potential. A step of removing the semiconductor substrate in a region to be formed, and a step of simultaneously forming a sidewall spacer on a side wall spacer and a gate electrode side wall of a step portion between the region to be a sub contact and the semiconductor substrate. A method for manufacturing a semiconductor device.