JPH07283300A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To suppress local oxidation of an end part of an element isolation region by a field shield and to reduce the width of the element isolation region. CONSTITUTION:The width of a shield electrode 4 is reduced by side etching and a side-wall insolation film consisting of a silicon nitriding film 7 and a silicon oxidation film 8 is formed inside a recessed part formed thereby. The silicon nitriding film 7 coveres a silicon substrate 1 under the end part of a field shield element isolation structure, thus allowing suppression of local oxidation of the silicon substrate 1 of that part at the time of later gate oxidation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device having element isolation by a field shield element isolation structure and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, with the demand for higher integration of semiconductor devices, the conventional LOCOS element isolation method has been miniaturized to a submicron level due to problems such as bird's beak and lateral diffusion of impurities from a channel stopper layer. It is becoming difficult to apply it to other devices. So LO
In place of the COS method, element isolation technology using a field shield element isolation structure has been attracting attention.

In the element isolation technique using this field shield element isolation structure, a shield electrode is formed on an element isolation region of a silicon substrate via a silicon oxide film for capacitive coupling (hereinafter referred to as "shield gate oxide film"). Then, by fixing the potential of the shield electrode to the GND potential, for example, the potential from the gate wiring passing over the shield electrode is cut off to prevent the conduction of the parasitic MOS transistor.

Therefore, the element isolation technique using the field shield element isolation structure has no problems such as bird's beak and lateral diffusion of impurities from the channel stopper layer unlike the conventional LOCOS method, and is noted as suitable for miniaturization. Has been done.

For example, IEDM-88, pp246-249 "Fully plan
It has been reported that, in the arized 0.5 μm technorogies for 16Mb DRAM ", the element isolation by the field shield element isolation structure is applied to the 16M DRAM to obtain good element isolation characteristics.

FIG. 3 is a schematic sectional view showing a method of forming a conventional field shield element isolation structure in the order of steps.

First, as shown in FIG. 3A, a shield gate oxide film 2 is formed on a silicon substrate 21 by a thermal oxidation method.
2 is formed to a film thickness of about 50 nm, and then ion implantation 23
By means of adding boron to the silicon substrate 21 at 1 × 10 ¹² / c
Inject about m ² . The boron ion implantation 22 is for adjusting the threshold voltages of the MOS transistor formed in the element region and the parasitic MOS transistor formed in the element isolation region, respectively.

Next, as shown in FIG. 3 (b), a polycrystalline silicon film 24 doped with phosphorus is formed to a thickness of about 200 nm by a method such as CVD, and a silicon oxide film 25 of 300 to 300 nm is further formed. It is formed to a thickness of about 400 nm. The polycrystalline silicon film 24 will be a shield electrode for performing element isolation later.

Next, a photoresist 26 is applied to the entire surface and then patterned by a lithography technique so that the photoresist 26 covers only the element isolation region.

Next, the silicon oxide film 25 and the polycrystalline silicon film 24 are etched by the anisotropic etching method such as RIE using the photoresist 26 as a mask to process the polycrystalline silicon film 24 into the shape of the shield electrode.

Next, as shown in FIG. 3C, a silicon oxide film having a thickness of 100 to 300 nm is formed on the entire surface by CVD or the like.
After forming the silicon oxide film to a certain thickness, RIE is performed on the silicon oxide film.
Anisotropic etching is performed by, for example, the polycrystalline silicon film 2
Sidewall spacers 27 are formed on both sides of No. 4.
At this time, as shown in the figure, the shield gate oxide film 22 in the element region is also removed.

Next, as shown in FIG. 3D, a gate oxide film 29 is formed on the surface portion of the silicon substrate 21 in the element region by thermal oxidation. At this time, the silicon substrate 21 is also oxidized at the end of the element isolation region, so that a local oxide film 28 is formed below the sidewall spacer 27 at the end of the element isolation region.

[0013]

As described above, the field shield element isolation structure originally has the advantage that bird's beak does not occur unlike the LOCOS method.
Actually, as described above, when the element isolation region is formed by the field shield element isolation structure and then thermal oxidation is performed, a local oxide film 28 is formed at the end of the element isolation region as shown in FIG. 3D. Therefore, as in the case of bird's beak of the LOCOS method, there is a problem that the width of the element isolation region is expanded. As a result, there is a problem of the narrow channel effect that the gate width of the MOS transistor formed in the element region is reduced and the threshold voltage rises.
Further, there is a problem that the local oxidation of the end portion of the element isolation region causes a crystal defect in the silicon substrate 21 and reduces the reliability of the shield gate oxide film 22.

Further, in the conventional field shield element isolation structure, the side wall spacer 27 as shown in FIG. 3 is used to insulate the side surface of the polycrystalline silicon film 24 which is the shield electrode. In such a structure, the sidewall spacer 27 is formed in the width of the polycrystalline silicon film 24 determined by the limit of the lithography technique.
The width of the element isolation region becomes the total width including the width of the element isolation region, and the width of the element isolation region is considerably increased. As a result, the degree of integration of the device could not be increased.

Therefore, an object of the present invention is to suppress local oxidation at the end of the element isolation region due to the field shield element isolation structure and to reduce the width of the element isolation region as compared with the conventional case. A semiconductor device and a method for manufacturing the same are provided.

[0016]

In order to solve the above-mentioned problems, the present invention provides a semiconductor device in which element isolation is performed by a shield electrode formed on a semiconductor substrate with a shield gate oxide film interposed therebetween. A cap insulating film is formed to be relatively larger than the shield electrode, and the shield electrode is formed in the recess surrounded by the cap insulating film, the shield electrode, and the shield gate oxide film via an oxidation resistant film. Side wall insulating film is formed.

In one aspect of the present invention, the oxidation resistant film is a silicon nitride film.

In one aspect of the present invention, the sidewall insulating film is a silicon oxide film.

In one aspect of the present invention, the cap insulating film is a silicon oxide film.

In one aspect of the present invention, the cap insulating film is a silicon nitride film.

In one aspect of the present invention, the shield electrode is a polycrystalline silicon film.

According to the method of manufacturing a semiconductor device of the present invention, a step of sequentially forming a shield gate oxide film, a polycrystalline silicon film, and a cap insulating film on a semiconductor substrate, and a pattern of the cap insulating film remaining in an element isolation region are left. And a step of selectively removing the cap insulating film, and a step of anisotropically etching the polycrystalline silicon film so that the pattern of the polycrystalline silicon film remains under the pattern of the cap insulating film, A step of side-etching the pattern of the polycrystalline silicon film by isotropic etching, and a step of forming a silicon nitride film as an oxidation resistant film over the entire surface including the surface of the side-etched portion of the polycrystalline silicon film. , A silicon oxide film is formed on the entire surface so that the side-etched portion of the polycrystalline silicon film is embedded. Has a degree, the silicon oxide film, the silicon nitride film and the shield gate oxide film is anisotropically etched, and forming a sidewall insulation film on a side of the polycrystalline silicon film.

In one aspect of the present invention, a silicon oxide film is formed as the cap insulating film.

In one aspect of the present invention, a silicon nitride film is formed as the cap insulating film.

[0025]

In the present invention, the shield gate oxide film at the end of the field shield element isolation structure is covered with an oxidation resistant film such as a silicon nitride film to suppress the oxidation of the semiconductor substrate thereunder.

Further, the structure in which the side wall insulating film is embedded in the recess formed by side etching the shield electrode suppresses the expansion of the width of the element isolation region.

[0027]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to embodiments with reference to FIGS.

FIG. 1 is a schematic sectional view showing a semiconductor device having a field shield element isolation structure according to an embodiment of the present invention.

In the figure, a polycrystalline silicon film 4 is formed in the element isolation region of the silicon substrate 1 via a shield gate oxide film 2, and the polycrystalline silicon film 4 is set to a predetermined potential such as GND. The element is separated by fixing. The upper surface of the polycrystalline silicon film 4 is covered with the silicon oxide film 5, and the side surfaces thereof are covered with the silicon oxide film 8 via the silicon nitride film 7 so as not to be electrically connected to the gate wiring 10. At this time, the width of the polycrystalline silicon film 4 is smaller than the width of the silicon oxide film 5 which is the cap insulating film, and is surrounded by the silicon oxide film 5, the polycrystalline silicon film 4 and the shield gate oxide film 2. A silicon oxide film 8 serving as a sidewall insulating film is formed in the recess via a silicon nitride film 7. On the other hand, in the element region surrounded by the element isolation region, the gate electrode 10 of the MOS transistor is formed via the gate oxide film 9 formed by the thermal oxidation method.
And the impurity diffusion layer 11 serving as the source / drain is formed in the silicon substrate 1. The impurity diffusion layer 11 is connected to the metal wiring 13 through a contact hole formed in the interlayer insulating film 12.

Next, a method of manufacturing the semiconductor device according to this embodiment will be described with reference to FIG.

First, as shown in FIG. 2A, a shield gate oxide film 2 having a thickness of 50 to 100 nm is formed on the surface of a silicon substrate 1 containing boron and having a specific resistance of 1 to 12 Ωcm by a thermal oxidation method. Form. And energy 30 to 50 KeV, dose amount 1 × 10 ^{12 to} 5 × 10 ¹² /
Boron ion implantation 3 is performed on the silicon substrate 1 under the condition of about cm ² . The boron ion implantation 3 is for adjusting the threshold voltage of each of the MOS transistor formed in the element region and the parasitic MOS transistor formed in the element isolation region.

Next, as shown in FIG. 2B, 2 × 10 ^{20 to} 6 × is formed by a method such as CVD or plasma CVD.
A polycrystalline silicon film 4 doped with phosphorus at a concentration of about 10 ²⁰ / cm ³ is formed to a thickness of about 100 to 200 nm,
Further, the silicon oxide film 5 is formed to a thickness of about 150 to 300 nm. The polycrystalline silicon film 4 will later become a shield electrode.

Next, a photoresist 6 is applied to the entire surface and then patterned by a lithography technique so that the photoresist 6 covers only the element isolation region. At this time, the width w of the photoresist 6 is 0.2-0.
It is about 8 μm.

Next, as shown in FIG. 2C, RIE,
ECR (Electron Cyclotron Resonance) Silicon oxide film 5 using photoresist 6 as a mask by anisotropic etching such as plasma etching or low temperature etching.
After etching, the photoresist 6 is removed by a method such as ashing.

Next, the polycrystalline silicon film 4 is anisotropically etched using the silicon oxide film 5 as a mask. At this time, using a parallel plate type reactive ion etching device, CF ₄ ,
A gas such as SF ₆ is used to control the anisotropy of etching by the gas pressure. To increase the anisotropy, the gas pressure is set to 1 Torr or less and the anisotropy is performed for about 30 to 90 seconds.

Next, the polycrystalline silicon film 4 is side-etched by isotropic etching. As shown in the figure, the polycrystalline silicon film 4 has a thickness of 0.
The thickness is made to be about 05 to 0.1 μm. The isotropic etching, in this example, again using a parallel plate type reactive ion etching apparatus, using gases such as CF _4, SF _6, and the gas pressure and 1Torr or more, 5 to 2
The time is about 0 sec.

That is, in this embodiment, the polycrystalline silicon film 4 is used.
The parallel plate type reactive ion etching apparatus is used for the etching of 1., and anisotropic etching and isotropic etching are continuously performed by controlling the pressure of the reaction gas such as CF ₄ and SF ₆ . Thus, the process for processing the polycrystalline silicon film 4 into a predetermined shape is simplified.

Next, as shown in FIG. 2 (d), the silicon nitride film 7 is formed into 20 by CVD or plasma CVD.
After being formed to a thickness of about 50 nm, the silicon oxide film 8 is formed.
To a thickness of about 150 to 200 nm.

Next, as shown in FIG. 2 (e), RIE,
The silicon oxide film 8 and the silicon nitride film 7 are anisotropically etched by ECR plasma etching, low temperature etching or the like until the surface of the silicon substrate 1 is exposed to form a sidewall insulating film. At this time, since the silicon nitride film 7 is thin, a relatively large etching selection ratio between the silicon oxide film and the silicon substrate may be taken into consideration as the etching selection ratio between the sidewall insulating film and the silicon substrate. Is relatively light. As the etching conditions at this time, a gas such as CF ₄ / CHF ₃ / Ar is used, and the gas pressure is 1 Torr, and the etching time is about 60 to 120 sec.

In this embodiment, as shown in FIG. 2E, a recess formed by the silicon oxide film 5 as the cap insulating film, the polycrystalline silicon film 4 as the shield electrode, and the shield gate oxide film 2 is formed. Since the sidewall insulating film is formed inside, the width of the sidewall insulating film as the sidewall spacer may be very small. That is, the width of the element isolation region is
Width w of silicon oxide film 5 determined by lithography ≈ 0.2
It does not increase so much from 0.8 μm. Further, by adjusting the film thicknesses of the silicon nitride film 7 and the silicon oxide film 8, the sidewall insulating film is left only in the recess formed by the silicon oxide film 5, the polycrystalline silicon film 4, and the shield gate oxide film 2. In this case, the width of the element isolation region is determined by lithography in the silicon oxide film 5.
The width w is approximately equal to 0.2 to 0.8 μm.

Further, as the cap insulating film of the polycrystalline silicon film 4, a silicon nitride film may be used instead of the silicon oxide film 5, and in this case, the etching selection ratio of the side wall insulating film to the cap insulating film is increased. Because it can be taken
It is possible to significantly reduce the film loss of the cap insulating film when the sidewall insulating film is anisotropically etched. Further, the film loss due to the subsequent pre-furnace cleaning step can also be reduced, and as a result, the film thickness of the cap insulating film at the time of formation and, consequently, the film thickness of the cap insulating film after anisotropic etching of the sidewall insulating film can be reduced. can do. Therefore, it is possible to reduce the height of the element isolation structure and prevent short-circuit defects due to step disconnection of the gate wiring 10 and the like and etching residue.

Next, the temperature is 800 to 850 ° C. and the time is 30 to
The silicon substrate 1 in the element region is subjected to thermal oxidation for about 90 minutes.
A gate oxide film 9 having a thickness of about 10 to 50 nm is formed on the surface of the. At this time, in this embodiment, since the silicon substrate 1 below the end portion of the element isolation structure is covered with the silicon nitride film 7, the oxidation is suppressed from progressing in that portion, and the enlarged local area is suppressed. Formation of an oxide film is prevented.

Next, by CVD or plasma CVD, a polycrystalline silicon film doped with phosphorus or arsenic at a concentration of about 2 × 10 ^{20 to} 6 × 10 ²⁰ / cm ³ is added to 100 to 40.
It is formed to a thickness of 0 nm. Then, the polycrystalline silicon film is patterned by the lithography technique to form the gate electrode 10.

Next, an impurity of phosphorus or arsenic is implanted by the ion implantation method to form the impurity diffusion layer 11 in self-alignment with the gate electrode 10. The surface concentration of the impurity diffusion layer 10 is, for example, 1 × 10 ¹⁹ to 1 × 10 ²¹ / cm ³ , and the junction depth is approximately 0.2 to 0.3 μm.

Next, after the impurity diffusion layer 11 is heat-treated, the interlayer insulating film 12 is formed, contact holes are formed, and Al is formed.
A desired semiconductor device is formed by forming a metal wiring 13 such as —Si—Cu.

Through the above steps, it is possible to manufacture a semiconductor device in which there is no local oxidation at the ends of the element isolation structure and the width of the field shield element isolation structure is smaller than in the conventional case.

The present invention has been described above with reference to the embodiments.
The invention is not limited to the embodiments described above. For example, the polycrystalline silicon film 4 may be amorphous silicon, tungsten silicide or polycide, or a refractory metal such as tungsten. The silicon substrate 1 is SIMOX (separation by implanted).
An SOI (Silicon On Insurator) substrate such as an oxygen substrate or a compound semiconductor substrate such as GaAs may be used.

[0048]

According to the present invention, by suppressing the local oxidation at the end of the field shield element isolation structure,
Since it is possible to prevent the reliability of the shield gate oxide film from decreasing,
Since the reliability of the semiconductor device can be improved and the expansion of the element isolation region can be suppressed, the degree of integration of elements can be improved.

Further, since the width of the element isolation region can be reduced by the side wall spacer of the field shield element isolation structure, the degree of integration of the elements can be further improved.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view showing a semiconductor device having a field shield element isolation structure according to an embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view showing a method of manufacturing a semiconductor device having a field shield element isolation structure according to an embodiment of the present invention in the order of steps.

FIG. 3 is a schematic cross-sectional view showing a method of manufacturing a conventional field shield element isolation structure in order of steps.

[Explanation of symbols]

 1 Silicon substrate 2 Shield gate oxide film 4 Polycrystalline silicon film 5 Silicon nitride film 6 Photoresist 7 Silicon nitride film 8 Silicon oxide film 9 Gate oxide film 10 Gate electrode (wiring) 11 Impurity diffusion layer 12 Interlayer insulating film 13 Metal wiring

Claims (9)

[Claims] 1. A semiconductor device for element isolation by a shield electrode formed on a semiconductor substrate via a shield gate oxide film, wherein a cap insulating film is formed on the shield electrode so as to be relatively larger than the shield electrode. A sidewall insulating film of the shield electrode is formed in a recess surrounded by the cap insulating film, the shield electrode, and the shield gate oxide film via an oxidation resistant film. 2. The semiconductor device according to claim 1, wherein the oxidation resistant film is a silicon nitride film. 3. The semiconductor device according to claim 2, wherein the sidewall insulating film is a silicon oxide film. 4. The semiconductor device according to claim 3, wherein the cap insulating film is a silicon oxide film. 5. The semiconductor device according to claim 3, wherein the cap insulating film is a silicon nitride film. 6. The semiconductor device according to claim 1, wherein the shield electrode is a polycrystalline silicon film. 7. A shield gate oxide film on a semiconductor substrate,
A step of sequentially forming a polycrystalline silicon film and a cap insulating film; a step of selectively removing the cap insulating film so that the pattern of the cap insulating film remains in the element isolation region; and the pattern of the cap insulating film. A step of anisotropically etching the polycrystalline silicon film so that the pattern of the polycrystalline silicon film remains underneath, and a step of side-etching the pattern of the polycrystalline silicon film by isotropic etching. A step of forming a silicon nitride film as an oxidation resistant film on the entire surface of the etched portion including the surface of the polycrystalline silicon film, and by filling the side-etched portion of the polycrystalline silicon film with silicon oxide on the entire surface. A step of forming a film, and forming the silicon oxide film, the silicon nitride film, and the shield gate oxide film. And anisotropic etching, a method of manufacturing a semiconductor device characterized by a step of forming a sidewall insulation film on a side of the polycrystalline silicon film. 8. The method of manufacturing a semiconductor device according to claim 7, wherein a silicon oxide film is formed as the cap insulating film. 9. The method of manufacturing a semiconductor device according to claim 7, wherein a silicon nitride film is formed as the cap insulating film.