JPH07273330A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To provide a semiconductor device having a highly reliable isolation property and a manufacturing method thereof. CONSTITUTION:The title semiconductor device is provided with a semiconductor substrate 2, an isolation region 4 buried in a groove formed in the substrate 2 and is formed of an insulator projecting from a surface of a semiconductor substrate, source/drain regions 6a, 6b, 6c spaced apart in an element region isolated by the isolation region 4, a gate electrode 8 formed in a surface of an element region held between source/drain regions having a gate insulation film 7 between and a side wall layer 5 formed in a side surface of a part projecting from a substrate surface of the isolation region 4. The source/drain region 6b in a part positioned in contact with the isolation region 4 and below a side wall layer is shallower than the source/drain region in a part excepting the above part.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to element isolation of a MIS transistor.

[0002]

2. Description of the Related Art In recent years, semiconductor integrated circuits have been increasingly miniaturized and highly integrated. In order to eliminate the insulation failure due to the parasitic channel and reduce the parasitic capacitance of the wiring, there is known a technique of forming an insulating film made of a thick oxide film in the field region between the elements and separating the elements by this insulating film. There is.

In forming this oxide film, a LOCOS method has been generally used in which a silicon nitride film is used as a mask to selectively thermally oxidize the substrate surface. However, this method inevitably causes the so-called bird's beak in which the end of the oxide film enters under the silicon nitride film that is the mask. Therefore, with the miniaturization of elements and element isolation regions, good element isolation characteristics are becoming difficult to obtain by the LOCOS method. In order to solve this problem, recently, after forming a groove in a silicon substrate by reactive ion etching, an element isolation region is formed by embedding an insulator in the groove using a film forming technique such as a CVD method. The trench element isolation method is adopted.

FIG. 7 shows a state in which an element isolation region is formed on a semiconductor substrate by using this method, and a gate electrode is further formed via a gate insulating film. As shown in FIG. 7, a trench 53 is provided in the semiconductor substrate 50 having the p-type well 51, and an insulating material is buried in the trench 53 to form an element isolation region 54. A source region 59 and a drain region 60 are provided in the surface region of the substrate sandwiched by the element isolation regions 51.
Are formed, and these source / drain regions 59 and 60 are formed.
A gate insulating film 52 and a gate electrode 55 are formed on the channel region sandwiched by the
The FET is configured. According to such a trench element isolation method, it is possible to cope with miniaturization of elements and element isolation,
It also has an advantage that a semiconductor device having excellent surface flatness can be obtained.

[0005]

However, when the trench element isolation method is adopted, the insulator forming the element isolation region is attacked by a dilute hydrofluoric acid-based treatment or the like in the cleaning step during the formation of the MOSFET. As shown in FIG. 7 (b), there arises a problem that the corner portion of the groove is exposed. When impurities are introduced into the substrate in such a state to form the source / drain, AB and CD in FIG. 7B are formed.
Also, as shown in the EF cross section, the depth of the diffusion layer at the source / drain ends becomes deep. In particular, punch-through may occur at the gate end in a cross section like AB.

Further, a MOSFET having such a shape
In order to reduce the resistance of the source / drain region, SALI
CIDE (Self Aligned Silicone)
When the step e) is applied, as shown in FIG.
The metal silicide film 65 formed on the element isolation region 6
3 may enter the exposed corners, resulting in increased junction leakage in the source / drain regions.

As described above, in the conventional element isolation technique,
It is difficult to control the shape at the interface between the source / drain region and the element isolation end, which causes punch-through and junction leak. Therefore, an object of the present invention is to provide a semiconductor device having an element isolation region having excellent element isolation characteristics and high reliability, and a method for manufacturing the same.

[0008]

In order to solve the above problems, a first invention comprises a semiconductor substrate and an insulator which is embedded in a groove formed in the substrate and protrudes from the surface of the semiconductor substrate. An element isolation region, a source / drain region formed separately from the element region separated by the element isolation region, and a surface of the element region sandwiched between the source / drain regions with a gate insulating film interposed therebetween. A gate electrode and a sidewall layer formed on a side surface of a portion of the element isolation region protruding from the surface of the substrate, and a source / drain portion in contact with the element isolation region and located under the sidewall layer. A semiconductor device is provided in which the depth of the region is shallower than the depth of the source / drain regions in the other portions.

In the semiconductor device of the first invention, the height of the step between the element isolation region and the substrate and the film thickness of the element isolation sidewall layer formed on the side surface of the element isolation region can be appropriately selected. , For example, the height of the step is 50 to 200n
It is preferable that the thickness of the element isolation side wall layer is about 0.5 to 2 times the height of the step.

The material of the side wall layer is SiN or SiO.
_2. Polycrystalline silicon or the like can be used. In addition,
In the semiconductor device of the first invention, a sidewall layer made of an insulating material may be formed on the side surface of the gate electrode. In this case, by forming the gate sidewall layer and the element isolation sidewall layer to have different widths, it is possible to optimize so as to satisfy the requirements due to the element characteristics and the element isolation characteristics.

According to a second aspect of the present invention, a semiconductor substrate and an element isolation region made of an insulating material that is embedded in a groove formed in the substrate and protrudes from the surface of the semiconductor substrate are provided.
Source / drain regions formed separately in the element region separated by the element isolation region, and a gate electrode formed on the surface of the element region sandwiched between the source / drain regions via a gate insulating film, A first sidewall layer made of an insulator provided on a side surface of the gate electrode, a second sidewall layer made of an insulating layer formed on a side surface of an element isolation region protruding from the substrate surface, and the first and second A semiconductor device, comprising: a metal silicide film formed on the surface of the source / drain region located between the second sidewall layers.

In the semiconductor device of the second invention, the film thickness of the first side wall layer made of an insulating material and formed on the side surface of the gate electrode can be appropriately selected, for example, 50 to 20.
It can be 0 nm.

The step difference between the element isolation region and the substrate and the film thickness of the element isolation sidewall layer which is the second sidewall layer formed on the side surface of the element isolation region are the same as those of the semiconductor device of the first invention. It can be appropriately selected, but preferably the step is
It is preferable that the thickness is about 50 to 200 nm, and the thickness of the element isolation side wall layer is at least about 0.5 to 2 times the height of the step.

As a metal constituting the metal silicide film, a transition metal, for example, a refractory metal such as Ti, Ni or Cr can be mentioned. By forming the metal silicide film on the surface of the diffusion layer, the resistance of the diffusion layer can be reduced.

A third aspect of the present invention is to form a groove for forming an element isolation region in a semiconductor substrate, and to form an insulator in the groove for forming the element isolation region so that an upper portion thereof projects from the substrate surface. Embedding and forming an element isolation region, sequentially forming a gate insulating film and a gate electrode on the surface of the element region separated by the element isolation region, and forming a sidewall layer on the entire surface of the substrate on which the element isolation region is formed. Forming an element isolation sidewall on the side surface of the portion of the element isolation region projecting from the substrate surface by anisotropic etching, and using the element isolation sidewall layer as a mask A step of introducing impurities into the element region in a self-aligned manner to form a diffusion layer in the element region.

In the third aspect of the invention, the gate electrode is used as a mask to introduce impurities into the element region in a self-aligning manner to form a diffusion layer (first diffusion layer) in the element region. Good. In this case, after that, a step of forming the element isolation region side wall layer is performed, and impurities are introduced into the element region in a self-aligned manner by using the element isolation side wall layer as a mask, and the first region is formed in the element region. It is preferable to perform the step of forming a diffusion layer (second diffusion layer) deeper than the first diffusion layer.

Further, a fourth aspect of the present invention is to form a groove for forming an element isolation region in a semiconductor substrate, and to provide an insulator in the groove for forming the element isolation region so that an upper portion thereof projects from the substrate surface. Burying and forming an element isolation region,
A step of sequentially forming a gate oxide film and a gate electrode on the surface of the element region separated by the element isolation region, and a film for forming a sidewall on the entire surface of the substrate on which the gate electrode is formed are anisotropically etched. A step of forming first and second sidewall layers made of an insulating material on a side surface of the gate electrode and a side surface of a portion of the element isolation region protruding from the surface of the substrate, respectively;
Of the diffusion layer located between the first and second side wall layers by introducing impurities into the element region in a self-aligning manner by using the side wall layer as a mask. And a step of forming a metal silicide film on the surface in a self-aligned manner.

In the fourth aspect of the invention, a step of introducing impurities into the element region in a self-aligned manner and further forming a diffusion layer in the element region may be performed using the gate electrode as a mask.

The first side wall layer on the side surface of the gate electrode,
The second side wall layer on the side surface of the element isolation region may be formed in separate steps, but may be formed by performing anisotropic etching once after depositing an insulating film on the gate electrode. . In this case, the etching selection ratio between the material exposed on the substrate surface and the material forming the sidewall layer,
And etching is performed in consideration of the amount of over-etching.

[0020]

In the semiconductor device of the present invention, the element isolation region is projected from the substrate surface, and the side wall layer is formed on this projected portion. Since the contact between the element isolation region and the substrate is protected by providing the sidewall layer in the element isolation region in this manner, the element isolation region is not attacked even when the treatment is performed with dilute hydrofluoric acid.

Further, in the semiconductor device of the first invention, since the depth of the first diffusion layer located under the element isolation side wall layer and in contact with the element isolation region is shallow, punch-through at the gate end is prevented. Can be prevented.

When the salicide process is applied to the MOSFET having such a structure and the metal silicide film is formed on the diffusion layer, since the side wall layer exists on the side surface of the element isolation region, it is formed on the diffusion layer. The formed metal silicide film does not directly contact the element isolation region. Therefore, it is possible to prevent a junction leak at the element isolation end. Therefore, element isolation is completed, and a highly reliable element isolation region can be obtained.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to the drawings. FIG. 1 shows an example of the semiconductor device of the present invention. As shown in FIG. 1, in a semiconductor device 1, an insulating film 4 made of silicon oxide or the like is embedded in a groove 3 for forming an element isolation region provided in a semiconductor substrate 2. The upper part of the insulating film 4 is
It is formed so as to be higher than the surface of the semiconductor substrate 2, and an element isolation sidewall layer 5 is formed in the step portion obtained by this. A diffusion layer 6 is provided between the element isolation regions.
A gate electrode 8 is provided via a gate oxide film 7 on the surface of a substrate sandwiched between two diffusion layers a, b and c electrically separated from each other. A gate sidewall layer 9 made of SiN is formed on the side surface of the gate electrode,
The diffusion layers 6b and 6c existing under the element isolation sidewall layer 5 and the gate sidewall layer 9 are diffusion layers 6a located between them.
The depth is shallower.

As described above, by forming the upper surface of the element isolation region 4 higher than the surface of the substrate 2 and further forming the sidewall layer 5 on the side surface of the element isolation region, the element isolation region 4 and the diffusion layer 6 are formed. The joint surface can be protected.

Next, a method of manufacturing a semiconductor device of the present invention will be described with reference to the drawings. 2 to 5 are sectional views showing the manufacturing process. First, as shown in FIG.
B as an impurity is added to the surface of the type silicon substrate 10 by 10 ¹⁷
Introduced by ion implantation at a concentration of / cm ³ , depth 1 μm
A p-type well 11 having a size of about 10 is formed. A thermal oxide film 12 of about 10 μm is formed on the substrate 10 on which the p-type well 11 is formed.
Then, a polycrystalline silicon film 13 having a film thickness of about 50 nm was formed by the CVD method. Polycrystalline silicon film 13
Is a CMP (Chemical Mechanical) insulator that is buried in a groove for forming an element isolation region later.
It acts as a stopper at the time of etching back by using the alkaline polishing method. Further, the thermal oxide film 12 prevents the substrate from being etched when the polycrystalline silicon film 13 is removed later.

The element region of the substrate 10 on which the thermal oxide film 12 and the polycrystalline silicon film 13 are formed by the above procedure is
Masking with a resist and patterning using RIE, a groove 1 having a width of about 0.8 μm and a depth of about 0.8 μm is formed in a portion where an element isolation region is formed as shown in FIG.
4 was formed.

Then, a CVD method is used to deposit a silicon oxide film 15 having a thickness of about 1 μm on the entire surface of the substrate on which the polycrystalline silicon film 13 is formed as shown in FIG. It is. In depositing the silicon oxide film 15, besides the CVD method, a method using a liquid phase using a supersaturated SiO ₂ solution may be adopted.

As the film to be embedded in the groove 14,
Other insulating films such as a silicon nitride film may be used, but in that case, it is preferable to sufficiently consider the selectivity with respect to the etching stopper in CMP and the consistency in the subsequent steps.

Then, the silicon oxide film 15 is etched back by the CMP method. At this time, the polycrystalline silicon film 1
Since 3 acts as a stopper, polishing can be stopped when the heights of the polycrystalline silicon film 13 and the silicon oxide film 15 coincide with each other as shown in FIG.

Next, CDE (Chemical Dry)
Etching) method or the like
Only selectively remove. As a result, as shown in FIG. 3B, the groove 14 is filled with the silicon oxide film 15 protruding from the substrate surface by about 50 to 60 nm.

Next, after performing ion implantation for adjusting the threshold value of the MOSFET as needed, the thermal oxide film 12 was peeled off and a gate oxide film 16 of about 10 nm was formed by thermal oxidation. Then, a polycrystalline silicon film 17 having a film thickness of 200 nm is formed by CVD, and P as an impurity is formed.
^Was added at a concentration of about 4 × 10 ²⁰ cm ⁻³ . Furthermore, a refractory metal film 1 having a thickness of about 150 nm is formed by the sputtering method.
8 and an insulating film 19 made of a silicon oxide film having a thickness of about 100 μm were sequentially formed. The obtained film was processed into a predetermined shape by RIE to form a gate electrode as shown in FIG. As the refractory metal film 18, T
i, W, Mo or the like can be used, and as the insulating film 19, a silicon oxide film, a silicon nitride film, or the like can be used. The insulating film 19 also serves as a cap for the gate electrode and has a function of preventing impurity ions from penetrating into the channel region and a function of protecting the refractory metal film during ion implantation for forming the source / drain.

Next, as shown in FIG. 4A, a thermal oxide film 20 having a thickness of about 10 nm is formed on the side surface of the polycrystalline silicon film 17, and then the substrate of As is formed at 50 KeV and 3 × 10 ¹³ cm ^-2. To form shallow source / drain regions 21. This is the so-called LDD (Lightly Do)
Ped drain), and such a shallow diffusion layer can alleviate the electric field concentration at the source / drain ends in contact with the element isolation region and improve the reliability of the element. Further, by forming the thermal oxide film 20 on the side surface of the polycrystalline silicon film 17, it is possible to relieve the electric field concentration and prevent the contamination from the resist that serves as a mask for ion implantation when forming a CMOS.

In this embodiment, the gate electrode is formed by laminating the impurity-added polycrystalline silicon film, the refractory metal film, and the insulating film, but the impurity-added polycrystalline silicon film is used as a single layer. You can also Alternatively, a layered structure of an impurity-added polycrystalline silicon film and a silicide film of a refractory metal such as TI, W, and Mo may be used.

Next, as shown in FIG. 4B, a silicon nitride film 22 is deposited on the entire surface to a thickness of about 150 nm by CVD, and then anisotropic etching is performed to form a gate as shown in FIG. 4C. The sidewall layer 23 is formed. As the film to be deposited on the entire surface to become the gate sidewall layer 23 later, a material having a large selection ratio with the silicon oxide film 15 and the thermal oxide film 12 which form the element isolation region during anisotropic etching is selected. Preferably.

Next, as shown in FIG. 5A, a silicon nitride film 24 is deposited on the entire surface by CVD to a film thickness of about 50 nm, and anisotropic etching is carried out, so that FIG.
The element isolation sidewall layer 25 is formed as shown in FIG.

Next, for example, 40 KeV, 3 × 10 ¹⁵ c
About m ⁻² As is introduced into the substrate to form the source / drain regions 26 as shown in FIG. Through the above steps, a semiconductor device having the element isolation sidewall layer 25 and the gate sidewall layer 23 and having a shallow source / drain region in contact with the element isolation region can be obtained. Width of element isolation sidewall layer,
The concentration and depth of the shallow source / drain region existing under the element isolation sidewall layer, the depth of the source / drain region formed by introducing impurities after the element isolation sidewall layer formation, etc. It becomes a factor that determines the characteristics.

In the semiconductor device shown in the above example, since the side wall layer 23 is also formed on the side surface of the gate electrode, the depth of the source / drain region located below the side wall layer 23 is also different from that of the element isolation side wall layer 25. Shallow as well as below. Width of gate sidewall layer, shallow source under gate sidewall layer
The short channel effect, the current driving force, the punch-through breakdown voltage, etc. are determined by the concentration and depth of the drain region, the depth of the source / drain region formed by introducing impurities after forming the element isolation sidewall layer, and the like. .

In the above-mentioned example, the element isolation side wall layer and the gate side wall layer are formed by using the same material in different steps, but these two side wall layers are formed by a single step. Good. In this case, first, the height ratio from the substrate surface is appropriately selected to form the gate and element isolation regions, and then the etching selection ratio between the material exposed on the substrate surface and the sidewall layer material is selected. , And the amount of over-etching are taken into consideration to perform anisotropic etching. Further, the two sidewall layers may be formed by using different kinds of materials. For example, instead of silicon nitride, silicon oxide (such as one formed by a CVD method) or polycrystalline silicon can be used.

In the above example, the n-type MOSF is used.
Although the ET has been described as an example, the p-type MOSFET can be manufactured by a similar method only by reversing the conductivity types of the substrate and the impurity.

FIG. 6 shows another example of a semiconductor device formed by using the manufacturing method of the present invention. In the semiconductor device 29 shown in FIG. 6, in order to reduce the resistance of the diffusion layer 41 of the source / drain, the SALICIDE process is applied to form the metal silicide film 42 on the source / drain 41.

As shown in the figure, since the element isolation side wall layer 39 is previously formed, the metal silicide film 42 is formed apart from the element isolation region 33. Therefore, it is possible to prevent the leak generated at the element isolation end.

In manufacturing the semiconductor device 29, first, the element isolation region 33 is formed in the substrate by the same steps as those shown in FIGS. 2A to 4A described above, and then, The gate electrode 34 via the gate insulating film 32,
35 etc. were formed and impurities were introduced into the substrate. Next, a silicon nitride film is deposited on the entire surface and anisotropic etching is performed once to form a gate sidewall layer 38 and an element isolation sidewall layer 39, and then impurities are introduced using these as a mask, The diffusion layer 41 was formed. Further, after 30 nm of Ti is formed on the surface of the diffusion layer 41 by a sputtering method, RTA (Rapid Ther) at about 750 ° C. is performed.
The metal silicide film 42 was formed in a self-aligning manner by performing heat treatment by means of mal annealing. After that, unreacted Ti is converted into H ₂ SO ₄ + H ₂ O ₂ or NH ₃
It was peeled off selectively with a solution such as + H ₂ O ₂ + H ₂ O.

As described above, when the SALICIDE process is performed, the gate sidewall layer 38 and the element isolation sidewall layer 39 are formed to prevent conduction between the source / drain and the gate.
It must be an insulating film such as SiN or SiO ₂ .

In the above example, the element isolation side wall layer and the gate side wall layer may be formed in different steps.
Moreover, you may form using a different kind of material. In addition, various modifications can be made without departing from the scope of the present invention.

[0045]

As described above, according to the present invention,
By forming the element isolation region so that the upper surface of the buried type element isolation region is higher than the substrate surface and forming the sidewall layer on the side surface of the element isolation region, the element isolation region and the diffusion layer in contact with the element isolation region are formed. Boundaries can be protected. Therefore, it is possible to prevent a void from being generated at the element isolation end and suppress the occurrence of a junction leak. Further, since the depth of the diffusion layer in contact with the element isolation region and located under the side wall layer is shallower than the other portions, it is possible to prevent the punch-through breakdown voltage of the element from deteriorating. Therefore, a semiconductor device having highly reliable and stable element isolation characteristics can be obtained. Such good element characteristics further improve the performance of the semiconductor device, and its industrial application effect is great.

[Brief description of drawings]

FIG. 1 is a sectional view showing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 4 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 5 is a cross-sectional view showing the manufacturing process of the semiconductor device of the first embodiment of the present invention.

FIG. 6 is a sectional view showing a semiconductor device according to a second embodiment of the present invention.

FIG. 7 is a diagram showing a cross-sectional shape of a conventional buried element isolation region.

FIG. 8: SALICE IDE for conventional embedded device isolation
The enlarged view which shows the cross section of an element isolation end at the time of applying the (self aligned silicide) process.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 2 ... Substrate, 3 ... Trench, 4 ... Element isolation region 5 ... Element isolation sidewall layer, 6 ... Diffusion layer, 7 ... Gate oxide film,
8 ... Gate electrode 9 ... Gate side wall layer, 10 ... Substrate, 11 ... P-type well, 1
2 ... Thermal oxide film 13 ... Polycrystalline silicon film, 14 ... Trench, 15 ... Silicon oxide film 16 ... Gate oxide film, 17 ... Polycrystalline silicon film, 18 ...
Refractory metal film 19 ... Insulating film, 20 ... Thermal oxide film, 21 ... Shallow diffusion layer 22 ... Polycrystalline silicon film, 23 ... Gate sidewall layer, 24 ...
Silicon nitride film 25 ... Element isolation side wall layer, 26 ... Diffusion layer, 29 ... Semiconductor device, 30 ... Substrate 31 ... P-type well, 32 ... Gate insulating film, 33 ... Element isolation region 34 ... Polycrystalline silicon film, 35 ... High Melting point metal film, 36 ...
Insulating film 37 ... Thermal oxide film, 38 ... Gate sidewall layer, 39 ... Element isolation sidewall layer 40 ... Shallow diffusion layer, 41 ... Diffusion layer, 42 ... Metal silicide film, 50 ... Substrate 51 ... P-type well, 52 ... Gate insulation Membrane, 53 ... Trench 54 ... Element isolation region, 55 ... Gate electrode, 56 ... Insulating film, 57 ... Gate sidewall layer 58 ... Diffusion layer, 59 ... Source region, 60 ... Drain region, 62 ... Substrate 63 ... Element isolation region, 64 ... Diffusion layer, 65 ... Metal silicide film.

Claims (4)

[Claims] 1. A semiconductor substrate, an element isolation region made of an insulating material which is embedded in a groove formed in the substrate and protrudes from the surface of the semiconductor substrate, and an element region isolated by the element isolation region. A source / drain region formed by a gate electrode formed on the surface of the element region sandwiched by the source / drain region via a gate insulating film; and a portion of the isolation region protruding from the substrate surface. A side wall layer formed on the side surface, the depth of the source / drain region in a portion in contact with the element isolation region and located under the side wall layer is greater than the depth of the source / drain region in the other portion. A semiconductor device characterized by being shallow. 2. A semiconductor substrate, an element isolation region made of an insulating material which is embedded in a groove formed in the substrate and protrudes from the surface of the semiconductor substrate, and an element region isolated by the element isolation region. And a gate electrode formed on the surface of the element region sandwiched by the source / drain region via a gate insulating film, and an insulator provided on a side surface of the gate electrode. First
Of the source / drain regions located between the first and second side wall layers, the second side wall layer formed of an insulating layer formed on the side surface of the element isolation region protruding from the substrate surface. A semiconductor device comprising: a metal silicide film formed on a surface thereof. 3. A step of forming a groove for forming an element isolation region in a semiconductor substrate, and a step of forming an element isolation region by burying an insulator in the groove for forming the element isolation region so that an upper portion of the groove projects from the substrate surface. A step of forming, a step of sequentially forming a gate insulating film and a gate electrode on the surface of the element region separated by the element isolation region, and a film for forming a sidewall layer on the entire surface of the substrate on which the element isolation region is formed Then, by performing anisotropic etching,
A step of forming an element isolation sidewall layer on a side surface of a portion of the element isolation region protruding from the substrate surface, and introducing impurities into the element region in a self-aligned manner using the element isolation sidewall layer as a mask, And a step of forming a diffusion layer on the substrate. 4. A step of forming a groove for forming an element isolation region in a semiconductor substrate, and an insulating material is embedded in the groove for forming the element isolation region so that an upper portion of the groove projects from the surface of the substrate to form the element isolation region. A step of forming, a step of sequentially forming a gate oxide film and a gate electrode on the surface of the element region separated by the element isolation region, and a film for forming a sidewall on the entire surface of the substrate on which the gate electrode is formed, By performing anisotropic etching, the first side made of an insulator is formed on the side surface of the gate electrode and the side surface of the portion of the element isolation region protruding from the substrate surface.
And a step of forming a second sidewall layer, and a step of introducing impurities into the element region in a self-aligning manner using the first and second sidewall layers as a mask to form a diffusion layer in the element region. A step of forming a metal silicide film on the surface of the diffusion layer located between the first and second side wall layers in a self-aligned manner.