JPH0923007A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the occurrence of short circuits between transistors and, at the same time, flatten the surface of a semiconductor device by forming an element separating insulating film, a gate electrode, a first conductive layer, and a second conductive layer so that the surfaces of the film, electrode, and layers can be nearly flushed with the surface of a semiconductor substrate. SOLUTION: The level difference between an element separating insulating film 14 which separates a first area 12 and a second area 13 from each other and a gate electrode 23 which is formed in the first and second areas 12 and 13 is almost eliminated in a state where the electrode 23 is conducted, because the area 14A of the insulating film 14 in which the gate electrode 23 is formed is formed at nearly the same height as that of the surface of a semiconductor substrate 11. Consequently, the level difference caused by the gate electrode 23 passing on the insulating film 14 is eliminated. In addition, since the surfaces of first conductive layers 33 and 34 and second conductive layers 43 and 44 are nearly flushed with the surfaces of the electrode 23 and film 14, the level difference caused by the electrode 23 and the surface of a semiconductor device 1 is almost eliminated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device in which gate electrodes of a plurality of transistors are connected to each other and a method for manufacturing the same.

[0002]

2. Description of the Related Art Conventional metal-oxide film-semiconductor (hereinafter referred to as M
A transistor called OS (MOS is an abbreviation for Metal-Oxide-Semiconductor) is formed in an active region isolated by an element isolation insulating film. And LOCOS (Lo
The element isolation insulating film and the gate electrode of the MOS transistor formed by the cal oxidation (Silicon) method form a step on the surface of the semiconductor substrate. As a transistor structure that eliminates the step, a transistor having a so-called stacked diffusion layer in which a conductive layer connected to the source / drain regions via sidewall insulating films is formed on both sides of a gate electrode is disclosed.

[0003]

However, the stacked diffusion layer is formed by forming a conductive layer forming film and then patterning the conductive layer forming film by a lithography process and an etching process. Alternatively, it is formed by epitaxially growing a material to be a stacked diffusion layer on the source / drain regions. Therefore, the manufacturing cost is high. Further, it is impossible to eliminate the step difference of the gate electrode arranged on the element isolation insulating film. Therefore, when forming the multi-layered wiring, it is not possible to adopt an exposure method with a small depth of focus, which makes it difficult to form a highly precise and fine wiring pattern. There is also a method of forming a conductive layer forming film to be a stacked diffusion layer and then polishing the conductive layer forming film to selectively form the stacked diffusion layer on the source / drain regions. However, this method cannot remove the extra conductive layer forming film formed on the side wall of the gate electrode on the element isolation insulating film. If the conductive layer forming film remains in this way, there arises a problem that the stacked diffusion layers between the transistors are short-circuited.

It is an object of the present invention to provide a semiconductor device which prevents short circuits between transistors in a low cost process and is excellent in planarization, and a manufacturing method thereof.

[0005]

SUMMARY OF THE INVENTION The present invention is a semiconductor device and a method of manufacturing the same which are made to achieve the above object.

That is, the semiconductor device has the following structure, and the element isolation insulating film for isolating the first region and the second region for forming an element is formed on the semiconductor substrate. A gate electrode is formed on the first and second regions, passing through the element isolation insulating film via the gate insulating film. First source / drain regions are formed in the first region of the semiconductor substrate on both sides of the gate electrode, and second source / drain regions are formed in the second region. A first electrode is formed on both sides of the gate electrode on each first source / drain region.
The first conductive layer is connected through the insulating film, and each second source
On the drain region, the second conductive layer is connected to both sides of the gate electrode via the second insulating film. And
The surface of the element isolation insulating film where the gate electrode is formed and the surface of the semiconductor substrate are formed at substantially the same height, and the element isolation insulating film, the gate electrode, the first conductive layer, and the second conductive layer are formed. Each surface is formed at substantially the same height.

In the manufacturing method, in the first step, an element isolation insulating film for separating the first region and the second region is formed on the semiconductor substrate, and subsequently, the element isolation insulating film is passed through the first and first regions. Two
After forming a mask pattern that is provided on the area and has an opening on the area where the gate electrode is to be formed, the element isolation insulating film exposed in the opening is made to have a height almost equal to the surface of the semiconductor substrate. Remove until Next, in a second step, after forming the gate insulating film on the surface of the semiconductor substrate in the opening, the gate electrode is formed so as to fill the opening, and the mask pattern is removed and the surface of the gate electrode and the element isolation insulating film are removed. The uppermost surface is formed at almost the same height. Then, in a third step, first and second insulating films are formed on both sides of the gate electrode, first source / drain regions are formed on the first region of the semiconductor substrate on both sides of the gate electrode, and a second source / drain region is formed on the second region. 2 Source / drain regions are formed. Then, in a fourth step, after forming a conductive layer forming film on the first and second source / drain regions, forming a conductive layer until the height becomes almost equal to that of the element separating insulating film by using the element separating insulating film as a stopper. Part of the film is removed to form first and second conductive layers connected to the first and second source / drain regions.

In the semiconductor device having the above structure, the surface of the element isolation insulating film in the portion where the gate electrode is formed and the surface of the semiconductor substrate are formed at substantially the same height, and the uppermost surface of the element isolation insulating film is formed. Since the surface of the gate electrode is formed at almost the same height, the gate electrode on the element isolation insulating film is made conductive with the gate electrodes in the first and second regions passing through the element isolation insulating film. The step between and is almost eliminated. Further, since the respective surfaces of the first and second conductive layers are formed at substantially the same height as the respective surfaces of the gate electrode and the element isolation insulating film, the surface of the semiconductor device is substantially flattened.

In the above-described manufacturing method, the element isolation insulating film in the region where the gate electrode is to be formed is removed until the height is almost the same as the surface of the semiconductor substrate, and then the gate insulating film is formed and then the first and second regions are formed. Since the gate electrode that passes over the element isolation insulating film is formed in the region, the gate electrode formed in the first and second regions is connected. Further, since the surface of the gate electrode and the uppermost surface of the element isolation insulating film are formed to have substantially the same height, the step of the gate electrode with respect to the element isolation insulating film is eliminated.

After forming the conductive layer forming film, the conductive layer forming film is removed by using the element isolation insulating film as a stopper. Therefore, by performing the film forming step and the removing step, the first layer is formed in a so-called self-aligned manner. , A second conductive layer is formed. Therefore, it is not necessary to perform a costly lithography process or epitaxial growth process in this process. Further, the surfaces of the first and second conductive layers and the surfaces of the element isolation insulating film and the gate electrode are formed at substantially the same height.

Since the surface of the gate electrode and the uppermost surface of the element isolation insulating film are formed at substantially the same height,
When the conductive layer forming film is polished, the conductive layer forming film does not remain on both sides of the gate electrode. Therefore, the first and second conductive layers formed in the first and second regions are not short-circuited.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to the schematic sectional view of FIG. In the figure, as an example, a semiconductor device in which one transistor is provided in each of the first and second regions is shown. A cross-sectional view in the gate width direction is shown in (1) of FIG.
A cross section in the gate length direction in the first region is shown in (2) of the figure, and a cross section in the gate length direction in the second region is shown in (3) of the figure. Note that the drawing in the gate length direction is shown in an enlarged manner compared to the drawing in the gate width direction.

As shown in the figure, the semiconductor substrate 11 has a first region 12 and a second region 1 for forming a transistor.
An element isolation insulating film 14 for separating the element 3 from the element 3 is formed.
The element isolation insulating film 14 is formed of, for example, an oxide film by the LOCOS method. The first and second regions 12, 1
A region 14A of the element isolation insulating film 14 between which the gate electrode is formed is formed at a height substantially equal to the surface of the semiconductor substrate 11. In addition, the first and second regions 12, 13
The regions 14B and 14C of the element isolation insulating film 14 on the side facing the region 14A with the gate electrodes formed therebetween are also formed to have a height substantially equal to the surface of the semiconductor substrate 11.

Then, it passes over the area 14A and crosses the first and second areas 12 and 13, and the first and second areas are formed.
A gate electrode 23 is formed on the regions 12 and 13 with the gate insulating films 21 and 22 interposed therebetween. This gate electrode 23
Is a part of the gate wiring on the element isolation insulating film 14. Both ends of the gate electrode 23 have the region 14
It is formed on B and 14C, and the surface thereof is formed at almost the same height as each surface of the element isolation insulating film 14.

First source / drain regions 31 and 32 are formed in the semiconductor substrate 11 in the first region 12 on both sides of the gate electrode 23. In addition, the gate electrode 23
The semiconductor substrate 11 in the second region 13 on both sides of the second
Source / drain regions 41 and 42 are formed.

Further, on the side wall of the gate electrode 23 on the first region 12, first insulating films 24 and 25 serving as sidewall insulating films are formed. The first insulating film 2 is formed on the first source / drain regions 31 and 32.
First conductive layers 33, 34 connected to the source / drain regions 31, 32 via 4, 25 are formed.

On the other hand, on the side wall of the gate electrode 23 on the second region 13, second insulating films 26 and 27 to be sidewall insulating films are formed. Further, on the second source / drain regions 41, 42, the second insulating film 26,
Second conductive layers 43 and 44 connected to the source / drain regions 41 and 42 via 27 are formed. Further, the element isolation insulating film 14 and the first and second conductive layers 33, 3
The surfaces of 4, 43, and 44 are formed at substantially the same height.

The first and second insulating films 24-27 are made of insulating films such as silicon oxide and silicon nitride. Each of the first and second conductive layers 33, 34, 43, 44 has a polycide structure in which, for example, a conductive polysilicon layer and a silicide layer are laminated. As a matter of course, it is also possible to form the other conductive material such as conductive polysilicon or refractory metal.

In the semiconductor device 1 having the above structure, the first and second
Since the region 14A of the element isolation insulating film 14 that separates the regions 12 and 13 is formed at substantially the same height as the surface of the semiconductor substrate 11, the first and second regions 1 are formed.
The step between the element isolation insulating film 14 and the gate electrode 23 is almost eliminated in a state where the gate electrodes 23 formed in 2 and 13 are made conductive. Therefore, the step due to the gate electrode 23 passing over the element isolation insulating film 14 in a state where the gate electrode 23 formed in the first and second regions 12 and 13 is made conductive is eliminated. In addition, the first conductive layer 33, 34 and the second conductive layer 4
Since the surfaces of the electrodes 3 and 44 are formed at substantially the same height as the surfaces of the gate electrode 23 and the element isolation insulating film 14, the step due to the gate electrode 23 is eliminated and the surface of the semiconductor device 1 is substantially flattened. To be done.

Next, a method of manufacturing a semiconductor device will be described with reference to manufacturing process diagrams (No. 1) to (No. 3) of FIGS.
2 to 3 (2) show a cross section in the gate width direction, and FIG. 3 (3) and subsequent figures show a cross section in the gate length direction. The drawing of the cross section in the gate length direction is shown in a larger scale than the drawing of the cross section in the gate width direction. The same components as those described in FIG. 1 are denoted by the same reference numerals.

In the first step, as shown in (1) of FIG. 2, for example, LOCOS (Local Oxidation of Silicon) is used.
By the method to form an element formation region on the semiconductor substrate 11.
Element isolation insulating film 1 for separating the region 12 and the second region 13
4 is formed of a silicon oxide film. Subsequently, a silicon nitride film (not shown) used as an oxidation mask used in the LOCOS method is removed by wet etching with, for example, hot phosphoric acid, and then a pad oxide film (not shown) used in the LOCOS method is wet etched with, for example, hydrofluoric acid. Remove by. The LOCOS method is a so-called poly pad LOC.
In the case of the OS method, the polycrystalline silicon film is also removed.

Next, as shown in FIG. 2B, for example, chemical vapor deposition (hereinafter, referred to as CVD, CVD is Chemic).
Al Vapor Deposition method)
After the silicon nitride film is formed on the first layer 1, it is formed on the regions where the gate electrodes are to be formed by passing through the element isolation insulating film 14A and the first and second regions 12 and 13 by the lithography technique and the etching. A mask pattern 52 having openings 51 is formed. After that, the portion of the element isolation insulating film 14 exposed in the opening 51, which is indicated by the chain double-dashed line, is removed by, for example, etching until the height becomes almost equal to the surface of the semiconductor substrate 11. Further, it is desirable that the height of the mask pattern 52 on the semiconductor substrate 11 be substantially equal to the step of the element isolation insulating film 14.

In the etching of the element isolation insulating film 14, after forming the mask pattern 52, a resist, for example, is applied as a flattening film having an etching rate equivalent to that of the oxide film forming the element isolation insulating film 14. To form a resist film (not shown). After that, etching back is performed under the condition that the resist film and the element isolation insulating film 14 have almost the same etching rate. In such etching, the surface of the element isolation insulating film 14 and the surface of the semiconductor substrate 11 formed by the etching have substantially the same height.

In the first step, ion implantation for forming a well (not shown), ion implantation for forming a channel stop diffusion layer (not shown), and adjusting the threshold voltage Vth are performed. Ion implantation is also performed.

Next, in the second step, as shown in FIG. 2C, the gate insulating films 21 and 22 made of silicon oxide are formed on the surface of the semiconductor substrate 11 inside the opening 51 by, for example, a thermal oxidation method. To do. Further, the electrode forming film 53 is formed by depositing, for example, polycrystalline silicon, which is a gate electrode material, at least above the height of the uppermost surface of the element isolation insulating film 14 in the opening 51 by the CVD method.

Then, as shown in FIG. 3A, the electrode forming film 5 on the mask pattern 52 is formed by a polishing method [for example, chemical mechanical polishing (chemical mechanical polishing)].
The portion indicated by the chain double-dashed line in 3 is removed.

Subsequently, as shown in FIG. 3B, the mask pattern 52 (the portion indicated by the chain double-dashed line) is removed by wet etching using, for example, hot phosphoric acid. Further, by a polishing method (for example, chemical mechanical polishing) or an ion stream etching method, a portion indicated by a chain double-dashed line of the electrode forming film 53 is removed to flatten the surface of the electrode forming film 53, Are formed at substantially the same height as the uppermost surface of the element isolation insulating film 14.
In this way, the gate electrode 23 having the surface having substantially the same height as the uppermost surface of the element isolation insulating film 14 is formed by the electrode forming film (53).

Next, the third step is performed. In the drawings after this step, a cross-sectional view of the first region 12 is shown as a representative. In addition,
Since the cross section of the second region 13 is the same as the cross section of the first region 12, the reference numerals of the components of the second region 13 are shown in parentheses.

As shown in FIG. 3C, the semiconductor substrate 1 on both sides of the gate electrode 23 is formed by the ion implantation method.
1st (2nd) LDD (Lightly Doped Drain)
) Diffusion layers 35 (45) and 36 (46) are formed. Then, the first (second) insulating film 24, 25 made of silicon oxide is formed on the side wall of the gate electrode 23 by a normal sidewall forming technique such as a film forming technique and an etchback technique.
(26,27) is formed. After that, the gate electrode 23 and the first (second) insulating films 24, 25 (26, 27) are used as an ion implantation mask, and the first (second) region 12 (13) in the upper layer of the semiconductor substrate 11 is ion-implanted. Then, first (second) source / drain regions 31, 32 (41, 42) are formed. In the case of a transistor in which hot carriers are not a problem, the LDD diffusion layers 35, 36 (4
5, 46) may not be formed.

Next, as shown in FIG. 4A, in the fourth step, polycrystalline silicon is formed on the first (second) source / drain regions 31, 32 (41, 42) by, for example, the CVD method. The conductive layer forming film 54 is formed so as to be embedded. Then, a part of the conductive layer forming film 54 is formed until the element isolation insulating film 14 and the first (second) insulating films 24, 25 (26, 27) are used as polishing stoppers to have a height substantially equal to that of the element isolation insulating film 14. Are removed by polishing [eg chemical mechanical polishing (eg chemical mechanical polishing)].

Then, as shown in FIG. 4B, the first
(Second) source / drain regions 31, 32 (41, 4)
2) connected to the first (second) conductive layer 33, 34 (43,
44) is formed. In the structure in which the insulating film is not formed on the gate electrode 23, the first (second) insulating films 24 and 2 are formed.
The upper part of 5 (26, 27) is slightly polished. As a result, the upper surfaces of the first (second) conductive layers 33, 34 (43, 44), the upper surface of the gate electrode 23, and the element isolation insulating film 14 are formed.
The upper surfaces of are formed at substantially the same height.

The semiconductor device 1 is completed as described above.

In the manufacturing method described with reference to FIGS. 2 to 4, the gate electrode 23 and the first and second conductive layers 33 and 3 are used.
Although 4, 43 and 44 are made of polycrystalline silicon, they may be made of, for example, amorphous silicon, or may be made of a semiconductor material other than silicon. Similarly, for the semiconductor substrate 11, it is also possible to use a substrate made of a semiconductor material other than silicon. Further, the impurity concentrations of the first and second LDD diffusion layers 35, 36, 45 and 46, the first and second source / drain diffusion layers 31, 32, 41 and 42 are appropriately selected.

In the above manufacturing method, the height of the element isolation insulating film 14 for separating the first region 12 and the second region 13 is substantially equal to the height of the surface of the semiconductor substrate 11 on the region where the gate electrode 23 is to be formed. After removing the gate insulating film 2
Since the gate electrodes 23 that pass over the element isolation insulating film 14 are formed in the first and second regions 12 and 13 after forming the first and second regions 22 and 13, the regions are formed on the first and second regions 12 and 13. With the gate electrode 23 connected, the surfaces of the gate electrode 23 and the element isolation insulating film 14 are formed at substantially the same height.

After forming the conductive layer forming film 54, the conductive layer forming film 54 is removed using the element isolation insulating film 14 as a stopper, and the first and second insulating films 24 to 24 are formed on both sides of the gate electrode 23.
27 through the first and second conductive layers 33, 34, 43, 44
Since the formation of the mask does not require a lithography process, a costly mask process is eliminated. Further, the conductive layer forming film 54 is formed by C instead of epitaxial growth.
Since the VD method or the sputtering method can be used, no film formation cost is required.

Furthermore, since the conductive layer forming film 54 is polished by using the element isolation insulating film 14 as a polishing stopper, the surfaces of the element isolation insulating film 14 and the gate electrode 23 are formed at substantially the same height. The surfaces of the gate electrode 23 and the element isolation insulating film 14 are formed at substantially the same height. Therefore, when the conductive layer forming film 54 is polished, the conductive layer forming film 54 does not remain on both sides of the gate electrode 23 on the element isolation insulating film 14, so that the first conductive layers 33 and 34 and the second conductive layer 43. , 44 is not short-circuited.

Further, as shown in FIG. 5, the gate electrode 2
The insulating film 55 may be formed on the upper part of 3. In FIG. 5, the first region 12 is shown as a representative. The second area (13) also has the same structure as the first area 12. In this forming method, for example, the surface of the gate electrode 23 may be oxidized to form the insulating film 55 made of silicon oxide before removing the mask pattern 52 [see (2) in FIG. 3]. The insulating film 55 is used as the element isolation insulating film 14 when the conductive layer forming film 54 is polished.
It also serves as a polishing stopper.

Further, as shown in FIG. 6, the gate electrode 23
The upper layers of the first (second) conductive layers 33 and 34 (43, 44) may be silicidized. In FIG. 6, the first region 12 is shown as a representative. Since the second region 13 has the same configuration as the first region 12, the reference numerals of the components of the second region 13 are shown in parentheses.

As shown in FIG. 6, the first and second conductive layers 3
A metal silicide layer [for example, a titanium silicide (TiSi ₂ ) layer] 71, 7 is provided on each surface layer of 3, 34 (43, 44).
2 (73, 74) are formed. In addition, the gate electrode 2
A metal silicide layer [for example, a titanium silicide (TiSi ₂ ) layer] 75 is also formed on the surface layer of No. 3. By forming the metal silicide layers 71 to 75 in this manner, the resistance of the element is reduced.

In the forming method, as shown in FIG. 7A, for example, titanium (Ti) is deposited on the entire surface of the semiconductor substrate 11 by CVD or sputtering to form a titanium film 70. In addition, in (1) and (2) of FIG. 7, the first region 12 is shown as a representative, and the reference numerals of the components of the second region (13) having the same configuration as the first region 12 are ().
Shown in

Thereafter, as shown in FIG. 7B, the first (second) conductive layers 33 and 34 are formed by silicidation reaction.
The metal silicide layers 71, 72 (73, 74) and 75 made of titanium silicide are formed on the respective surface layers of (43, 44), and the metal silicide layer 75 made of titanium silicide is formed on the surface layer of the gate electrode 23. Then, on the element isolation insulating film 14 and the first and second insulating films 24, 25 (2
The unreacted titanium film 70 (the portion indicated by the chain double-dashed line) on 6, 27) is removed by, for example, wet etching.
When the insulating film is formed on the gate electrode 23 (see FIG. 5), the first (second) conductive layers 33, 34 (4
3, 44) only the respective surface layers are silicidized.

The metal silicide layers 71 to 75 are not limited to titanium silicide, and for example, a metal material such as cobalt can be used as a metal for forming silicide.

In the manufacturing method shown in FIG. 7, since the so-called stacked diffusion layer composed of the first (second) conductive layers 33, 34 (43, 44) is formed, the silicidation reaction is carried out. Of the semiconductor substrate 11 and the first (second) source / drain diffusion layers 31, 32 (4
1, 42), no junction breakdown occurs. Therefore, the reliability of the transistor can be improved. Further, since the respective surface layers of the first (second) conductive layers 33, 34 (43, 44) are silicidized, the resistance of the element can be reduced, and a transistor with high speed and low power consumption can be formed.

In the manufacturing method described with reference to FIGS. 2 to 7, the materials used as the first and second insulating films 24 to 27 and the insulating film 55 are not limited to the silicon oxide film, but may be nitrides (for example, nitrides). Any material may be used as long as it has an insulating property such as silicon) or nitride oxide (for example, silicon nitride oxide). In this case, the mask pattern 5
It is necessary to select a material having an etching selection ratio with respect to 2.

For example, as shown in (1) of FIG.
In the configuration in which the (second) insulating films 24, 25 (26, 27) are formed of silicon nitride, the first (second) conductive layer 3 is formed before the metal silicide layers 71 to 75 described in FIG. 7 are formed.
Oxide film 8 by oxidizing each surface of 3, 34 (43, 44)
1, 82 (83, 84) are formed. At this time, the surface of the gate electrode 23 is also oxidized and the oxide film 85 is formed.
Then, the oxide films 81 to 85 are selectively removed by etching the oxide film with hydrofluoric acid or the like, so that the first (second) conductive layers 33 and 34 are formed as shown in (2) of FIG.
The electrical insulation separation between (43, 44) and the gate electrode 23 is further ensured by the protrusion of the first (second) insulating films 24, 25 (26, 27).

Further, in the embodiment of the manufacturing method described with reference to FIGS. 2 to 8, the individual processes (for example, CVD, sputtering, lithography, etching, etc.) can be handled by existing processes, so that the process load is small.

[0047]

As described above, according to the semiconductor device of the present invention, the surface of the element isolation insulating film for separating the first and second regions for forming the element on the surface where the gate electrode is formed is the semiconductor substrate. Since the gate electrodes of the first and second regions are connected, the upper surface of the gate electrode and the uppermost surface of the element isolation insulating film are formed at almost the same height as the surface of the device. It becomes possible to do. And the first,
Since the surfaces of the second conductive layer, the gate electrode, and the element isolation insulating film are formed at almost the same height, it is possible to use an exposure method with a shallow depth of focus when forming wiring on them. become. Therefore, the wiring can be easily formed with high accuracy.

According to the manufacturing method of the present invention, the element isolation insulating film in the region where the gate electrode is to be formed is removed to a height almost equal to the surface of the semiconductor substrate, and then the element isolation insulating film is passed over the element isolation insulating film. Since the gate electrodes in the first and second regions are formed on the substrate, the respective surfaces of the gate electrode and the element isolation insulating film should be formed at substantially the same height while the gate electrodes in the first and second regions are connected. Will be possible. Then, after forming the conductive layer forming film, the conductive layer forming film is removed by using the element isolation insulating film as a stopper. Therefore, by performing the film forming step and the removing step, so-called self-alignment is performed. Layers can be formed. Therefore, since it is not necessary to perform a costly lithography process or an epitaxial growth process in this process, the manufacturing cost can be reduced. In addition, since the conductive layer forming film is formed and removed after the surfaces of the gate electrode and the element isolation insulating film are formed at substantially the same height, the conductive layer forming film is not left on both sides of the gate electrode. Absent. Therefore, the first and second conductive layers formed in the first and second regions are not short-circuited, so that the reliability of the semiconductor device can be improved.

[Brief description of drawings]

FIG. 1 is a schematic configuration sectional view of an embodiment of the present invention.

FIG. 2 is a manufacturing process diagram (1) of the embodiment of the present invention.

FIG. 3 is a manufacturing process diagram (2) of the embodiment of the present invention.

FIG. 4 is a manufacturing process diagram (3) of the embodiment of the present invention.

FIG. 5 is an explanatory diagram of an example in which an insulating film is formed on a gate electrode.

FIG. 6 is an explanatory diagram of an example of silicidation.

FIG. 7 is an explanatory diagram of a silicidation process.

FIG. 8 is an explanatory diagram of insulation separation by oxidation.

[Explanation of symbols]

 1 Semiconductor Device 11 Semiconductor Substrate 12 First Region 13 Second Region 14 Element Isolation Insulating Film 21 Gate Insulating Film 22 Gate Insulating Film 23 Gate Electrode 24 First Insulating Film 25 First Insulating Film 26 Second Insulating Film 27 Second Insulating Film 31 first source / drain region 32 first source / drain region 33 first conductive layer 34 first conductive layer 41 second source / drain region 42 second source / drain region 43 second conductive layer 44 second conductive layer

Claims (5)

[Claims] 1. A semiconductor substrate in which a first region and a second region for forming an element are separated by an element isolation insulating film, and a gate insulating film is provided on the first region and the second region. And a gate electrode formed on the element isolation insulating film, first source / drain regions formed on the semiconductor substrate in the first region on both sides of the gate electrode, and semiconductor substrates in the second region on both sides of the gate electrode. Formed second source / drain regions, first conductive layers connected to the first source / drain regions and formed on both sides of the gate electrode via a first insulating film, and the second source / drain regions. A semiconductor device having a second conductive layer which is connected to a drain region and is formed on both sides of the gate electrode with a second insulating film interposed therebetween, the element isolation insulation of a portion where the gate electrode is formed. The surface of the film and the surface of the semiconductor substrate are formed at substantially the same height, and the surfaces of the element isolation insulating film, the gate electrode, the first conductive layer, and the second conductive layer are substantially the same. A semiconductor device having a height. 2. An element isolation insulating film for isolating a first region and a second region, which are element forming regions, is formed on a semiconductor substrate, and subsequently passes over the element isolation insulating film, and on the first region and Second
After forming a mask pattern having an opening on the area where the gate electrode is to be formed, the element isolation insulating film exposed in the opening is almost equal to the surface of the semiconductor substrate. A first step of removing the gate insulating film to the height of the gate insulating film on the surface of the semiconductor substrate in the opening, and then forming a gate electrode so as to fill the opening and removing the mask pattern. A second step of forming the surface of the gate electrode and the uppermost surface of the element isolation insulating film at substantially the same height, and forming a first insulating film on the sidewall of the gate electrode in the first region and A second insulating film is formed on the side wall of the gate electrode in the second region, and first source / drain regions are formed in the semiconductor substrate in the first region on both sides of the gate electrode and in the semiconductor substrate in the second region. (2) A third step of forming source / drain regions; forming a conductive layer forming film on each of the first source / drain regions and on each of the second source / drain regions, and then stoppering the element isolation insulating film. As a result, a part of the conductive layer forming film is removed until the height becomes almost equal to that of the element isolation insulating film, and the first conductive layer connected to each first source / drain region and each second source / drain region are connected. And a fourth step of forming a second conductive layer to be connected to the semiconductor device. 3. The method for manufacturing a semiconductor device according to claim 2, wherein the removal of the conductive layer forming film is performed by polishing the conductive layer forming film using the element isolation insulating film as a polishing stopper. Manufacturing method of semiconductor device. 4. The method of manufacturing a semiconductor device according to claim 2, wherein after forming the first and second conductive layers in the fourth step, subsequently, the surface layers of the first and second conductive layers are oxidized. Forming a oxide layer, and then selectively removing the oxide layer. 5. The method of manufacturing a semiconductor device according to claim 3, wherein after forming the first and second conductive layers in the fourth step, subsequently, surface layers of the first and second conductive layers are oxidized. Forming a oxide layer, and then selectively removing the oxide layer.